Assertion Enable/Disable Example

assertion_enable_disable.sv

//design example
module design_module(
        input logic enable,
        input logic reset,
        input logic clk,
        output logic active);

    logic [1:0] fsm_cs;//current state
    logic [1:0] fsm_ns;//next state

    always @(posedge clk or posedge reset)
    begin
        if(reset)
            fsm_cs <= 2'b0;
        else
            fsm_cs <= fsm_ns;
    end

    always_comb
        case(fsm_cs)
            2'b00: if(enable==1'b1 && reset==1'b0)
                    fsm_ns=2'b1;
            2'b01: if(enable==1'b0 || reset==1'b1)
                    fsm_ns=2'b0;
            default: fsm_ns=2'b0;
        endcase

    assign active = (fsm_ns==2'b01) ? 1'b1:1'b0;

    property p_dummy();
        @(posedge clk)
         `uvm_error("design_module", "Property failed");
    endproperty

    DUMMY_ASSERT : assert property (p_dummy) `uvm_info(""design_module"", "DUMMY", UVM_HIGH)
    else `uvm_error("design_module", $sformatf("p_dummy failed"))

endmodule

//testbench top
module top();
    logic en,reset,tester_clk,active_out;
	
    initial
    begin
        tester_clk=1'b0;
        forever #10 tester_clk=~tester_clk;
    end

    design_module mydut(.enable(en),.reset(reset),.clk(tester_clk),.active(active_out));

    //switching off specific named assertion
    initial
    begin
        $assertoff(0,top.mydut.DUMMY_ASSERT);
    end
endmodule