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function void writing_binary_file(int unsigned total_bytes_to_write=32);
int fwrite;
bit [7:0] wdata;
//Open file with binary write mode("wb"), b here specifies binary
fwrite=$fopen("binary_file.bin","wb");
if(fwrite==0)
`uvm_error("NO_FILE_FOUND","Couldn't open file binary_file.bin for writing")
//iterate until all intended bytes are written
function void read_binary_file();
int fread;
bit [7:0] rdata;
int unsigned line_count;
line_count=0;
//Open file with binary read mode("rb"), b here specifies binary
fread=$fopen("binary_file.bin","rb");
if(fread==0)
`uvm_error("NO_FILE_FOUND","Couldn't open file binary_file.bin for reading")
@varunhuliyar
varunhuliyar / parse_file_systemverilog.sv
Last active June 7, 2024 14:03
Parsing file in Systemverilog
task parse_file_sv();
int samplefile;
string line_from_file, sub1;
real sub2;
string srcdir;
if($value$plusargs("SRCDIR=%s", srcdir))
`uvm_info(get_name(), $sformatf("+SRCDIR:%s",srcdir),UVM_MEDIUM)
else
`uvm_error(get_name(), $sformatf("+SRCDIR is not passed"));
@varunhuliyar
varunhuliyar / binding_assertion.sv
Created January 15, 2019 23:23
Binding Assertion Example
//design example
module design_module(
input logic enable,
input logic reset,
input logic clk,
output logic active);
logic [1:0] fsm_cs;//current state
logic [1:0] fsm_ns;//next state
@varunhuliyar
varunhuliyar / assertion_enable_disable.sv
Created January 15, 2019 23:18
Assertion Enable/Disable Example
//design example
module design_module(
input logic enable,
input logic reset,
input logic clk,
output logic active);
logic [1:0] fsm_cs;//current state
logic [1:0] fsm_ns;//next state
@varunhuliyar
varunhuliyar / icc2_useful_commands.txt
Created January 11, 2019 22:57
ICC2 Useful commands
#start GUI
icc_shell>start_gui
#report max transition constaints
icc_shell> report_constraint -max_transition -verbose
#report timing with transition with pins (through that pin)
icc_shell> report_timing -thr <instance_name>/<pin_name>