process_node_info.md

Typical process nodes by function

Block / Interface	Typical Per‑Lane Rate / Function	Realistic Process Nodes Seen in Practice	Notes
CPU cores (OOO, high‑perf)	Multi‑GHz scalar + wide SIMD	7 nm, 5 nm, 4 nm, 3 nm for new designs	Driven by power/area and competitive perf, not IO limits.
Low‑power CPU / MCUs	100s of MHz – low GHz	40 nm, 28 nm, 22 nm, 16 nm	Cost, leakage and NVM options dominate.
SATA 3.0 PHY	6 Gb/s NRZ	65 nm, 55 nm, 40 nm, 28 nm (TSMC & GF) [anysilicon]​	Commercial SATA 3 PHY IP explicitly offered in GF 40/55 nm and TSMC 65/28 nm.
PCIe 3.0 PHY	8 Gb/s NRZ	65 nm, 55 nm, 40 nm, 28 nmscribd+1	12.5 Gb/s multi‑standard SerDes shown in 40 nm low‑leakage CMOS (PCIe, SATA, USB3, 10G‑KR). [scribd]​
PCIe 4.0 PHY	16 Gb/s NRZ	28 nm, 16/14 nm, 12 nm, 7 nm design-reuse+1	IP vendors ship PCIe 4.0 SerDes PHY in 7 nm; also available at 16/28 nm for less aggressive SoCs.
PCIe 5.0 PHY	32 Gb/s NRZ	16/14 nm, 12 nm, 7 nm, 5 nm oiforum+1	High‑end IP marketed “in leading‑edge nodes (7 nm–3 nm)” but 16 nm is realistic for many ASICs.
PCIe 6.0 PHY	64 GT/s PAM4	7 nm, 5 nm, 4 nm, 3 nm; some 6 nm oiforum+2	5 nm test silicon for PCIe 6.0 PHY reported; commercial multi‑channel PCIe 6.0 PHY IP in 7 nm and below. eenewseurope+1
DDR4/LPDDR4 PHY	Up to ~3.2–4.2 Gb/s	28 nm, 22 nm, 16 nm	Similar class to PCIe 3/4 in speed; 28–16 nm common.
DDR5/LPDDR5 PHY	~6.4 Gb/s and up	16 nm, 12 nm, 7 nm	Needs better jitter and equalization; typically co‑located with high‑end CPU/GPU nodes.
1G/2.5G/TSN Ethernet PHY (1000BASE‑T, 100BASE‑T1, TSN)	1 Gb/s over copper	65 nm, 55 nm, 40 nm, 28 nm design-reuse-embedded+1	Automotive 10/100/1G PHY IP explicitly targeted at 28 nm for power and automotive integration. [design-reuse-embedded]​
10GBASE‑T / 10G‑KR SerDes	10 Gb/s NRZ	40 nm, 28 nm, 22 nm, 16 nm[scribd]​	12.5 Gb/s multi‑standard SerDes demonstrated in 40 nm; 28/16 nm for lower power and integration. [scribd]​
25G/50G SerDes (NRZ / PAM4)	25–56 Gb/s	28 nm (early), 22 nm, 16 nm, 7 nm	Many 28 nm demos, but production IP tends toward 16 nm and below for power/channel margin.
UFS 3.x / 4.0 M‑PHY (host/device)	Up to 23.2 Gb/s per lane (HS‑Gear5) [americas.kioxia]​	16/14 nm, 10/8 nm, 7 nm; some 28 nm at lower gears	UFS 4.0/4.1 uses M‑PHY 5.0 HS‑Gear5; high‑volume mobile controllers are on advanced mobile SoC nodes. semiconductor.samsung+1
USB 3.x / 3.2 PHY	5–20 Gb/s NRZ	65 nm, 55 nm, 40 nm, 28 nm [us.design-reuse]​	Synopsys USB3 PHY IP offered from 65 nm down to 28 nm.
USB4 / Thunderbolt‑class PHY	20–40 Gb/s	16 nm, 12 nm, 7 nm	Similar to PCIe 4/5 in SerDes complexity; typically on same node as high‑speed IO complex.
GMAC (1G), TSN MAC (no PHY)	Pure digital MAC	Any logic node: 65 nm → 3 nm	Synthesizable RTL; process choice driven purely by SoC integration cost and power.
Multi‑gig automotive Ethernet (2.5G/5G/10GBASE‑T1)	Up to 10 Gb/s over single pair	28 nm, 22 nm, 16 nm	Automotive suppliers target 28 nm for robustness, then move down for power/integration. design-reuse-embedded+1
Wi‑Fi RFIC (Wi‑Fi 5/6/7)	2.4/5/6 GHz RF front‑end + BB	65 nm RF CMOS, 40 nm RF, 28 nm RF; cutting edge at 16 nm RF	RF performance and cost drive this more than digital; often on its own RF‑optimized process.
On‑chip NoC / coherency fabric	1–3 GHz digital	Same as core logic node	Pure digital interconnect; follows CPU/GPU node.
SATA/PCIe multi‑standard SerDes (shared)	1–12.5 Gb/s multi‑protocol	40 nm, 28 nm, 22 nm [scribd]​	12.5 Gb/s TX in 40 nm low‑leakage CMOS shown, covering SATA, PCIe, USB3.1, 10G‑KR, JESD204B. [scribd]​