redbeard brianredbeard

## process_node_info.md

      
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    Typical process nodes by function


Block / Interface
Typical Per‑Lane Rate / Function
Realistic Process Nodes Seen in Practice
Notes


CPU cores (OOO, high‑perf)
Multi‑GHz scalar + wide SIMD
7 nm, 5 nm, 4 nm, 3 nm for new designs
Driven by power/area and competitive perf, not IO limits.


Low‑power CPU / MCUs
100s of MHz – low GHz
40 nm, 28 nm, 22 nm, 16 nm
Cost, leakage and NVM options dominate.


SATA 3.0 PHY
6 Gb/s NRZ
65 nm, 55 nm, 40 nm, 28 nm (TSMC & GF) [anysilicon]
Commercial SATA 3 PHY IP explicitly offered in GF 40/55 nm and TSMC 65/28 nm.


PCIe 3.0 PHY
8 Gb/s NRZ
65 nm, 55 nm, 40 nm, 28 nmscribd+1
12.5 Gb/s multi‑standard SerDes shown in 40 nm low‑leakage CMOS (PCIe, SATA, USB3, 10G‑KR). [scribd]


PCIe 4.0 PHY
16 Gb/


## rambly-audio-fix.user.js
// ==UserScript==
// @name         Rambly WebRTC Audio Fix
// @namespace    rambly-fix
// @version      1.0
// @description  Fixes permanent audio muting caused by replaceTrack(null) bug in distance-based optimization
// @match        https://rambly.app/*
// @grant        none
// @run-at       document-start
// ==/UserScript==

## README.md

      
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              July 27, 2025 02:23
            
              
                Playwright MCP running under systemd via podman
              
          
    About

This document outlines the configuration of a systemd unit designed to run the Playwright MCP server. The setup is opinionated, adhering to the Filesystem Hierarchy Standard (FHS) and the curated SELinux policies found in Fedora and Red Hat Enterprise Linux distributions.
Rootful Container Execution

This systemd unit runs the Playwright MCP container in "rootful" mode, meaning the container is managed by a podman process running as the root user. This is in contrast to Podman's default and more secure "rootless" mode, which allows non-privileged users to run containers. Running as root is a deliberate choice in this configuration, often necessitated by requirements like binding to privileged ports below 1024.
Networking and DNS


## draft_rfp.md

      
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              April 29, 2025 21:54
            
              
                package graph
              
          
    RISE TSC Project Proposal: Open Source Software Dependency & Code Analytics Tool (MVP)

Proposal Title: Development of an Open Source Software Dependency & Code Analytics Tool (MVP Phase)
Authors: Brian 'redbeard' Harrington
Date: April 29, 2025
Related Working Group: [Insert Relevant RISE Working Group, e.g., "Toolchain WG" or "Software Ecosystem WG"]

  
## aider_o3.md

      
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              May 2, 2025 00:38
            
              
                Aider Response coming from o3
              
          
    architect> /ask why is it that you keep insisting on speaking to me in Spanish or German?  What is causing this?
Nothing inside your repository is making me switch languages—the cause is on my side.

I’m instructed to reply in whichever language the user is using. The model decides which language that is by looking at the most recent user messages and guessing their predominant

language. If a previous turn of yours (or of another user in the same thread) was in Spanish or German, my heuristic may still “think” that’s the correct language and continue in it until

it notices enough English again. In short, it’s an over-eager language-detection heuristic, not anything in your codebase.

  
## vanity.c
#include <stdio.h>
#include <stdlib.h>
#include <string.h>
#include <ctype.h>
#include <openssl/sha.h>

#define TARGET_PREFIX "20250327"
#define MAX_WORDS 256
#define MAX_TEXT 2048
#define MAX_ATTEMPTS (1ULL << 32) // 2^32 attempts (~4.3B, enough for 8-char prefix)

## README.md

      
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                lspot.py
              
          
    list spot

a simple utility to quickly identify the cheapest spot location for an instance type
examples

❯ AWS_PROFILE=redbeard python3.11 lspot.py --help
usage: lspot.py [-h] [--json] [--table] [-v] [-1] [-r REGION] instance_type

  
## instructlab.txt
>>> Explain how the vector extension for RISC-V works.  Provide definitions of key concepts and components, how it works, and it's benefits.                                                                  [S][default]

╭─────────────────────────────────────────────────────────────────────────────────────────────── merlinite-7b-lab-Q4_K_M ────────────────────────────────────────────────────────────────────────────────────────────────╮
│ The vector extension for RISC-V is an enhancement to the RISC-V Instruction Set Architecture (ISA) that allows multiple operations to be performed on multiple data elements in parallel, thereby increasing the       │
│ throughput of calculations and improving performance in data-intensive applications. This extension introduces new vector registers, vector instructions, and data alignment concepts to optimize the processing of    │
│ vector data.

## gist:bc1cc2c591f3dc5168cf50c2e2a31758
❯ picocom -b 115200 /dev/ttyUSB0
picocom v3.1

port is        : /dev/ttyUSB0
flowcontrol    : none
baudrate is    : 115200
parity is      : none
databits are   : 8
stopbits are   : 1
escape is      : C-a

## shell.out
### Current Directory Structure (micropython submodule pruned)
❯ tree --gitignore
.
├── CMakeLists.txt
├── components
│   └── micropython
├── main
│   ├── CMakeLists.txt
│   ├── idf_component.yml
│   └── mp-test.c
Block / Interface	Typical Per‑Lane Rate / Function	Realistic Process Nodes Seen in Practice	Notes
CPU cores (OOO, high‑perf)	Multi‑GHz scalar + wide SIMD	7 nm, 5 nm, 4 nm, 3 nm for new designs	Driven by power/area and competitive perf, not IO limits.
Low‑power CPU / MCUs	100s of MHz – low GHz	40 nm, 28 nm, 22 nm, 16 nm	Cost, leakage and NVM options dominate.
SATA 3.0 PHY	6 Gb/s NRZ	65 nm, 55 nm, 40 nm, 28 nm (TSMC & GF) [anysilicon]	Commercial SATA 3 PHY IP explicitly offered in GF 40/55 nm and TSMC 65/28 nm.
PCIe 3.0 PHY	8 Gb/s NRZ	65 nm, 55 nm, 40 nm, 28 nmscribd+1	12.5 Gb/s multi‑standard SerDes shown in 40 nm low‑leakage CMOS (PCIe, SATA, USB3, 10G‑KR). [scribd]
PCIe 4.0 PHY	16 Gb/
	// ==UserScript==
	// @name Rambly WebRTC Audio Fix
	// @namespace rambly-fix
	// @version 1.0
	// @description Fixes permanent audio muting caused by replaceTrack(null) bug in distance-based optimization
	// @match https://rambly.app/*
	// @grant none
	// @run-at document-start
	// ==/UserScript==
	#include <stdio.h>
	#include <stdlib.h>
	#include <string.h>
	#include <ctype.h>
	#include <openssl/sha.h>

	#define TARGET_PREFIX "20250327"
	#define MAX_WORDS 256
	#define MAX_TEXT 2048
	#define MAX_ATTEMPTS (1ULL << 32) // 2^32 attempts (~4.3B, enough for 8-char prefix)
	>>> Explain how the vector extension for RISC-V works. Provide definitions of key concepts and components, how it works, and it's benefits. [S][default]

	╭─────────────────────────────────────────────────────────────────────────────────────────────── merlinite-7b-lab-Q4_K_M ────────────────────────────────────────────────────────────────────────────────────────────────╮
	│ The vector extension for RISC-V is an enhancement to the RISC-V Instruction Set Architecture (ISA) that allows multiple operations to be performed on multiple data elements in parallel, thereby increasing the │
	│ throughput of calculations and improving performance in data-intensive applications. This extension introduces new vector registers, vector instructions, and data alignment concepts to optimize the processing of │
	│ vector data.
	❯ picocom -b 115200 /dev/ttyUSB0
	picocom v3.1

	port is : /dev/ttyUSB0
	flowcontrol : none
	baudrate is : 115200
	parity is : none
	databits are : 8
	stopbits are : 1
	escape is : C-a
	### Current Directory Structure (micropython submodule pruned)
	❯ tree --gitignore
	.
	├── CMakeLists.txt
	├── components
	│ └── micropython
	├── main
	│ ├── CMakeLists.txt
	│ ├── idf_component.yml
	│ └── mp-test.c