Added two signed signal and check if the result is overflow or underflow.

signed_add_signed.sv

/// Signed extension macro. The add_width must be larger than 1.
`define SIGNEXT(signal, from_width, add_width) {{(add_width){signal[(from_width)-1]}}, signal}

/// Unsigned extension macro. The add_width must be larger than 1.
`define ZEROEXT(signal, from_width, add_width) {{(add_width){1'b0}}, signal}

module value_adder #(BITS=16) (
    input logic [BITS-1:0] a, // Unsigned.
    input logic [BITS-1:0] b, // Signed.
    output logic [BITS-1:0] c,
    output logic overflow,
    output logic underflow
);
    logic [BITS+1:0] sum;
    
    sum = `SIGNEXT(a, BITS, 1) + `SIGNEXT(b, BITS, 1);
    c[BITS-1:0] = sum[BITS-1:0];
    underflow = a[BITS-1] & b[BITS-1] & ~sum[BITS-1];
    overflow = ~a[BITS-1] & ~b[BITS-1] & sum[BITS-1];
endmodule