GaryLee

import collections.abc
from typing import Any, Dict, Iterator, Union

class ReadOnlyMergedDict(collections.abc.Mapping):
    """
    A read-only merged dictionary class that can merge multiple dict-like objects
    """
    
    def __init__(self, *dicts: Dict[Any, Any]):
        """

GaryLee

/// Signed extension macro. The add_width must be larger than 1.
`define SIGNEXT(signal, from_width, add_width) {{(add_width){signal[(from_width)-1]}}, signal}

/// Unsigned extension macro. The add_width must be larger than 1.
`define ZEROEXT(signal, from_width, add_width) {{(add_width){1'b0}}, signal}

module value_adder #(BITS=16) (
    input logic [BITS-1:0] a, // Unsigned.
    input logic [BITS-1:0] b, // Signed.
    output logic [BITS-1:0] c,

GaryLee

/// Signed extension macro. The add_width must be larger than 1.
`define SIGNEXT(signal, from_width, add_width) {{(add_width){signal[(from_width)-1]}}, signal}

/// Unsigned extension macro. The add_width must be larger than 1.
`define ZEROEXT(signal, from_width, add_width) {{(add_width){1'b0}}, signal}

module value_adder #(BITS=16) (
    input logic [BITS-1:0] a, // Unsigned.
    input logic [BITS-1:0] b, // Signed.
    output logic [BITS-1:0] c,

GaryLee

#!python
# coding: utf-8
"""
Utility functions for comment-based code generation.

Single line code generation:
- Lines starting with the specified print symbol (default: '//? ') within the block are treated as f-string of Python.
- The leading spaces of f-string lines is for indentation in Python code. Not the generated code.
- The generated code is inserted into the output at the position of the code generation block.

GaryLee

# Following line can be added to your .?shrc file.
export PATH=`python -c "print(':'.join(dict.fromkeys('''$PATH'''.split(':'))))"`

GaryLee

#!/usr/bin/env python
# -*- coding: utf-8 -*-

import os
import sys
from pathlib import Path
import platform
import xml.etree.ElementTree as ET

# Define the output figure format. Could be 'svg', 'png', 'pdf', etc.

GaryLee

// Problem: https://hdlbits.01xz.net/wiki/Fsm_serialdp.
module top_module(
    input clk,
    input in,
    input reset,    // Synchronous reset
    output [7:0] out_byte,
    output done
); //
	parameter START = 4'd0, BIT0 = 4'd1, BIT1 = 4'd2, BIT2 = 4'd3, BIT3 = 4'd4, 
    		  BIT4 = 4'd5, BIT5 = 4'd6, BIT6 = 4'd7, BIT7 = 4'd8, PARITY = 4'd9,

GaryLee

// Problem: https://hdlbits.01xz.net/wiki/Fsm_serialdata
module top_module(
    input clk,
    input in,
    input reset,    // Synchronous reset
    output [7:0] out_byte,
    output done
); //
	parameter START = 4'd0, BIT0 = 4'd1, BIT1 = 4'd2, BIT2 = 4'd3, BIT3 = 4'd4, 
    		  BIT4 = 4'd5, BIT5 = 4'd6, BIT6 = 4'd7, BIT7 = 4'd8,  STOP = 4'd9,

GaryLee

module counter #(parameter BGN, parameter END, parameter LOAD=0) (
    input clk,
    input reset,
    input ena,
    output c,
    output [7:0] d
	);
    logic c0, c1;
    assign c0 = (d[3:0] == 4'd9);
	assign c = ena & (d == 8'(END)); // AND `ena` here to make sure `c` is set when previous digit is counting.

GaryLee

module top_module (
    input [7:0] a,
    input [7:0] b,
    output [7:0] s,
    output overflow
);
    logic c;
    assign {c, s} = a + b;
    assign overflow = ~(a[7] ^ b[7]) & (c ^ s[7]);
endmodule