- Launch Synplify Premier:
> module load base synplify
> synplify_premier- Import RTL and constraints with
File→Build Project - Open compile options with
Options→Configure Verilog Compiler - Check box for
Use DesignWare Foundation Library - Set the
Design Compiler Install Location. This should be the Synopsys folder that has subfoldersdw,doc,libraries, etc. - Compile with
Run→Run