The HP48 LCD is a 131x64 dot matrix STN display combined with a 6x1 display for annunciators. The Saturn CPU drives data from it's internal memory out to the display one row at a time, refreshing rows at a 4096Hz rate and the entire screen at a 64Hz rate.
The columns (segments) of the dot matrix display are driven by a pair of SED1181 64-segment drivers daisy chained together along with a small additional internal shift register driving the additional 3 columns. The 64 rows (common) of the dot matrix display are driven by the Saturn itself, which ends up functioning identically to the SED1191. In order to simplify this document, it's written as if the rows were driven by a SED1191. The display is driven by a voltage swing of up to V+ (about 10V) to ground (0V). The voltage range varies based on the contrast setting and includes several intermediate voltages to properly drive the display.
The annunciators are driven by the Saturn CPU itself, with a 5V voltage swing.
- SED1181 Datasheet
- SED1191 Datasheet
- HP49G Schematic
- Guide to the Saturn Processor
- Images of HP48 LCD
- This Document
The framebuffer can be segmented between a menu area and a primary display. Registers within the Saturn point to the memory area for each, a long with a register indicating how many rows to draw in the primary area before switching to the menu area.
Each line is 17 bytes long with bits packed LSB first. The first 16 bytes contain data for columns 1-128. Only the first three bits of the final byte represent display pixels (columns 129-131). Two additional bits are included in the serial output but are ignored.
The read of each line from RAM happens at the maximum possible rate, nominally 1MHz, taking about 17us, utilizing the memory bus about 7% of the time. Because the CPU (and memory bus) clock can vary quite widely, but the LCD bus is much more accurate, this percentage will be higher for slower CPU clock rates, and lower for faster rates.
The logical interface drives the internal row driver, the external column drivers (SED1181) and the LCD output signals attached to the card 1 slot.
The logic signal voltages are referenced between the SED1181 VDD (V+) and
the SED1181 VSS (VCC). In practice measured levels for a V+ of 9.5V and
VCC of 5V are around 4.2V for a low output and 8.8V for a high output. The
datasheet indicates it must be at least 0.8 * (VDD - VSS) + VSS, or around
8.6V. and a logic low must be at most 0.2 * (VDD - VSS) + VSS or around
5.9V. Note that the logic low is below the datasheet minimum of VSS - 0.3V
or 4.7V.
The output voltages for the driving the LCD are calculated by a ratio between
VDD and VSSH given by the relation: VSSH + N * (VDD - VSSH) / 9. The
values are given by the following tables (FR alternates between frames, the
first table is for frames with FR=0 and the second for frames with FR=1):
FR=0 |
Level | Row Idle | Row Active |
|---|---|---|---|
| Level | V4 1/9 |
VDD 9/9 |
|
| Column Idle | V3 2/9 |
-1/9 | 7/9 |
| Column Active | VSSH 0/9 |
1/9 | 9/9 |
FR=1 |
Level | Row Idle | Row Active |
|---|---|---|---|
| Level | V1 8/9 |
VSSH 0/9 |
|
| Column Idle | V2 7/9 |
1/9 | -7/9 |
| Column Active | VDD 9/9 |
-1/9 | -9/9 |
The annunciators have two simple voltage levels for both the row and columns of 0V and 5V.
The line pulse starts the scan out process. It's an approximately 1us active high pulse whose falling edge signals to the SED1191 to cycle to the next row and for the SED1181 to transition the current line from internal shift registers to parallel output.
The Saturn processor responds to a line pulse by reading in the current line
from RAM and then within a few clock cycles begins shifting the data
out via D0 and D1, clocking with XSCL.
Additionally, every 64th line pulse, the frame signal (FR) transitions from
high to low or low to high. Both the Saturn CPU and the SED1191 begin at row
1 following a frame signal transition.
The data clock shifts serial row data from the CPU into the column driver
serial shift registers via D0 and D1. The SED1181 allows this signal to be
driven at up to 6MHz (166ns per cycle), but the Saturn drives this at around
550 kHz, or about 1.8us per cycle. Both D0 and D1 are first shifted
through an internal 3 bit shift register before going out to the first SED1181,
U8, and then to the second, U9, for a total chain length of 67 bits.
Note that because a pair of 3 bit shift registers exist internal to the Saturn, the first three bits shifted out are from the last line. New line data (column 1/2) begin with the 4th bit.
The frame signal alternates high/low with each frame. This is to signal drivers to reverse the potential across LCD cells to eliminate any DC bias. DC bias will slowly damage any LCD cells, leaving them permanently on or off.
This signal also signals to the Saturn row driver to begin at row 1 and that data should be read starting at row 1.
If you have an issue with an LCD that causes any row or column to stay on or off, continuing to use the device in this state may cause permanent damage to the affected rows or columns due to a possible DC bias.
These are the row data serial shift lines. Please note that the SED1181 D0
signal is for the segment 0 to 31 outputs and the D1 signal is for the
segment 32 to 63 outputs. Please note that data is shifted out with the first
bit going to D1 and thus labeled LD(0)/LCDd1 in schematics and the
second bit going to D0 and is labeled LD(1)/LCDd2.
Inside the Saturn, the first bit shifted out is column 1 (LD(0)) and column
2 (LD(1)). The 66th bit shifted out is column 131 (D1) and column 132
(LD(1)). The 67th bit shifted out (the final bit) is column 133 (LD(0))
and a bit that is always 1 (LD(1)). This last always 1 bit is possibly the
row drive for the annunciators but is difficult to confirm. Note that while
columns 132 and 133 exist within the frame buffer and are shifted out, they
appear to be unused.
The actual LD(0) and LD(1) outputs from the Saturn CPU are delayed by 3
cycles due to the internal shift registers. So the first three bits to come
out are the last three bits from the previous row (columns 129-133 and the
always 1 bit). The first and second column start with the 4th bit.
This is the logic high level for the SED1181 and is tied to V+,
approximately 10 volts.
This voltage is also used for the row driver active state when FR is low
and the column driver active state when FR is high.
This is the logic low level for the SED1181 and is tied to VCC,
approximately 5 volts.
This is an internal voltage for the row driver idle state voltage when FR
is high. This voltage is equal to VSSH + 8 * (VDD - VSSH) / 9.
This is the column driver idle state voltage when FR is high. Note that V2
and V3 are multiplexed together and are switched between by the FR signal.
This voltage is equal to VSSH + 7 * (VDD - VSSH) / 9.
This is the column driver idle state voltage when FR is low. This voltage is
equal to VSSH + 2 * (VDD - VSSH) / 9.
This is an internal voltage for the row driver idle state voltage when FR
is low. This voltage is equal to VSSH + 1 * (VDD - VSSH) / 9.
This voltage is used for the row driver active state when FR is high and the
column driver active state when FR is low. This voltage is adjusted lower
when contrast is adjust up, and higher when contrast is adjusted down. The
voltage between VSS and VSSH is the total voltage swing across the LCD.
The remaining voltages are at fixed ratios between these two values.
With a measured V+ of 9.6V, the following voltages are observed:
| Contrast | VSSH |
VDD - VSSH |
|---|---|---|
| Minimum | 1.56V | 8.0V |
| Default | 0.56V | 9.0V |
| Maximum | 0.0V | 9.56V |
The annunciators are driven by 16 * 64Hz (1024Hz) signal. The signal consists of 4 pulses, followed by 4 idle states (5V high, 0V low):
| Signal | |
|---|---|
| Row | #_#_#_#_________ |
| Column Idle | #_#_#_#_________ |
| Column Active | ________#_#_#_#_ |
Thus for an idle column, the voltage across the element is always 0V. For an active column, the voltage difference pulses 4 times at 5V, and then 4 times at -5V.
The LCD is connected via 137 column drivers (including 6 for annunciators) and 65 row drivers (including 1 for annunciators) for a total of 202 signals. Schematics typically number these as V1 to V105 for signals across the top and V201 to V299 (skipping V202 and V298, unpopulated pads on the PCB) across the bottom. Note that these are numbered from left to right when viewing the pads on the back of the PCB and from the front of the calculator.
| LCD | Row | Column | SED1181 (U8) | SED1181 (U9) | Saturn |
|---|---|---|---|---|---|
| V1 | 16 | 35 | |||
| V2 | 15 | 34 | |||
| V3 | 14 | 33 | |||
| V4 | 13 | 32 | |||
| V5 | 12 | 31 | |||
| V6 | 11 | 30 | |||
| V7 | 10 | 29 | |||
| V8 | 9 | 28 | |||
| V9 | 8 | 27 | |||
| V10 | 7 | 26 | |||
| V11 | 6 | 25 | |||
| V12 | 5 | 24 | |||
| V13 | 4 | 23 | |||
| V14 | 3 | 22 | |||
| V15 | 2 | 21 | |||
| V16 | 1 | 20 | |||
| V17 | A1 | 152 | |||
| V18 | 1 | 68 (seg63) | |||
| V19 | 3 | 67 (seg62) | |||
| V20 | 5 | 66 (seg61) | |||
| V21 | 7 | 65 (seg60) | |||
| V22 | 9 | 64 (seg59) | |||
| V23 | A1 | 153 | |||
| V24 | 11 | 63 (seg58) | |||
| V25 | 13 | 62 (seg57) | |||
| V26 | 15 | 61 (seg56) | |||
| V27 | 17 | 60 (seg55) | |||
| V28 | 19 | 59 (seg54) | |||
| V29 | 21 | 58 (seg53) | |||
| V30 | 23 | 57 (seg52) | |||
| V31 | 25 | 56 (seg51) | |||
| V32 | 27 | 55 (seg50) | |||
| V33 | 29 | 54 (seg49) | |||
| V34 | 31 | 53 (seg48) | |||
| V35 | A2 | 154 | |||
| V36 | 33 | 52 (seg47) | |||
| V37 | 35 | 51 (seg46) | |||
| V38 | 37 | 50 (seg45) | |||
| V39 | 39 | 49 (seg44) | |||
| V40 | 41 | 48 (seg43) | |||
| V41 | 43 | 47 (seg42) | |||
| V42 | 45 | 46 (seg41) | |||
| V43 | 47 | 45 (seg40) | |||
| V44 | 49 | 44 (seg39) | |||
| V45 | 51 | 43 (seg38) | |||
| V46 | 53 | 42 (seg37) | |||
| V47 | 55 | 41 (seg36) | |||
| V48 | A3 | 155 | |||
| V49 | 57 | 40 (seg35) | |||
| V50 | 59 | 39 (seg34) | |||
| V51 | 61 | 38 (seg33) | |||
| V52 | 63 | 37 (seg32) | |||
| V53 | 65 | 68 (seg63) | |||
| V54 | 67 | 67 (seg62) | |||
| V55 | 69 | 66 (seg61) | |||
| V56 | 71 | 65 (seg60) | |||
| V57 | 73 | 64 (seg59) | |||
| V58 | 75 | 63 (seg58) | |||
| V59 | A4 | 156 | |||
| V60 | 77 | 62 (seg57) | |||
| V61 | 79 | 61 (seg56) | |||
| V62 | 81 | 60 (seg55) | |||
| V63 | 83 | 59 (seg54) | |||
| V64 | 85 | 58 (seg53) | |||
| V65 | 87 | 57 (seg52) | |||
| V66 | 89 | 56 (seg51) | |||
| V67 | 91 | 55 (seg50) | |||
| V68 | 93 | 54 (seg49) | |||
| V69 | 95 | 53 (seg48) | |||
| V70 | 97 | 52 (seg47) | |||
| V71 | 99 | 51 (seg46) | |||
| V72 | A5 | 40,157 | |||
| V73 | 101 | 50 (seg45) | |||
| V74 | 103 | 49 (seg44) | |||
| V75 | 105 | 48 (seg43) | |||
| V76 | 107 | 47 (seg42) | |||
| V77 | 109 | 46 (seg41) | |||
| V78 | 111 | 45 (seg40) | |||
| V79 | 113 | 44 (seg39) | |||
| V80 | 115 | 43 (seg38) | |||
| V81 | 117 | 42 (seg37) | |||
| V82 | 119 | 41 (seg36) | |||
| V83 | 121 | 40 (seg35) | |||
| V84 | A6 | 39,158 | |||
| V85 | 123 | 39 (seg34) | |||
| V86 | 125 | 38 (seg33) | |||
| V87 | 127 | 37 (seg32) | |||
| V88 | 129 | 139 | |||
| V89 | 131 | 141 | |||
| V90 | 17 | 41 | |||
| V91 | 18 | 42 | |||
| V92 | 19 | 43 | |||
| V93 | 20 | 44 | |||
| V94 | 21 | 45 | |||
| V95 | 22 | 46 | |||
| V96 | 23 | 47 | |||
| V97 | 24 | 48 | |||
| V98 | 25 | 49 | |||
| V99 | 26 | 50 | |||
| V100 | 27 | 51 | |||
| V101 | 28 | 52 | |||
| V102 | 29 | 53 | |||
| V103 | 30 | 54 | |||
| V104 | 31 | 55 | |||
| V105 | 32 | 56 |
| LCD | Row | Column | SED1181 (U8) | SED1181 (U9) | Saturn |
|---|---|---|---|---|---|
| V201 | 33 | 19 | |||
| V202 | |||||
| V203 | 34 | 18 | |||
| V204 | 35 | 17 | |||
| V205 | 36 | 16 | |||
| V206 | 37 | 15 | |||
| V207 | 38 | 14 | |||
| V208 | 39 | 13 | |||
| V209 | 40 | 12 | |||
| V210 | 41 | 11 | |||
| V211 | 42 | 10 | |||
| V212 | 43 | 9 | |||
| V213 | 44 | 8 | |||
| V214 | 45 | 7 | |||
| V215 | 46 | 6 | |||
| V216 | 47 | 5 | |||
| V217 | 48 | 4 | |||
| V218 | 2 | 77 (seg31) | |||
| V219 | 4 | 78 (seg30) | |||
| V220 | 6 | 79 (seg29) | |||
| V221 | 8 | 80 (seg28) | |||
| V222 | 10 | 1 (seg27) | |||
| V223 | 12 | 2 (seg26) | |||
| V224 | 14 | 3 (seg25) | |||
| V225 | 16 | 4 (seg24) | |||
| V226 | 18 | 5 (seg23) | |||
| V227 | 20 | 6 (seg22) | |||
| V228 | 22 | 7 (seg21) | |||
| V229 | 24 | 8 (seg20) | |||
| V230 | 26 | 9 (seg19) | |||
| V231 | 28 | 10 (seg18) | |||
| V232 | 30 | 11 (seg17) | |||
| V233 | 32 | 12 (seg16) | |||
| V234 | 34 | 13 (seg15) | |||
| V235 | 36 | 14 (seg14) | |||
| V236 | 38 | 15 (seg13) | |||
| V237 | 40 | 16 (seg12) | |||
| V238 | 42 | 17 (seg11) | |||
| V239 | 44 | 18 (seg10) | |||
| V240 | 46 | 19 (seg9) | |||
| V241 | 48 | 20 (seg8) | |||
| V242 | 50 | 21 (seg7) | |||
| V243 | 52 | 22 (seg6) | |||
| V244 | 54 | 23 (seg5) | |||
| V245 | 56 | 24 (seg4) | |||
| V246 | 58 | 25 (seg3) | |||
| V247 | 60 | 26 (seg2) | |||
| V248 | 62 | 27 (seg1) | |||
| V249 | 64 | 28 (seg0) | |||
| V250 | 66 | 77 (seg31) | |||
| V251 | 68 | 78 (seg30) | |||
| V252 | 70 | 79 (seg29) | |||
| V253 | 72 | 80 (seg28) | |||
| V254 | 74 | 1 (seg27) | |||
| V255 | 76 | 2 (seg26) | |||
| V256 | 78 | 3 (seg25) | |||
| V257 | 80 | 4 (seg24) | |||
| V258 | 82 | 5 (seg23) | |||
| V259 | 84 | 6 (seg22) | |||
| V260 | 86 | 7 (seg21) | |||
| V261 | 88 | 8 (seg20) | |||
| V262 | 90 | 9 (seg19) | |||
| V263 | 92 | 10 (seg18) | |||
| V264 | 94 | 11 (seg17) | |||
| V265 | 96 | 12 (seg16) | |||
| V266 | 98 | 13 (seg15) | |||
| V267 | 100 | 14 (seg14) | |||
| V268 | 102 | 15 (seg13) | |||
| V269 | 104 | 16 (seg12) | |||
| V270 | 106 | 17 (seg11) | |||
| V271 | 108 | 18 (seg10) | |||
| V272 | 110 | 19 (seg9) | |||
| V273 | 112 | 20 (seg8) | |||
| V274 | 114 | 21 (seg7) | |||
| V275 | 116 | 22 (seg6) | |||
| V276 | 118 | 23 (seg5) | |||
| V277 | 120 | 24 (seg4) | |||
| V278 | 122 | 25 (seg3) | |||
| V279 | 124 | 26 (seg2) | |||
| V280 | 126 | 27 (seg1) | |||
| V281 | 128 | 28 (seg0) | |||
| V282 | 130 | 140 | |||
| V283 | 64 | 72 | |||
| V284 | 63 | 71 | |||
| V285 | 62 | 70 | |||
| V286 | 61 | 69 | |||
| V287 | 60 | 68 | |||
| V288 | 59 | 67 | |||
| V289 | 58 | 66 | |||
| V290 | 57 | 65 | |||
| V291 | 56 | 64 | |||
| V292 | 55 | 63 | |||
| V293 | 54 | 62 | |||
| V294 | 53 | 61 | |||
| V295 | 52 | 60 | |||
| V296 | 51 | 59 | |||
| V297 | 50 | 58 | |||
| V298 | |||||
| V299 | 49 | 57 |
The annunciator columns are:
| Column | Name |
|---|---|
| A1 | Left Shift |
| A2 | Right Shift |
| A3 | Alpha |
| A4 | Low Battery |
| A5 | Busy |
| A6 | IO |
The total viewable area of the metal window in 66.3mm x 39.1mm. The display area of the LCD is ~61.5mm x ~30.2mm. This gives a resolution of approximately 2.12 pixels/mm. The top margin is ~6.4mm. The total horizontal space within the metal frame is 74mm x 49mm and the space available at the top is 5.2mm.
Special thanks to Matthew Mastracci, author of the definitive Guide to the Saturn Processor, Marcos Navarro, who produced excellent photos of an HP48 LCD allowing me to verify my row/column mappings as well as die photos providing confirmation that the row driver is built into the Saturn, and Marcel Flipse for creating the HP48G/GX schematic.
Written by Russ Dill, licensed under the CC BY 4.0.