luojia65

use std::{env, path::PathBuf};

fn main() {
    let out = PathBuf::from(env::var_os("OUT_DIR").unwrap());
    let ld = &out.join("artinchip-rt.ld");

    std::fs::write(ld, LINKER_SCRIPT).unwrap();

    println!("cargo:rustc-link-arg=-T{}", ld.display());
    println!("cargo:rustc-link-search={}", out.display());

luojia65

#!/usr/bin/env python3
# -*- coding: utf-8 -*-
import struct

INPUT = "input.txt"   # 空格/换行分隔的hex字节
OUTPUT = "output.txt" # 可选：写回更新后的头部（同样以hex格式输出）

def read_hex_bytes(path: str) -> bytearray:
    data = bytearray()
    with open(path, "r", encoding="utf-8") as f:

luojia65

// lib.rs

#![no_std]

pub mod host;
pub mod guest;

#[cfg(test)]
mod tests {
    // 参考：sbi-spec

luojia65

[RustSBI] INFO  - Hello RustSBI!

[RustSBI] INFO  - RustSBI version 0.4.0

[RustSBI] INFO  - .______       __    __      _______.___________.  _______..______   __

[RustSBI] INFO  - |   _  \     |  |  |  |    /       |           | /       ||   _  \ |  |

[RustSBI] INFO  - |  |_)  |    |  |  |  |   |   (----`---|  |----`|   (----`|  |_)  ||  |

luojia65

use allwinner_hal::ccu::{self, ClockConfig, DramClockSource, FactorN};
use allwinner_rt::soc::d1::{CCU, PHY};
use core::ptr::{read_volatile, write_volatile};

// for verbose prints
const VERBOSE: bool = false;

pub const RAM_BASE: usize = 0x40000000;

// p49 ff

luojia65

/// A memory mapping from virtual address space to physical ones.
pub trait AddressMapping {
    /// Iterator of physical parts on this memory mapping system.
    type Window<P>: Iterator<Item = P>;
    /// Address translation errors, e.g. page faults.
    type Error;
    /// Maps reference of a virtual object into a set of physical parts.
    fn map<P: Virtual>(&self, virt_ref: P) -> Result<Self::Window<Part<P>>, Self::Error>;
}

luojia65

## -- modules --
axi // bus
uart
spi
i2c
usb
radio

## -- structs --
McuSystem { uart: &'static Uart, }

luojia65

From 249a3b13d121523be55c3262ba7e7defd446f368 Mon Sep 17 00:00:00 2001
From: Phil Edworthy <phil.edworthy@renesas.com>
Date: Wed, 2 Nov 2016 11:14:36 +0000
Subject: [PATCH] ddr: Add driver for Cadence DDR Controller

The controller supports DDR2 and DDR3 using 8 or 16-bit bus width.
When using 16-bit wide data, the controller can be configured to
use 8-bit data and 8-bit ECC.

Signed-off-by: Phil Edworthy <phil.edworthy@renesas.com>

luojia65

#!/usr/bin/env bash
# Original author: @junkdog. Modified by @luojia65.

#     --slave /usr/bin/$1 $1 /usr/bin/$1-\${version} \\

function register_clang_version {
    local version=$1
    local priority=$2

    update-alternatives \

luojia65

/// Runtime dynamic SIMD value
/// 
/// This structure a wrap of an unsized slice, whose memory layout varies by architecture
/// under #[repr(simd)].
/// 
/// In RISC-V, this type represents a group of elements to be processed in application,
/// or VL number of T values. Length of current vector is placed in separate vector length
/// CSR register `vl`.
#[repr(simd)]
pub struct DynSimd<T>([T]);