Useful functions to enable GPIO 5 interrupt, and accompanying interrupt handler, for ESP32S3 ULP core (not yet mainlined)

esp_hal_rs_ulp_gpio_interrupt_gist.rs

// Required to shadow the weakly-linked ulp_irq_handler
// that is defined by esp-lp-hal.
#[link_name = "ulp_irq_handler"]
#[unsafe(link_section = ".init")]
#[unsafe(no_mangle)]
extern "C" fn ulp_irq_handler(q1: u32) {
    /* Internal Interrupts */
    if (q1 & 0b1) > 0 {
        // TODO
    }
    /* External/Peripheral interrupts */
    if (q1 & 0x80000000) > 0 {
        /* RTC Peripheral interrupts */
        let cocpu_int_st: u32 = unsafe { &*esp_lp_hal::pac::SENS::PTR }
            .sar_cocpu_int_st()
            .read()
            .bits();
        if cocpu_int_st > 0 {
            // Clear the interrupt
            unsafe { &*esp_lp_hal::pac::SENS::PTR }
                .sar_cocpu_int_clr()
                .write(|w| unsafe { w.bits(cocpu_int_st) });
        }
        /* RTC IO interrupts */
        let rtcio_int_st: u32 = unsafe { &*esp_lp_hal::pac::RTC_IO::PTR }
            .status()
            .read()
            .bits();
        if rtcio_int_st > 0 {

            // Check bit 5 (lshift by 10) is set
            if rtcio_int_st & (1 << 15) > 0 {
                // GPIO5 interrupt happened!!! Do something!!!!!!
            }

            // Clear the interrupt
            unsafe { &*esp_lp_hal::pac::RTC_IO::PTR }
                .status_w1tc()
                .write(|w| unsafe { w.bits(rtcio_int_st) });
        }
    }
}

// Call this in your main()
fn enable_gpio_intr() {
    // RTC_GPIO_PINn_PAD_DRIVER (R/W)
    //   Pin driver selection.
    //   0: normal output
    //   1: open drain.

    // RTC_GPIO_PINn_INT_TYPE (R/W)
    // GPIO interrupt type selection.
    //   0: GPIO interrupt disabled
    //   1: rising edge trigger
    //   2: falling edge trigger
    //   3: any edge trigger
    //   4: low level trigger
    //   5: high level trigger.

    // RTC_GPIO_PINn_WAKEUP_ENABLE (R/W)
    //   GPIO wake-up enable. This will only wake up the chip from Light-sleep.
    unsafe { &*esp_lp_hal::pac::RTC_IO::PTR }
        .pin5()
        .write(|w| unsafe { w.int_type().bits(2) });
}