Extract I/O Port and Parameters of a given SV file

io_param_extraction.py

# pip install pyverilog

from pyverilog.vparser.ast import Inout, Input, Localparam, ModuleDef, Output, Parameter, Supply
from pyverilog.vparser.parser import VerilogCodeParser

parser = VerilogCodeParser([])

# Hack: Get rid of the icarus verilog dependency

# Place your Verilog in a lambda function
# Replace it with text reading and merging
parser.preprocess = lambda: """
module top #(
    parameter FUGU = 1
)(
    input logic [3:0] a,
    input logic [3:0] b,
    output logic [3:0]c[0:1]
);
  localparam SWIM = 1;
  assign c = a & b;
endmodule
"""

ast = parser.parse()


def bfs_over_ast(source, node_type):
    search_list = [source]
    result = []
    while search_list:
        node = search_list.pop()
        if isinstance(node, node_type):
            result.append(node)
        else:
            search_list += node.children()
    return result


modules = bfs_over_ast(ast, ModuleDef)
io_param_result = {
    module.name: [
        node for node in
        bfs_over_ast(module, (Input, Output, Inout, Parameter))
        if not isinstance(node, (Localparam, Supply))
    ]
    for module in modules
}

for mod_name, entires in io_param_result.items():
    print(f"=========={mod_name}==========")
    for entry in entires:
        entry.show()