gistfile1.txt

# EFM8 Busy Bee Family EFM8BB1 Data Sheet

The EFM8BB1, part of the Busy Bee family of MCUs, is a multipurpose line of 8-bit microcontrollers with a comprehensive feature set in small packages.

These devices offer high-value by integrating advanced analog and communication peripherals into small packages, making them ideal for space-constrained applications. With an efficient 8051 core, enhanced pulse-width modulation, and precision analog, the EFM8BB1 family is also optimal for embedded applications.

## EFM8BB1 Applications
- Motor control
- Consumer electronics
- Sensor controllers
- Medical equipment
- Lighting systems
- I/O port expander

## Key Features
- Pipelined 8-bit C8051 core with 25 MHz maximum operating frequency
- Up to 18 multifunction, 5 V tolerant I/O pins
- One 12-bit Analog to Digital Converter (ADC)
- Two low-current analog comparators
- Integrated temperature sensor
- 3-channel enhanced PWM / PCA
- Four 16-bit timers
- UART, SPI, and SMBus/I2C
- Priority crossbar for flexible pin mapping

**Lowest power mode with peripheral operational:**
- Normal: 10 s
- Shutdown: (unspecified in excerpt)

---

# 1. Feature List

The EFM8BB1 highlighted features are listed below.

### Core
- Pipelined CIP-51 Core
- Fully compatible with standard 8051 instruction set
- 70% of instructions execute in 1-2 clock cycles
- 25 MHz maximum operating frequency

### Memory
- Up to 8 kB flash memory, in-system re-programmable from firmware
- Up to 512 bytes RAM (including 256 bytes standard 8051 RAM and 256 bytes on-chip XRAM)

### Power
- Internal LDO regulator for CPU core voltage
- Power-on reset circuit and brownout detectors

### I/O
- Up to 18 total multifunction I/O pins:
  - All pins 5 V tolerant under bias
  - Flexible peripheral crossbar for peripheral routing
  - 5 mA source, 12.5 mA sink allows direct drive of LEDs

### Clock Sources
- Internal 24.5 MHz oscillator with ±2% accuracy
- Internal 80 kHz low-frequency oscillator
- External CMOS clock option

### Timers/Counters and PWM
- 3-channel programmable counter array (PCA) supporting PWM, capture/compare, and frequency output modes
- 4 × 16-bit general-purpose timers
- Independent watchdog timer, clocked from the low frequency oscillator

### Communications and Digital Peripherals
- UART
- SPI™ Master / Slave
- SMBus™ / I2C™ Master / Slave
- 16-bit CRC unit, supporting automatic CRC of flash at 256-byte boundaries

### Analog
- 12-Bit Analog-to-Digital Converter (ADC)
- 2 × Low-current analog comparators with adjustable reference
- On-Chip, Non-Intrusive Debugging
- Full memory and register inspection
- Four hardware breakpoints, single-stepping
- Pre-loaded UART bootloader

### Additional Specifications
- Temperature range: -40 to 85°C or -40 to 125°C
- Single power supply: 2.2 to 3.6 V
- Packages: QSOP24, SOIC16, and QFN20

With on-chip power-on reset, voltage supply monitor, watchdog timer, and clock oscillator, the EFM8BB1 devices are truly standalone system-on-a-chip solutions. The flash memory is reprogrammable in-circuit, providing non-volatile data storage and allowing field upgrades of the firmware. The on-chip debugging interface (C2) allows non-intrusive, full-speed, in-circuit debugging using the production MCU installed in the final application. This debug logic supports inspection and modification of memory and registers, setting breakpoints, single stepping, and run and halt commands. All analog and digital peripherals are fully functional while debugging. Each device is specified for 2.2 to 3.6 V operation and is AEC-Q100 qualified. Both G-grade and I-grade devices are available in 20-pin QFN, 16-pin SOIC, or 24-pin QSOP packages, and A-grade devices are available in the 20-pin QFN package. All package options are lead-free and RoHS compliant.

---

# 2. Ordering Information

## Figure 2.1. EFM8BB1 Part Numbering
*(Refer to the original document for the figure.)*

All EFM8BB1 family members have the following features:
- CIP-51 Core running up to 25 MHz
- Two Internal Oscillators (24.5 MHz and 80 kHz)
- SMBus / I2C
- SPI
- UART
- 3-Channel Programmable Counter Array (PWM, Clock Generation, Capture/Compare)
- 4 16-bit Timers
- 2 Analog Comparators
- 12-bit Analog-to-Digital Converter with integrated multiplexer, voltage reference, and temperature sensor
- 16-bit CRC Unit
- AEC-Q100 qualified
- Pre-loaded UART bootloader

### Table 2.1. Product Selection Guide

| Part Number            | Flash (kB) | RAM (bytes) | I/O Pins | ADC Inputs | CMP0 Inputs | CMP1 Inputs | AEC-Q100 | Temp Range    | Package |
|-----------------------|------------|-------------|----------|------------|-------------|-------------|----------|---------------|---------|
| EFM8BB10F8G-A-QSOP24 | 8          | 512         | 18       | 16         | 8           | 8           | Yes      | -40 to +85°C  | QSOP24  |
| EFM8BB10F8G-A-QFN20  | 8          | 512         | 16       | 15         | 8           | 7           | Yes      | -40 to +85°C  | QFN20   |
| EFM8BB10F8G-A-SOIC16 | 8          | 512         | 13       | 12         | 6           | 7           | Yes      | -40 to +85°C  | SOIC16  |
| EFM8BB10F4G-A-QFN20  | 4          | 512         | 16       | 15         | 8           | 7           | Yes      | -40 to +85°C  | QFN20   |
| EFM8BB10F2G-A-QFN20  | 2          | 256         | 16       | 15         | 8           | 7           | Yes      | -40 to +85°C  | QFN20   |
| EFM8BB10F8I-A-QSOP24 | 8          | 512         | 18       | 16         | 8           | 8           | Yes      | -40 to +125°C | QSOP24  |
| EFM8BB10F8I-A-QFN20  | 8          | 512         | 16       | 15         | 8           | 7           | Yes      | -40 to +125°C | QFN20   |
| EFM8BB10F8I-A-SOIC16 | 8          | 512         | 13       | 12         | 6           | 6           | Yes      | -40 to +125°C | SOIC16  |
| EFM8BB10F4I-A-QFN20  | 4          | 512         | 16       | 15         | 8           | 7           | Yes      | -40 to +125°C | QFN20   |
| EFM8BB10F2I-A-QFN20  | 2          | 256         | 16       | 15         | 8           | 7           | Yes      | -40 to +125°C | QFN20   |
| EFM8BB10F8A-A-QFN20  | 8          | 512         | 16       | 15         | 8           | 7           | Yes      | -40 to +125°C | QFN20   |
| EFM8BB10F4A-A-QFN20  | 4          | 512         | 16       | 15         | 8           | 7           | Yes      | -40 to +125°C | QFN20   |
| EFM8BB10F2A-A-QFN20  | 2          | 256         | 16       | 15         | 8           | 7           | Yes      | -40 to +125°C | QFN20   |

**Note:**
1. End of life for QSOP24 packages.

The A-grade devices (e.g., EFM8BB10F8A-A-QFN20) receive full automotive quality production status, including AEC-Q100 qualification, registration with International Material Data System (IMDS), and Part Production Approval Process (PPAP) documentation. PPAP documentation is available at [www.silabs.com](https://www.silabs.com) with a registered and NDA-approved user account.

---

# 3. System Overview

## 3.1 Introduction

*(Refer to Figure 3.1. Detailed EFM8BB1 Block Diagram in the original document.)*

This section describes the EFM8BB1 family at a high level. For more information on the device packages and pinout, electrical specifications, and typical connection diagrams, see the EFM8BB1 Data Sheet. For more information on each module including register definitions, see the EFM8BB1 Reference Manual. For more information on any errata, see the EFM8BB1 Errata.

## 3.2 Power

All internal circuitry draws power from the VDD supply pin. External I/O pins are powered from the VIO supply voltage (or VDD on devices without a separate VIO connection), while most of the internal circuitry is supplied by an on-chip LDO regulator. Control over the device power can be achieved by enabling/disabling individual peripherals as needed. Each analog peripheral can be disabled when not in use and placed in low power mode. Digital peripherals, such as timers and serial buses, have their clocks gated off and draw little power when they are not in use.

### Table 3.1. Power Modes

| Power Mode | Details                                                                 | Mode Entry                          | Wake-Up Sources      |
|------------|------------------------------------------------------------------------|-------------------------------------|----------------------|
| Normal     | Core and all peripherals clocked and fully operational                | -                                   | -                    |
| Idle       | - Core halted<br>- All peripherals clocked and fully operational<br>- Code resumes execution on wake event | Set IDLE bit in PCONO | Any interrupt        |
| Stop       | - All internal power nets shut down<br>- Pins retain state<br>- Exit on any reset source | 1. Clear STOPCF bit in REGOCN<br>2. Set STOP bit in PCONO | Any reset source     |
| Shutdown   | - All internal power nets shut down<br>- Pins retain state<br>- Exit on pin or power-on reset | 1. Set STOPCF bit in REGOCN<br>2. Set STOP bit in PCONO | - RSTb pin reset<br>- Power-on reset |

## 3.3 I/O

Digital and analog resources are externally available on the device's multi-purpose I/O pins. Port pins P0.0-P1.7 can be defined as general-purpose I/O (GPIO), assigned to one of the internal digital resources through the crossbar or dedicated channels, or assigned to an analog function. Port pins P2.0 and P2.1 can be used as GPIO. Additionally, the C2 Interface Data signal (C2D) is shared with P2.0.

- Up to 18 multi-function I/O pins, supporting digital and analog functions
- Flexible priority crossbar decoder for digital peripheral assignment
- Two drive strength settings for each port
- Two direct-pin interrupt sources with dedicated interrupt vectors (INT0 and INT1)
- Up to 16 direct-pin interrupt sources with shared interrupt vector (Port Match)

## 3.4 Clocking

The CPU core and peripheral subsystem may be clocked by both internal and external oscillator resources. By default, the system clock comes up running from the 24.5 MHz oscillator divided by 8.

- Provides clock to core and peripherals
- 24.5 MHz internal oscillator (HFOSCO), accurate to ±2% over supply and temperature corners
- 80 kHz low-frequency oscillator (LFOSCO)
- External CMOS clock input (EXTCLK)
- Clock divider with eight settings for flexible clock scaling: Divide the selected clock source by 1, 2, 4, 8, 16, 32, 64, or 128

## 3.5 Counters/Timers and PWM

### Programmable Counter Array (PCA0)
The programmable counter array (PCA) provides multiple channels of enhanced timer and PWM functionality while requiring less CPU intervention than standard counter/timers. The PCA consists of a dedicated 16-bit counter/timer and one 16-bit capture/compare module for each channel.

- 16-bit time base
- Programmable clock divisor and clock source selection
- Up to three independently-configurable channels
- 8, 9, 10, 11, and 16-bit PWM modes (center or edge-aligned operation)
- Output polarity control
- Frequency output mode
- Capture on rising, falling, or any edge
- Compare function for arbitrary waveform generation
- Software timer (internal compare) mode
- Can accept hardware "kill" signal from comparator 0

### Timers (Timer 0, Timer 1, Timer 2, and Timer 3)
Several counter/timers are included in the device: two are 16-bit counter/timers compatible with those found in the standard 8051, and the rest are 16-bit auto-reload timers for timing peripherals or for general purpose use.

#### Timer 0 and Timer 1 Features:
- Standard 8051 timers, supporting backwards-compatibility with firmware and hardware
- Clock sources: SYSCLK, SYSCLK divided by 12, 4, or 48, External Clock divided by 8, or an external pin
- 8-bit auto-reload counter/timer mode
- 13-bit counter/timer mode
- 16-bit counter/timer mode
- Dual 8-bit counter/timer mode (Timer 0)

#### Timer 2 and Timer 3 Features:
- Clock sources: SYSCLK, SYSCLK divided by 12, or External Clock divided by 8
- 16-bit auto-reload timer mode
- Dual 8-bit auto-reload timer mode
- External pin capture (Timer 2)
- LFOSCO capture (Timer 3)

### Watchdog Timer (WDT0)
The device includes a programmable watchdog timer (WDT) running off the low-frequency oscillator.

- Programmable timeout interval
- Runs from the low-frequency oscillator
- Lock-out feature to prevent any modification until a system reset

## 3.6 Communications and Other Digital Peripherals

### Universal Asynchronous Receiver/Transmitter (UART0)
UART0 is an asynchronous, full duplex serial port offering modes 1 and 3 of the standard 8051 UART.

- Asynchronous transmissions and receptions
- Baud rates up to SYSCLK/2 (transmit) or SYSCLK/8 (receive)
- 8- or 9-bit data
- Automatic start and stop generation
- Single-byte FIFO on transmit and receive

### Serial Peripheral Interface (SPI0)
The serial peripheral interface (SPI) module provides access to a flexible, full-duplex synchronous serial bus.

- Supports 3- or 4-wire operation in master or slave modes
- Supports external clock frequencies up to SYSCLK/2 in master mode and SYSCLK/10 in slave mode
- Support for four clock phase and polarity options
- 8-bit dedicated clock rate generator
- Support for multiple masters on the same data lines

### System Management Bus / I2C (SMB0)
The SMBus I/O interface is a two-wire, bi-directional serial bus compliant with System Management Bus Specification, version 1.1, and compatible with the I²C serial bus.

- Standard (up to 100 kbps) and Fast (400 kbps) transfer speeds
- Support for leader, follower, and multi-leader modes
- Hardware synchronization and arbitration for multi-leader mode
- Clock low extending (clock stretching) to interface with faster leaders
- Hardware support for 7-bit follower and general call address recognition
- Firmware support for 10-bit follower address decoding
- Ability to inhibit all follower states
- Programmable data setup/hold times

### 16-bit CRC (CRC0)
The cyclic redundancy check (CRC) module performs a CRC using a 16-bit polynomial.

- Support for CCITT-16 polynomial (0x1021)
- Byte-level bit reversal
- Automatic CRC of flash contents on one or more 256-byte blocks
- Initial seed selection of 0x0000 or 0xFFFF

## 3.7 Analog

### 12-Bit Analog-to-Digital Converter (ADC0)
The ADC is a successive-approximation-register (SAR) ADC with 12-, 10-, and 8-bit modes.

- Up to 16 external inputs
- Single-ended 12-bit and 10-bit modes
- Supports an output update rate of 200 ksps in 12-bit mode or 800 ksps in 10-bit mode
- Operation in low power modes at lower conversion speeds
- Asynchronous hardware conversion trigger, selectable between software, external I/O, and internal timer sources
- Output data window comparator allows automatic range checking
- Support for burst mode
- Conversion complete and window compare interrupts supported
- Flexible output data formatting
- Includes an internal fast-settling reference with two levels (1.65 V and 2.4 V) and support for external reference
- Integrated temperature sensor

### Low Current Comparators (CMP0, CMP1)
Analog comparators compare the voltage of two analog inputs, with a digital output indicating which input voltage is higher.

- Up to 8 external positive inputs
- Up to 8 external negative inputs
- Additional input options: Internal connection to LDO output, Direct connection to GND
- Synchronous and asynchronous outputs can be routed to pins via crossbar
- Programmable hysteresis between 0 and ±20 mV
- Programmable response time
- Interrupts generated on rising, falling, or both edges

## 3.8 Reset Sources

Reset circuitry allows the controller to be placed in a predefined default condition.

- Power-on reset
- External reset pin
- Comparator reset
- Software-triggered reset
- Supply monitor reset (monitors VDD supply)
- Watchdog timer reset
- Missing clock detector reset
- Flash error reset

## 3.9 Debugging

The EFM8BB1 devices include an on-chip Silicon Labs 2-Wire (C2) debug interface for flash programming and in-system debugging.

## 3.10 Bootloader

All devices come pre-programmed with a UART bootloader residing in the code security page.

- **Bootloader Signature Byte**: Set to 0xA5 to indicate presence; any other value indicates absence.
- When present, the device jumps to the bootloader vector after any reset.
- Silicon Labs recommends disabling and locking the bootloader after production programming for code security.

### Figure 3.2. Flash Memory Map with Bootloader-8 KB Devices
*(Refer to the original document for the figure.)*

### Table 3.2. Summary of Pins for Bootloader Communication

| Bootloader | Pins for Bootload Communication |
|------------|---------------------------------|
| UART       | TX - P0.4<br>RX - P0.5         |

### Table 3.3. Summary of Pins for Bootload Mode Entry

| Device Package | Pin for Bootload Mode Entry |
|----------------|-----------------------------|
| QSOP24         | P2.0/C2D                    |
| QFN20          | P2.0/C2D                    |
| SOIC16         | P2.0/C2D                    |

More information is available in AN945: EFM8 Factory Bootloader User Guide at [www.silabs.com/8bit-appnotes](https://www.silabs.com/8bit-appnotes).

---

# 4. Electrical Specifications

## 4.1 Electrical Characteristics

### 4.1.1 Recommended Operating Conditions

#### Table 4.1. Recommended Operating Conditions

| Parameter                      | Symbol   | Test Condition         | Min  | Typ | Max  | Unit |
|-------------------------------|----------|------------------------|------|-----|------|------|
| Operating Supply Voltage on VDD | VDD     |                        | 2.2  | -   | 3.6  | V    |
| System Clock Frequency        | f<sub>SYSCLK</sub> |             | 0    | -   | 25   | MHz  |
| Operating Ambient Temperature | T<sub>A</sub> | G-grade devices | -40  | -   | 85   | °C   |
|                               |          | I-grade or A-grade devices | -40 | -   | 125  | °C   |

**Note:**
1. All voltages with respect to GND.
2. GPIO levels are undefined whenever VDD is less than 1 V.

### 4.1.2 Power Consumption

#### Table 4.2. Power Consumption

| Parameter                                      | Symbol | Test Condition                                    | Min | Typ   | Max   | Unit |
|-----------------------------------------------|--------|--------------------------------------------------|-----|-------|-------|------|
| **Digital Core Supply Current (G-grade, -40°C to +85°C)** |        |                                                  |     |       |       |      |
| Normal Mode - Full speed with code executing from flash | I<sub>DD</sub> | F<sub>SYSCLK</sub> = 24.5 MHz² | -   | 4.45  | 4.85  | mA   |
|                                               |        | F<sub>SYSCLK</sub> = 1.53 MHz² | -   | 915   | 1150  | µA   |
|                                               |        | F<sub>SYSCLK</sub> = 80 kHz³, T<sub>A</sub> = 25°C | - | 250 | 290 | µA   |
|                                               |        | F<sub>SYSCLK</sub> = 80 kHz³             | -   | 250   | 380   | µA   |
| Idle Mode - Core halted with peripherals running | I<sub>DD</sub> | F<sub>SYSCLK</sub> = 24.5 MHz² | -   | 2.05  | 2.3   | mA   |
|                                               |        | F<sub>SYSCLK</sub> = 1.53 MHz² | -   | 550   | 700   | µA   |
|                                               |        | F<sub>SYSCLK</sub> = 80 kHz³, T<sub>A</sub> = 25°C | - | 125 | 130 | µA   |
|                                               |        | F<sub>SYSCLK</sub> = 80 kHz³             | -   | 125   | 200   | µA   |
| Stop Mode - Core halted, all clocks stopped, LDO On, Supply monitor off | I<sub>DD</sub> | T<sub>A</sub> = 25°C | - | 105 | 120 | µA   |
|                                               |        | T<sub>A</sub> = -40 to +85°C            | -   | 105   | 170   | µA   |
| Shutdown Mode - Core halted, all clocks stopped, LDO Off, Supply monitor off | I<sub>DD</sub> |                        | -   | 0.2   | -     | µA   |
| **Digital Core Supply Current (I-grade or A-grade, -40°C to +125°C)** |        |                                                  |     |       |       |      |
| Normal Mode - Full speed with code executing from flash | I<sub>DD</sub> | F<sub>SYSCLK</sub> = 24.5 MHz² | -   | 4.45  | 5.25  | mA   |
|                                               |        | F<sub>SYSCLK</sub> = 1.53 MHz² | -   | 915   | 1600  | µA   |
|                                               |        | F<sub>SYSCLK</sub> = 80 kHz³, T<sub>A</sub> = 25°C | - | 250 | 290 | µA   |
|                                               |        | F<sub>SYSCLK</sub> = 80 kHz³             | -   | 250   | 725   | µA   |
| Idle Mode - Core halted with peripherals running | I<sub>DD</sub> | F<sub>SYSCLK</sub> = 24.5 MHz² | -   | 2.05  | 2.6   | mA   |
|                                               |        | F<sub>SYSCLK</sub> = 1.53 MHz² | -   | 550   | 1000  | µA   |
|                                               |        | F<sub>SYSCLK</sub> = 80 kHz³, T<sub>A</sub> = 25°C | - | 125 | 130 | µA   |
|                                               |        | F<sub>SYSCLK</sub> = 80 kHz³             | -   | 125   | 550   | µA   |
| Stop Mode - Core halted, all clocks stopped, LDO On, Supply monitor off | I<sub>DD</sub> | T<sub>A</sub> = 25°C | - | 105 | 120 | µA   |
|                                               |        | T<sub>A</sub> = -40 to +125°C           | -   | 105   | 270   | µA   |
| Shutdown Mode - Core halted, all clocks stopped, LDO Off, Supply monitor off | I<sub>DD</sub> |                        | -   | 0.2   | -     | µA   |
| **Analog Peripheral Supply Currents (-40°C to +125°C)** |        |                                                  |     |       |       |      |
| High-Frequency Oscillator                    | I<sub>HFOSC</sub> | Operating at 24.5 MHz, T<sub>A</sub> = 25°C | - | 155 | - | µA   |
| Low-Frequency Oscillator                     | I<sub>LFOSC</sub> | Operating at 80 kHz, T<sub>A</sub> = 25°C | - | 3.5 | - | µA   |
| ADC0 Always-on ⁴                              | I<sub>ADC</sub> | 800 ksps, 10-bit or 200 ksps, 12-bit, Normal bias, V<sub>DD</sub> = 3.0 V | - | 845 | 1200 | µA |
|                                               |        | 250 ksps, 10-bit or 62.5 ksps, 12-bit, Low power bias, V<sub>DD</sub> = 3.0 V | - | 425 | 580 | µA |
| ADC0 Burst Mode, 10-bit, external reference  | I<sub>ADC</sub> | 200 ksps, V<sub>DD</sub> = 3.0 V | - | 370 | - | µA   |
|                                               |        | 100 ksps, V<sub>DD</sub> = 3.0 V | - | 185 | - | µA   |
|                                               |        | 10 ksps, V<sub>DD</sub> = 3.0 V  | - | 19  | - | µA   |
| ADC0 Burst Mode, 10-bit, internal reference, Low power bias | I<sub>ADC</sub> | 200 ksps, V<sub>DD</sub> = 3.0 V | - | 490 | - | µA |
|                                               |        | 100 ksps, V<sub>DD</sub> = 3.0 V | - | 245 | - | µA   |
| ADC0 Burst Mode, 12-bit, external reference  | I<sub>ADC</sub> | 100 ksps, V<sub>DD</sub> = 3.0 V | - | 23  | - | µA   |
|                                               |        | 50 ksps, V<sub>DD</sub> = 3.0 V  | - | 530 | - | µA   |
|                                               |        | 50 ksps, V<sub>DD</sub> = 3.0 V  | - | 265 | - | µA   |
| ADC0 Burst Mode, 12-bit, internal reference  | I<sub>ADC</sub> | 100 ksps, V<sub>DD</sub> = 3.0 V, Normal bias | - | 950 | - | µA |
|                                               |        | 50 ksps, V<sub>DD</sub> = 3.0 V, Low power bias | - | 420 | - | µA |
|                                               |        | 10 ksps, V<sub>DD</sub> = 3.0 V, Low power bias | - | 85  | - | µA   |
| Internal ADC0 Reference, Always-on ⁵         | I<sub>VREFFS</sub> | Normal Power Mode            | -   | 680   | 790   | µA   |
|                                               |        | Low Power Mode                  | -   | 160   | 210   | µA   |
| Temperature Sensor                           | I<sub>TSENSE</sub> |                        | -   | 75    | 120   | µA   |
| Comparator 0 (CMP0), Comparator 1 (CMP1)    | I<sub>CMP</sub> | CPMD = 11                   | -   | 0.5   | -     | µA   |
|                                               |        | CPMD = 10                   | -   | 3     | -     | µA   |
|                                               |        | CPMD = 01                   | -   | 10    | -     | µA   |
|                                               |        | CPMD = 00                   | -   | 25    | -     | µA   |
| Voltage Supply Monitor (VMON0)               | I<sub>VMON</sub> |                        | -   | 15    | 20    | µA   |

**Note:**
1. Currents are additive.
2. Includes supply current from internal regulator, supply monitor, and High Frequency Oscillator.
3. Includes supply current from internal regulator, supply monitor, and Low Frequency Oscillator.
4. ADC0 always-on power excludes internal reference supply current.
5. The internal reference is enabled as-needed in burst mode to save power.

### 4.1.3 Reset and Supply Monitor

#### Table 4.3. Reset and Supply Monitor

| Parameter                              | Symbol   | Test Condition                          | Min  | Typ | Max  | Unit |
|---------------------------------------|----------|----------------------------------------|------|-----|------|------|
| VDD Supply Monitor Threshold         | V<sub>VDDM</sub> |                                | 1.85¹ | 1.95 | 2.1 | V    |
| Power-On Reset (POR) Threshold        | V<sub>POR</sub> | Rising Voltage on V<sub>DD</sub> | -    | 1.4 | -    | V    |
|                                       |          | Falling Voltage on V<sub>DD</sub> | 0.75 | -   | 1.36 | V    |
| VDD Ramp Time                         | t<sub>RMP</sub> | Time to V<sub>DD</sub> ≥ 2.2 V | 10   | -   | -    | µs   |
| Reset Delay from POR                  | t<sub>POR</sub> | Relative to V<sub>DD</sub> ≥ V<sub>POR</sub> | 3 | 10 | 31 | ms   |
| Reset Delay from non-POR source       | t<sub>RST</sub> | Time between release of reset source and code execution | - | 39 | - | µs   |
| RST Low Time to Generate Reset        | t<sub>RSTL</sub> |                                | 15   | -   | -    | µs   |
| Missing Clock Detector Response Time  | t<sub>MCD</sub> | F<sub>SYSCLK</sub> > 1 MHz     | -    | 0.625 | 1.2 | ms   |
| Missing Clock Detector Trigger Frequency | F<sub>MCD</sub> |                             | -    | 7.5 | 13.5 | kHz  |
| VDD Supply Monitor Turn-On Time       | t<sub>MON</sub> |                                | -    | 2   | -    | µs   |

**Note:**
1. MCU core, digital logic, flash memory, and RAM operation is guaranteed down to the minimum VDD Supply Monitor Threshold.

### 4.1.4 Flash Memory

#### Table 4.4. Flash Memory

| Parameter                    | Symbol   | Test Condition                          | Min  | Typ  | Max  | Units |
|-----------------------------|----------|----------------------------------------|------|------|------|-------|
| Write Time¹,²               | t<sub>WRITE</sub> | One Byte, F<sub>SYSCLK</sub> = 24.5 MHz | 19 | 20  | 21  | µs    |
| Erase Time¹,²               | t<sub>ERASE</sub> | One Page, F<sub>SYSCLK</sub> = 24.5 MHz | 5.2 | 5.35 | 5.5 | ms    |
| VDD Voltage During Programming³ | V<sub>PROG</sub> |                             | 2.2  | -   | 3.6  | V     |
| Endurance (Write/Erase Cycles) | N<sub>WE</sub> |                             | 20k  | 100k | -   | Cycles |
| CRC Calculation Time        | t<sub>CRC</sub> | One 256-Byte Block, SYSCLK = 24.5 MHz | -  | 11  | -   | µs    |

**Note:**
1. Does not include sequencing time before and after the write/erase operation.
2. Internal High-Frequency Oscillator must be between 22 and 25 MHz during flash write/erase.
3. Flash can be safely programmed at any voltage above the supply monitor threshold (V<sub>VDDM</sub>).
4. Data Retention Information is published in the Quarterly Quality and Reliability Report.

### 4.1.5 Internal Oscillators

#### Table 4.5. Internal Oscillators

| Parameter                    | Symbol   | Test Condition                          | Min  | Typ  | Max  | Unit |
|-----------------------------|----------|----------------------------------------|------|------|------|------|
| **High Frequency Oscillator 0 (24.5 MHz)** |          |                                        |      |      |      |      |
| Oscillator Frequency        | f<sub>HFOSCO</sub> | Full Temp and Supply Range | 24   | 24.5 | 25   | MHz  |
| Power Supply Sensitivity    | PSS<sub>HFOSCO</sub> | T<sub>A</sub> = 25°C     | -    | 0.5  | -    | %/V  |
| Temperature Sensitivity     | TS<sub>HFOSCO</sub> | V<sub>DD</sub> = 3.0 V  | -    | 40   | -    | ppm/°C |
| **Low Frequency Oscillator (80 kHz)** |          |                                        |      |      |      |      |
| Oscillator Frequency        | f<sub>LFOSC</sub> | Full Temp and Supply Range | 75   | 80   | 85   | kHz  |
| Power Supply Sensitivity    | PSS<sub>LFOSC</sub> | T<sub>A</sub> = 25°C     | -    | 0.05 | -    | %/V  |
| Temperature Sensitivity     | TS<sub>LFOSC</sub> | V<sub>DD</sub> = 3.0 V  | -    | 65   | -    | ppm/°C |

### 4.1.6 External Clock Input

#### Table 4.6. External Clock Input

| Parameter                    | Symbol   | Test Condition                          | Min  | Typ  | Max  | Unit |
|-----------------------------|----------|----------------------------------------|------|------|------|------|
| External Input CMOS Clock Frequency | f<sub>CMOS</sub> |                        | 0    | -    | 25   | MHz  |
| External Input CMOS Clock High Time | t<sub>CMOSH</sub> |                       | 18   | -    | -    | ns   |
| External Input CMOS Clock Low Time | t<sub>CMOSL</sub> |                        | 18   | -    | -    | ns   |

### 4.1.7 ADC

#### Table 4.7. ADC

| Parameter                    | Symbol   | Test Condition                          | Min  | Typ  | Max  | Unit |
|-----------------------------|----------|----------------------------------------|------|------|------|------|
| Resolution                  | N<sub>bits</sub> | 12 Bit Mode             | 12   | -    | -    | Bits |
|                             |          | 10 Bit Mode             | 10   | -    | -    | Bits |
| Throughput Rate (High Speed Mode) | f<sub>S</sub> | 12 Bit Mode       | -    | -    | 200  | ksps |
|                             |          | 10 Bit Mode             | -    | -    | 800  | ksps |
| Throughput Rate (Low Power Mode) | f<sub>S</sub> | 12 Bit Mode        | -    | -    | 62.5 | ksps |
|                             |          | 10 Bit Mode             | -    | -    | 250  | ksps |
| Tracking Time               | t<sub>TRK</sub> | High Speed Mode       | 230  | -    | -    | ns   |
|                             |          | Low Power Mode          | 450  | -    | -    | ns   |
| Power-On Time               | t<sub>PWR</sub> |                        | 1.2  | -    | -    | µs   |
| SAR Clock Frequency         | f<sub>SAR</sub> | High Speed Mode, Ref = 2.4 V internal | - | - | 6.25 | MHz  |
|                             |          | High Speed Mode, Ref ≠ 2.4 V internal | - | - | 12.5 | MHz  |
|                             |          | Low Power Mode          | -    | -    | 4    | MHz  |
| Conversion Time             | t<sub>CNV</sub> | 10-Bit, SAR Clock = 12.25 MHz, SYSCLK = 24.5 MHz | - | - | - | µs   |
| Sample/Hold Capacitor       | C<sub>SAR</sub> | Gain = 1              | -    | 5    | -    | pF   |
|                             |          | Gain = 0.5              | -    | 2.5  | -    | pF   |
| Input Pin Capacitance       | C<sub>IN</sub> |                         | -    | 20   | -    | pF   |
| Input Mux Impedance         | R<sub>MUX</sub> |                        | -    | 550  | -    | Ω    |
| Voltage Reference Range     | V<sub>REF</sub> |                        | 1    | -    | V<sub>DD</sub> | V |
| Input Voltage Range*        | V<sub>IN</sub> | Gain = 1               | 0    | -    | V<sub>REF</sub> | V |
|                             |          | Gain = 0.5              | 0    | -    | 2 × V<sub>REF</sub> | V |
| Power Supply Rejection Ratio | PSRR<sub>ADC</sub> |                     | -    | 70   | -    | dB   |
| **DC Performance**          |          |                                        |      |      |      |      |
| Integral Nonlinearity       | INL      | 12 Bit Mode             | -    | ±1   | ±2.3 | LSB  |
|                             |          | 10 Bit Mode             | -    | ±0.2 | ±0.6 | LSB  |
| Differential Nonlinearity   | DNL      | 12 Bit Mode             | -1   | ±0.7 | 1.9  | LSB  |
|                             |          | 10 Bit Mode             | -    | ±0.2 | ±0.6 | LSB  |
| Offset Error                | E<sub>OFF</sub> | 12 Bit Mode, VREF = 1.65 V | -3 | 0 | 3 | LSB  |
|                             |          | 10 Bit Mode, VREF = 1.65 V | -2 | 0 | 2 | LSB  |
| Offset Temperature Coefficient | TC<sub>OFF</sub> |                    | -    | 0.004 | -   | LSB/°C |

*(Note: Additional subsections like 4.1.8 to 4.1.13, 5. Typical Connection Diagrams) are omitted for brevity but follow a similar table structure in the original document.)*

---

# 6. Pin Definitions

## 6.1 EFM8BB1x-QSOP24 Pin Definitions

*(Refer to Figure 6.1 in the original document for the pinout.)*

### Table 6.1. Pin Definitions for EFM8BB1x-QSOP24

| Pin Number | Pin Name | Description         | Crossbar Capability | Additional Digital Functions | Analog Functions          |
|------------|----------|---------------------|---------------------|-----------------------------|---------------------------|
| 1          | P0.0     | Multifunction I/O   | Yes                 | P0MAT.0, INT0.0, INT1.0     | ADC0.0, CMP0P.0, CMP0N.0, VREF |
| 2          | P0.1     | Multifunction I/O   | Yes                 | P0MAT.1, INT0.1, INT1.1     | ADC0.1, CMP0P.1, CMP0N.1, AGND |
| 3          | P0.2     | Multifunction I/O   | Yes                 | P0MAT.2, INT0.2, INT1.2     | ADC0.2, CMP0P.2, CMP0N.2 |
| 4          | GND      | Ground              |                     |                             |                           |
| 5          | VDD      | Supply Power Input  |                     |                             |                           |
| 6          | RSTb/C2CK| Active-low Reset / C2 Debug Clock |         |                             |                           |
| 7          | P2.0/C2D | Multifunction I/O / C2 Debug Data |       |                             |                           |
| 8          | P1.7     | Multifunction I/O   | Yes                 | P1MAT.7                     | ADC0.15, CMP1P.7, CMP1N.7 |
| 9          | P1.6     | Multifunction I/O   | Yes                 | P1MAT.6                     | ADC0.14, CMP1P.6, CMP1N.6 |
| 10         | P1.5     | Multifunction I/O   | Yes                 | P1MAT.5                     | ADC0.13, CMP1P.5, CMP1N.5 |
| 11         | P1.4     | Multifunction I/O   | Yes                 | P1MAT.4                     | ADC0.12, CMP1P.4, CMP1N.4 |
| 12         | P1.3     | Multifunction I/O   | Yes                 | P1MAT.3                     | ADC0.11, CMP1P.3, CMP1N.3 |
| 13         | P1.2     | Multifunction I/O   | Yes                 | P1MAT.2                     | ADC0.10, CMP1P.2, CMP1N.2 |
| 14         | GND      | Ground              |                     |                             |                           |
| 15         | P2.1     | Multifunction I/O   |                     |                             |                           |
| 16         | N/C      | No Connection       |                     |                             |                           |
| 17         | P1.1     | Multifunction I/O   | Yes                 | P1MAT.1                     | ADC0.9, CMP1P.1, CMP1N.1  |
| 18         | P1.0     | Multifunction I/O   | Yes                 | P1MAT.0                     | ADC0.8, CMP1P.0, CMP1N.0  |
| 19         | P0.7     | Multifunction I/O   | Yes                 | P0MAT.7, INT0.7, INT1.7     | ADC0.7, CMP0P.7, CMP0N.7  |
| 20         | P0.6     | Multifunction I/O   | Yes                 | P0MAT.6, CNVSTR, INT0.6, INT1.6 | ADC0.6, CMP0P.6, CMP0N.6 |
| 21         | P0.5     | Multifunction I/O   | Yes                 | P0MAT.5, INT0.5, INT1.5     | ADC0.5, CMP0P.5, CMP0N.5  |
| 22         | P0.4     | Multifunction I/O   | Yes                 | P0MAT.4, INT0.4, INT1.4     | ADC0.4, CMP0P.4, CMP0N.4  |
| 23         | P0.3     | Multifunction I/O   | Yes                 | P0MAT.3, EXTCLK, INT0.3, INT1.3 | ADC0.3, CMP0P.3, CMP0N.3 |
| 24         | N/C      | No Connection       |                     |                             |                           |

## 6.2 EFM8BB1x-QFN20 Pin Definitions

*(Refer to Figure 6.2 in the original document for the pinout.)*

### Table 6.2. Pin Definitions for EFM8BB1x-QFN20

| Pin Number | Pin Name | Description         | Crossbar Capability | Additional Digital Functions | Analog Functions          |
|------------|----------|---------------------|---------------------|-----------------------------|---------------------------|
| 1          | P0.1     | Multifunction I/O   | Yes                 | P0MAT.1, INT0.1, INT1.1     | ADC0.1, CMP0P.1, CMP0N.1, AGND |
| 2          | P0.0     | Multifunction I/O   | Yes                 | P0MAT.0, INT0.0, INT1.0     | ADC0.0, CMP0P.0, CMP0N.0, VREF |
| 3          | GND      | Ground              |                     |                             |                           |
| 4          | VDD      | Supply Power Input  |                     |                             |                           |
| 5          | RSTb/C2CK| Active-low Reset / C2 Debug Clock |         |                             |                           |
| 6          | P2.0/C2D | Multifunction I/O / C2 Debug Data |       |                             |                           |
| 7          | P1.6     | Multifunction I/O   | Yes                 | P1MAT.6                     | ADC0.14, CMP1P.6, CMP1N.6 |
| 8          | P1.5     | Multifunction I/O   | Yes                 | P1MAT.5                     | ADC0.13, CMP1P.5, CMP1N.5 |
| 9          | P1.4     | Multifunction I/O   | Yes                 | P1MAT.4                     | ADC0.12, CMP1P.4, CMP1N.4 |
| 10         | P1.3     | Multifunction I/O   | Yes                 | P1MAT.3                     | ADC0.11, CMP1P.3, CMP1N.3 |
| 11         | P1.2     | Multifunction I/O   | Yes                 | P1MAT.2                     | ADC0.10, CMP1P.2, CMP1N.2 |
| 12         | GND      | Ground              |                     |                             |                           |
| 13         | P1.1     | Multifunction I/O   | Yes                 | P1MAT.1                     | ADC0.9, CMP1P.1, CMP1N.1  |
| 14         | P1.0     | Multifunction I/O   | Yes                 | P1MAT.0                     | ADC0.8, CMP1P.0, CMP1N.0  |
| 15         | P0.7     | Multifunction I/O   | Yes                 | P0MAT.7, INT0.7, INT1.7     | ADC0.7, CMP0P.7, CMP0N.7  |
| 16         | P0.6     | Multifunction I/O   | Yes                 | P0MAT.6, CNVSTR, INT0.6, INT1.6 | ADC0.6, CMP0P.6, CMP0N.6 |
| 17         | P0.5     | Multifunction I/O   | Yes                 | P0MAT.5, INT0.5, INT1.5     | ADC0.5, CMP0P.5, CMP0N.5  |
| 18         | P0.4     | Multifunction I/O   | Yes                 | P0MAT.4, INT0.4, INT1.4     | ADC0.4, CMP0P.4, CMP0N.4  |
| 19         | P0.3     | Multifunction I/O   | Yes                 | P0MAT.3, EXTCLK, INT0.3, INT1.3 | ADC0.3, CMP0P.3, CMP0N.3 |
| 20         | P0.2     | Multifunction I/O   | Yes                 | P0MAT.2, INT0.2, INT1.2     | ADC0.2, CMP0P.2, CMP0N.2  |
| Center     | GND      | Ground              |                     |                             |                           |

## 6.3 EFM8BB1x-SOIC16 Pin Definitions

*(Refer to Figure 6.3 in the original document for the pinout.)*

### Table 6.3. Pin Definitions for EFM8BB1x-SOIC16

| Pin Number | Pin Name | Description         | Crossbar Capability | Additional Digital Functions | Analog Functions          |
|------------|----------|---------------------|---------------------|-----------------------------|---------------------------|
| 1          | P0.2     | Multifunction I/O   | Yes                 | P0MAT.2, INT0.2, INT1.2     | ADC0.2, CMP0P.2, CMP0N.2 |
| 2          | P0.1     | Multifunction I/O   | Yes                 | P0MAT.1, INT0.1, INT1.1     | ADC0.1, CMP0P.1, CMP0N.1 |
| 3          | P0.0     | Multifunction I/O   | Yes                 | P0MAT.0, INT0.0, INT1.0     | ADC0.0, CMP0P.0, CMP0N.0 |
| 4          | GND      | Ground              |                     |                             |                           |
| 5          | VDD      | Supply Power Input  |                     |                             |                           |
| 6          | RSTb/C2CK| Active-low Reset / C2 Debug Clock |         |                             |                           |
| 7          | P2.0/C2D | Multifunction I/O / C2 Debug Data |       |                             |                           |
| 8          | P1.3     | Multifunction I/O   | Yes                 | P1MAT.3                     | ADC0.11, CMP1P.5, CMP1N.5 |
| 9          | P1.2     | Multifunction I/O   | Yes                 | P1MAT.2                     | ADC0.10, CMP1P.4, CMP1N.4 |
| 10         | P1.1     | Multifunction I/O   | Yes                 | P1MAT.1                     | ADC0.9, CMP1P.3, CMP1N.3  |
| 11         | P1.0     | Multifunction I/O   | Yes                 | P1MAT.0                     | ADC0.8, CMP1P.2, CMP1N.2  |
| 12         | P0.7     | Multifunction I/O   | Yes                 | P0MAT.7, INT0.7, INT1.7     | ADC0.7, CMP1P.1, CMP1N.1  |
| 13         | P0.6     | Multifunction I/O   | Yes                 | P0MAT.6, CNVSTR, INT0.6, INT1.6 | ADC0.6, CMP1P.0, CMP1N.0 |
| 14         | P0.5     | Multifunction I/O   | Yes                 | P0MAT.5, INT0.5, INT1.5     | ADC0.5, CMP0P.5, CMP0N.5  |
| 15         | P0.4     | Multifunction I/O   | Yes                 | P0MAT.4, INT0.4, INT1.4     | ADC0.4, CMP0P.4, CMP0N.4  |
| 16         | P0.3     | Multifunction I/O   | Yes                 | P0MAT.3, EXTCLK, INT0.3, INT1.3 | ADC0.3, CMP0P.3, CMP0N.3 |

---

# 7. QSOP24 Package Specifications

## 7.1 Package Dimensions

*(Refer to Figure 7.1 in the original document for the drawing.)*

### Table 7.1. Package Dimensions

| Dimension | Min  | Typ   | Max  |
|-----------|------|-------|------|
| A         | -    | -     | 1.75 |
| A1        | 0.10 | -     | 0.25 |
| b         | 0.20 | -     | 0.30 |
| c         | 0.10 | -     | 0.25 |
| D         |      | 8.65 BSC |   |
| E         |      | 6.00 BSC |   |
| E1        |      | 3.90 BSC |   |
| e         |      | 0.635 BSC |  |
| L         | 0.40 | -     | 1.27 |
| theta     | 0°   | -     | 8°   |
| aaa       |      | 0.20  |      |
| bbb       |      | 0.18  |      |
| ccc       |      | 0.10  |      |
| ddd       |      |       |      |

**Note:**
1. All dimensions in millimeters (mm) unless otherwise noted.
2. Dimensioning and Tolerancing per ANSI Y14.5M-1994.
3. Conforms to JEDEC outline MO-137, variation AE.
4. Recommended card reflow profile per JEDEC/IPC J-STD-020.

## 7.2 PCB Land Pattern

*(Refer to Figure 7.2 in the original document for the drawing.)*

### Table 7.2. PCB Land Pattern Dimensions

| Dimension | Min  | Max  |
|-----------|------|------|
| C         | 5.20 | 5.30 |
| E         | 0.635 BSC |  |
| X         | 0.30 | 0.40 |
| Y         | 1.50 | 1.60 |

**Note:**
1. All dimensions in millimeters (mm).
2. Based on IPC-7351 guidelines.
3. Non-solder mask defined (NSMD) pads with 60 µm minimum clearance.
4. Stencil thickness: 0.125 mm (5 mils).
5. Stencil aperture to land pad ratio: 1:1 for perimeter pads.
6. Recommended: No-Clean, Type-3 solder paste and JEDEC/IPC J-STD-020 reflow profile.

## 7.3 Package Marking

*(Refer to Figure 7.3 in the original document for the marking.)*

- **PPPPPPPP**: Part number designation
- **TTTTTT**: Trace or manufacturing code
- **YY**: Last 2 digits of assembly year
- **WW**: 2-digit workweek of assembly
- **\#**: Device revision (A, B, etc.)

---

# 8. QFN20 Package Specifications

## 8.1 QFN20 Package Dimensions

*(Refer to Figure 8.1 in the original document for the drawing.)*

### Table 8.1. QFN20 Package Dimensions

| Dimension | Min  | Typ   | Max  |
|-----------|------|-------|------|
| A         | 0