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gistfile1.txt
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# **PY32F002B**
# **32-bit ARM® Cortex®-M0+ microcontroller**
**Reference manual**
| 1. | | | List of abbreviations for register 14 | |
|----|------|---------|--------------------------------------------------------|--|
| 2. | | | System architecture 15 | |
| 3. | | | Memory and bus architecture 16 | |
| | 3.1. | | System architecture 16 | |
| | 3.2. | | Memory organization 16 | |
| | 3.3. | | Introduction to memory structure 16 | |
| | 3.4. | | Embedded SRAM 20 | |
| | 3.5. | | Flash Memory 20 | |
| | 3.6. | | Boot mode20 | |
| | | 3.6.1. | Memory physical mapping21 | |
| 4. | | | Embedded Flash memory22 | |
| | 4.1. | | Key features 22 | |
| | 4.2. | | Flash memory function introduction22 | |
| | | 4.2.1. | Flash structure22 | |
| | | 4.2.2. | Flash read operation and access latency22 | |
| | | 4.2.3. | Flash program and erase operations 23 | |
| | 4.3. | | Unique Identification Code(UID) 26 | |
| | 4.4. | | Option Byte Description 27 | |
| | | 4.4.1. | Flash option byte 27 | |
| | | 4.4.2. | Flash option byte write 30 | |
| | 4.5. | | Flash configuration bytes 32 | |
| | | 4.5.1. | HSI_TRIMMING_FOR_USER33 | |
| | | 4.5.2. | FLASH_SLEEPTIME_CONFIG33 | |
| | | 4.5.3. | HSI_24M_EPPARA034 | |
| | | 4.5.4. | HSI_24M _EPPARA134 | |
| | | 4.5.5. | HSI_24M _EPPARA234 | |
| | | 4.5.6. | HSI_24M _EPPARA334 | |
| | | 4.5.7. | HSI_24M _EPPARA435 | |
| | | 4.5.8. | LSI_32.768K/38.4K_TRIMMING35 | |
| | | 4.5.9. | VREFBUF_1.5V_TRIMMING35 | |
| | | 4.5.10. | Flash USER OTP memory Bytes 35 | |
| | 4.6. | | Flash protection36 | |
| | | 4.6.1. | Flash software development kit (SDK) area protection36 | |
| | | 4.6.2. | Flash write protection 37 | |
| | | 4.6.3. | Load Flash area protection37 | |
| | | 4.6.4. | Option byte write protection37 | |
| | 4.7. | | Flash interrupt 37 | |
| | 4.8. | | Flash register description38 | |
| | | 4.8.1. | Flash access control register (FLASH_ACR)38 | |
| | 4.8.2. | Flash key register (FLASH_KEYR) 38 | |
|----|---------|---------------------------------------------------------------------|--|
| | 4.8.3. | Flash option key register (FLASH_OPTKEYR)38 | |
| | 4.8.4. | Flash status register (FLASH_SR)39 | |
| | 4.8.5. | Flash control register (FLASH_CR)39 | |
| | 4.8.6. | Flash option register (FLASH_OPTR)41 | |
| | 4.8.7. | Flash SDK address register (FLASH_SDKR) 41 | |
| | 4.8.8. | FLASH boot control (FLASH_BTCR) 42 | |
| | 4.8.9. | Flash WRP address register (FLASH_WRPR) 42 | |
| | 4.8.10. | Flash sleep time configuration register (FLASH_STCR)43 | |
| | 4.8.11. | Flash TS0 register (FLASH_TS0) 43 | |
| | 4.8.12. | Flash TS1 register (FLASH_TS1) 44 | |
| | 4.8.13. | Flash TS2P register (FLASH_TS2P) 44 | |
| | 4.8.14. | Flash TPS3 register (FLASH_TPS3) 44 | |
| | 4.8.15. | Flash TS3 register (FLASH_TS3) 45 | |
| | 4.8.16. | Flash page erase TPE register (FLASH_PERTPE)45 | |
| | 4.8.17. | FLASH SECTOR/MASS ERASE TPE Register (FLASH_SMERTPE) 45 | |
| | 4.8.18. | FLASH PROGRAM TPE register (FLASH_PRGTPE) 46 | |
| | 4.8.19. | FLASH PRE-PROGRAM TPE Register (FLASH_PRETPE) 46 | |
| | 4.8.20. | Flash register mapping46 | |
| 5. | | Power control49 | |
| | 5.1. | Power supply49 | |
| | 5.1.1. | Power block diagram49 | |
| | 5.2. | Voltage regulator49 | |
| | 5.3. | Dynamic voltage value management49 | |
| | 5.4. | Power monitoring 50 | |
| | 5.4.1. | Power-on reset (POR)/power-down reset (PDR)/brown-out reset (BOR)50 | |
| 6. | | Low-power control51 | |
| | 6.1. | Low-power mode51 | |
| | 6.1.1. | Introduction to low-power modes 51 | |
| | 6.1.2. | Functions in each working mode51 | |
| | 6.2. | Sleep mode52 | |
| | 6.2.1. | Entering sleep mode 52 | |
| | 6.2.2. | Exiting sleep mode 52 | |
| | 6.3. | Stop mode53 | |
| | 6.3.1. | Entering stop mode 53 | |
| | 6.3.2. | Exiting Stop mode 53 | |
| | 6.4. | Decreasing system clock frequency 54 | |
| | 6.5. | Peripheral clock gating54 | |
| | 6.6. | Power management register54 | |
| | 6.6.1. | Power control register 1 (PWR_CR1) 55 | |
| 6.6.2. | PWR register map 55 | |
|---------|-------------------------------------------------------------------|--|
| 7. | Reset56 | |
| 7.1. | Reset source56 | |
| 7.1.1. | Power reset 56 | |
| 7.1.2. | System reset56 | |
| 7.1.3. | NRST pin (external reset)56 | |
| 7.1.4. | Watchdog reset 57 | |
| 7.1.5. | Software reset 57 | |
| 7.1.6. | Option byte loader reset 57 | |
| 8. | Clock 58 | |
| 8.1. | Clock source 58 | |
| 8.1.1. | High-speed external clock (HSE) 58 | |
| 8.1.2. | Low-speed external clock (LSE)58 | |
| 8.1.3. | High-speed internal clock (HSI)58 | |
| 8.1.4. | Low-speed internal clock (LSI)58 | |
| 8.2. | Clock tree 58 | |
| 8.3. | Clock security system (CSS) 59 | |
| 8.4. | Clock-out capability59 | |
| 8.5. | Internal and external clock calibration with TIM1460 | |
| 8.5.1. | HSI calibration 60 | |
| 8.5.2. | LSI calibration61 | |
| 8.6. | Reset/clock register 61 | |
| 8.6.1. | Clock control register (RCC_CR) 61 | |
| 8.6.2. | Internal clock source calibration register (RCC_ICSCR) 62 | |
| 8.6.3. | Clock configuration register (RCC_CFGR) 63 | |
| 8.6.4. | External clock source control register (RCC_ECSCR) 64 | |
| 8.6.5. | Clock interrupt enable register (RCC_CIER) 65 | |
| 8.6.6. | Clock interrupt flag register (RCC_CIFR)66 | |
| 8.6.7. | Clock interrupt clear register (RCC_CICR) 66 | |
| 8.6.8. | I/O interface reset register (RCC_IOPRSTR) 67 | |
| 8.6.9. | AHB peripheral reset register (RCC_AHBRSTR) 67 | |
| 8.6.10. | APB peripheral reset register 1 (RCC_APBRSTR1)68 | |
| 8.6.11. | APB peripheral reset register 2 (RCC_APBRSTR2)68 | |
| 8.6.12. | I/O interface clock enable register (RCC_IOPENR)69 | |
| 8.6.13. | AHB peripheral clock enable register (RCC_AHBENR)69 | |
| 8.6.14. | APB peripheral clock enable register 1 (RCC_APBENR1)70 | |
| 8.6.15. | APB peripheral clock enable register 2 (RCC_APBENR2)70 | |
| 8.6.16. | Peripheral independent clock configuration register (RCC_CCIPR)71 | |
| 8.6.17. | RTC domain control register (RCC_BDCR)72 | |
| 8.6.18. | Control/status register (RCC_CSR) 73 | |
| | | 8.6.19. | RCC register address map73 | |
|-----|--------|---------|-------------------------------------------------------------------------|--|
| 9. | | | General-purpose I/Os (GPIO)76 | |
| | 9.1. | | GPIO introduction76 | |
| | 9.2. | | GPIO main features 76 | |
| | 9.3. | | GPIO functional description 76 | |
| | 9.3.1. | | General-purpose I/O (GPIO) 77 | |
| | 9.3.2. | | I/O pin alternate function multiplexer and mapping77 | |
| | 9.3.3. | | I/O port control registers78 | |
| | 9.3.4. | | I/O port data registers78 | |
| | 9.3.5. | | I/O data bitwise handling 78 | |
| | 9.3.6. | | GPIO locking mechanism79 | |
| | 9.3.7. | | I/O alternate function input/output 79 | |
| | 9.3.8. | | External interrupt/wakeup lines 79 | |
| | 9.3.9. | | I/O input configuration 79 | |
| | | 9.3.10. | I/O output configuration 80 | |
| | | 9.3.11. | Alternate function configuration81 | |
| | | 9.3.12. | Analog configuration82 | |
| | | 9.3.13. | Use the LSE oscillator pins as GPIOs83 | |
| | 9.4. | | GPIO registers 83 | |
| | 9.4.1. | | GPIO port mode register (GPIOx_MODER) (x = A, B, C)83 | |
| | 9.4.2. | | GPIO port output type register (GPIOx_OTYPER) (x = A, B, C) 83 | |
| | 9.4.3. | | GPIO port output speed register (GPIOx_OSPEEDR) (x = A, B, C) 84 | |
| | 9.4.4. | | GPIO port pull-up and pull-down register (GPIOx_PUPDR) (x = A, B, C) 84 | |
| | 9.4.5. | | GPIO port input data register (GPIOx_IDR) (x = A, B, C) 85 | |
| | 9.4.6. | | GPIO port output data register (GPIOx_ODR) (x = A, B, C)85 | |
| | 9.4.7. | | GPIO port bit set/reset register (GPIOx_BSRR) (x = A, B, C) 85 | |
| | 9.4.8. | | GPIO port configuration lock register (GPIOx_LCKR) (x = A, B, C) 86 | |
| | 9.4.9. | | GPIO alternate function register (low) (GPIOx_AFRL) (x = A, B, C) 86 | |
| | | 9.4.10. | GPIO alternate function register(high)(GPIOx_AFRH) (x = A, B, C)88 | |
| | | 9.4.11. | GPIO port bit reset register (GPIOx_BRR) (x = A, B, C)91 | |
| | | 9.4.12. | GPIO register map 91 | |
| 10. | | | System configuration controller (SYSCFG) 94 | |
| | 10.1. | | System configuration register94 | |
| | | 10.1.1. | SYSCFG configuration register 1 (SYSCFG_CFGR1) 94 | |
| | | 10.1.2. | SYSCFG configuration register 2 (SYSCFG_CFGR2) 95 | |
| | | 10.1.3. | GPIO filtering enable(GPIO_ENS) 95 | |
| | | 10.1.4. | SYSCFG register map96 | |
| 11. | | | Interrupts and events 97 | |
| | 11.1. | 11.1.1. | Nested vectored interrupt controller (NVIC)97<br>NVIC main features 97 | |
| | | | | |
| 11.1.2. | SysTick calibration value register97 | |
|---------|--------------------------------------------------------|--|
| 11.1.3. | Interrupt and exception vectors 97 | |
| 11.2. | Extended interrupts and events controller (EXTI)98 | |
| 11.2.1. | EXTI main features98 | |
| 11.2.2. | EXTI diagram98 | |
| 11.2.3. | EXTI connection between peripherals and CPU99 | |
| 11.2.4. | EXTI configurable event trigger wake-up 99 | |
| 11.2.5. | EXTI direct type event input wakeup100 | |
| 11.2.6. | EXTI selector100 | |
| 11.3. | EXTI registers101 | |
| 11.3.1. | Rising trigger selection register (EXTI_RTSR)101 | |
| 11.3.2. | Falling trigger selection register (EXTI_FTSR) 102 | |
| 11.3.3. | Software interrupt event register (EXTI_SWIER)103 | |
| 11.3.4. | Pending register (EXTI_PR)104 | |
| 11.3.5. | External interrupt select register 1 (EXTI_EXTICR1)106 | |
| 11.3.6. | External interrupt select register 2 (EXTI_EXTICR2)106 | |
| 11.3.7. | Interrupt mask register (EXTI_IMR) 107 | |
| 11.3.8. | Event mask register (EXTI_EMR) 108 | |
| 11.3.9. | EXTI register map 109 | |
| 12. | Cyclic redundancy check calculation unit (CRC)111 | |
| 12.1. | Introduction111 | |
| 12.2. | CRC main features111 | |
| 12.3. | CRC functional description111 | |
| 12.3.1. | CRC block diagram 111 | |
| 12.4. | CRC registers112 | |
| 12.4.1. | Data register (CRC_DR) 112 | |
| 12.4.2. | Independent data register (CRC_IDR)112 | |
| 12.4.3. | Control register (CRC_CR) 112 | |
| 12.4.4. | CRC register map113 | |
| 13. | Analog-to-digital converter (ADC)114 | |
| 13.1. | Introduction114 | |
| 13.2. | ADC main features114 | |
| 13.3. | ADC functional description115 | |
| 13.3.1. | ADC diagram115 | |
| 13.3.2. | Calibration (ADCAL)115 | |
| 13.3.3. | ADC on-off control (ADEN) 116 | |
| 13.3.4. | ADC Clock 117 | |
| 13.3.5. | Configuring the ADC 117 | |
| 13.3.6. | Channel selection (CHSEL, SCANDIR) 117 | |
| 13.3.7. | Programmable sampling time (SMP) 118 | |
| 13.3.8. | Single conversion mode (CONT = 0, DISCEN = 0) 118 | |
|-----------|------------------------------------------------------------------------|--|
| 13.3.9. | Continuous conversion mode (CONT = 1)119 | |
| 13.3.10. | Discontinuous conversion mode (DISCEN = 1) 119 | |
| 13.3.11. | Starting conversions (ADSTART)120 | |
| 13.3.12. | 转换时间 120 | |
| 13.3.13. | Stopping an ongoing conversion (ADSTP)121 | |
| 13.4. | Conversion on external trigger and trigger polarity (EXTSEL, EXTEN)121 | |
| 13.4.1. | Fast conversion mode 122 | |
| 13.4.2. | End of conversion, end of sampling phase (EOC, EOSMP flags) 122 | |
| 13.4.3. | End of conversion sequence (EOSEQ flag)122 | |
| 13.4.4. | Example timing diagrams 123 | |
| 13.5. | Data management125 | |
| 13.5.1. | Data register and data alignment (ADC_DR, ALIGN)125 | |
| 13.5.2. | ADC overrun (OVR, OVRMOD) 125 | |
| 13.5.3. | Managing conversion sequences without DMA 126 | |
| 13.5.4. | Conversion without DMA and overflow detection126 | |
| 13.6. | Low-power features127 | |
| 13.6.1. | Automatic latency conversion mode127 | |
| 13.7. | Analog window watchdog127 | |
| 13.7.1. | ADC_AWD_OUT signal output generation 128 | |
| 13.8. | Temperature sensor and internal reference voltage129 | |
| 13.9. | ADC interrputs130 | |
| 13.10. | ADC regiseters 130 | |
| 13.10.1. | ADC interrupt and status register (ADC_ISR)130 | |
| 13.10.2. | ADC interrupt enable register (ADC_IER)131 | |
| 13.10.3. | ADC control register (ADC_CR)132 | |
| 13.10.4. | ADC configuration register 1 (ADC_CFGR1)133 | |
| 13.10.5. | ADC configuration register 2 (ADC_CFGR2)135 | |
| 13.10.6. | ADC sampling time register (ADC_SMPR) 136 | |
| 13.10.7. | ADC watchdog threshold register (ADC_TR)137 | |
| 13.10.8. | ADC channel selection register (ADC_CHSELR) 137 | |
| 13.10.9. | ADC data register (ADC_DR)138 | |
| 13.10.10. | ADC calibration configuration and status registers (ADC_CCSR)138 | |
| 13.10.11. | ADC common configuration register (ADC_CCR)139 | |
| 13.10.12. | ADC register map 140 | |
| 14. | Comparator (COMP) 142 | |
| 14.1. | Introduction142 | |
| 14.2. | COMP main features142 | |
| 14.3. | COMP function description 143 | |
| 14.3.1. | COMP diagram143 | |
| 14.3.2. | COMP pins and internal signals 143 | |
|----------|----------------------------------------------------|--|
| 14.3.3. | COMP reset and clock 143 | |
| 14.3.4. | Window comparator 144 | |
| 14.3.5. | Low-power mode144 | |
| 14.3.6. | Comparator filtering144 | |
| 14.3.7. | COMP interrupt145 | |
| 14.4. | COMP registers145 | |
| 14.4.1. | COMP1 control and status registers (COMP1_CSR) 145 | |
| 14.4.2. | COMP1 filter register (COMP1_FR)146 | |
| 14.4.3. | COMP2 control and status registers (COMP2_CSR) 147 | |
| 14.4.4. | COMP2 filter register (COMP2_FR)147 | |
| 14.4.5. | COMP register map148 | |
| 15. | Advanced-control timer (TIM1)149 | |
| 15.1. | TIM1 introduction 149 | |
| 15.2. | TIM1 main features 149 | |
| 15.3. | TIM1 functional description 150 | |
| 15.3.1. | Time-base unit150 | |
| 15.3.2. | Counter modes 152 | |
| 15.3.3. | Repetition counter 159 | |
| 15.3.4. | Clock source160 | |
| 15.3.5. | Capture/compare channel 162 | |
| 15.3.6. | Input capture mode 164 | |
| 15.3.7. | PWM input mode165 | |
| 15.3.8. | Forced output mode 166 | |
| 15.3.9. | Output compare mode166 | |
| 15.3.10. | PWM mode167 | |
| 15.3.11. | Complementary outputs and dead-time insertion169 | |
| 15.3.12. | Using the break function171 | |
| 15.3.13. | Clearing the OCxREF signal on an external event173 | |
| 15.3.14. | 6-step PWM generation174 | |
| 15.3.15. | One-pulse mode 175 | |
| 15.3.16. | Encoder interface mode 177 | |
| 15.3.17. | Timer input XOR function 178 | |
| 15.3.18. | Interfacing with Hall sensors179 | |
| 15.3.19. | TIMx and external trigger synchronization 180 | |
| 15.3.20. | Timer synchronization 183 | |
| 15.3.21. | Debug mode 183 | |
| 15.4. | TIM1 registers 183 | |
| 15.4.1. | TIM1 control register1 (TIM1_CR1)183 | |
| 15.4.2. | TIM1 control register2 (TIM1_CR2)185 | |
| | 15.4.3. | TIM1 slave mode control register (TIM1_SMCR)186 | |
|-----|----------|--------------------------------------------------------|--|
| | 15.4.4. | TIM1 interrupt enable register (TIM1_DIER)188 | |
| | 15.4.5. | TIM1 status register (TIM1_SR)189 | |
| | 15.4.6. | TIM1 event generation register (TIM1_EGR)191 | |
| | 15.4.7. | TIM1 capture/compare mode register1 (TIM1_CCMR1)192 | |
| | 15.4.8. | TIM1 capture/compare mode register 2 (TIM1_CCMR2)195 | |
| | 15.4.9. | TIM1 capture/compare enable register (TIM1_CCER) 196 | |
| | 15.4.10. | TIM1 counter (TIM1_CNT) 198 | |
| | 15.4.11. | TIM1 prescaler (TIM1_PSC)198 | |
| | 15.4.12. | TIM1 auto-reload register (TIM1_ARR)199 | |
| | 15.4.13. | TIM1 repetition counter register (TIM1_RCR)199 | |
| | 15.4.14. | TIM1 capture/compare register 1 (TIM1_CCR1)200 | |
| | 15.4.15. | TIM1 capture/compare register 2 (TIM1_CCR2)200 | |
| | 15.4.16. | TIM1 capture/compare register 3 (TIM1_CCR3)200 | |
| | 15.4.17. | TIM1 capture/compare register 4 (TIM1_CCR4)201 | |
| | 15.4.18. | TIM1 break and dead-time register (TIM1_BDTR)201 | |
| | 15.4.19. | TIM1 register mapping203 | |
| 16. | | General purpose timer (TIM14)205 | |
| | 16.1. | TIM14introduction 205 | |
| | 16.2. | TIM14 main features 205 | |
| | 16.3. | TIM14 functional description 206 | |
| | 16.3.1. | Time-base unit206 | |
| | 16.3.2. | Clock sources 210 | |
| | 16.3.3. | Capture/compare channels 210 | |
| | 16.3.4. | Input capture mode 211 | |
| | 16.3.5. | Force ouput mode 212 | |
| | 16.3.6. | Output compare mode213 | |
| | 16.3.7. | PWM mode213 | |
| | 16.3.8. | One-pulse mode214 | |
| | 16.3.9. | Timer synchronization 216 | |
| | 16.3.10. | Debug mode 216 | |
| | 16.4. | TIM14 register 216 | |
| | 16.4.1. | TIM14control register 1 (TIM14_CR1) 216 | |
| | 16.4.2. | TIM14 DMA/interrupt enable register (TIM14_DIER)217 | |
| | 16.4.3. | TIM14status register (TIM14_SR)217 | |
| | 16.4.4. | TIM14 Event generation register (TIM14_EGR) 218 | |
| | 16.4.5. | TIM14 Capture/compare mode register 1(TIM14_CCMR1)219 | |
| | 16.4.6. | TIM14 capture/compare enable register (TIM14_CCER) 221 | |
| | 16.4.7. | TIM14 Counter (TIM14_CNT) 222 | |
| | 16.4.8. | TIM14 prescaler(TIM14_PSC) 222 | |
| 16.4.9. | TIM14 auto-reload register (TIM14_ARR)222 | |
|----------|---------------------------------------------------|--|
| 16.4.10. | TIM14 capture/compare register 1(TIM14_CCR1)223 | |
| 16.4.11. | TIM14 option register(TIMx_OR)223 | |
| 16.4.12. | TIM14 register map 223 | |
| 17. | Low power timer(LPTIM)225 | |
| 17.1. | Introduction225 | |
| 17.2. | LPTIM main features225 | |
| 17.3. | LPTIM functional description225 | |
| 17.3.1. | LPTIMblock diagram 225 | |
| 17.3.2. | LPTIM pins and internal signals 225 | |
| 17.3.3. | LPTIM Reset and clock 226 | |
| 17.3.4. | Prescaler 226 | |
| 17.3.5. | Operating mode226 | |
| 17.3.6. | Register update 226 | |
| 17.3.7. | Enable timer 226 | |
| 17.3.8. | Counter reset INDANG227 | |
| 17.3.9. | Debug mode227 | |
| 17.4. | LPTIM Low power mode 227 | |
| 17.5. | LPTIM interrupt227 | |
| 17.6. | LPTIMregister227 | |
| 17.6.1. | LPTIMinterrupt and status register (LPTIM_ISR)228 | |
| 17.6.2. | LPTIM interrupt clear register (LPTIM_ICR) 228 | |
| 17.6.3. | LPTIM interrupt enable register (LPTIM_IER)228 | |
| 17.6.4. | LPTIM configuration register (LPTIM_CFGR)229 | |
| 17.6.5. | LPTIMcontrol register (LPTIM_CR)229 | |
| 17.6.6. | LPTIM auto-reload register (LPTIM_ARR)230 | |
| 17.6.7. | LPTIM counter (LPTIM_CNT) 230 | |
| 17.6.8. | LPTIM register map231 | |
| 18. | Independent watchdog(IWDG)232 | |
| 18.1. | Introduction232 | |
| 18.2. | IWDGmain features232 | |
| 18.3. | IWDG functional diagram 232 | |
| 18.3.1. | IWDG block diagram 232 | |
| 18.3.2. | Hardware watchdog 232 | |
| 18.3.3. | Register access protection 233 | |
| 18.3.4. | Debug mode233 | |
| 18.4. | IWDG register233 | |
| 18.4.1. | Key register (IWDG_KR)233 | |
| 18.4.2. | Prescaler register (IWDG_PR)233 | |
| 18.4.3. | Reload register (IWDG_RLR)234 | |
| | 18.4.4. | Status register (IWDG_SR)234 | |
|-----|----------|---------------------------------------------------------------------|--|
| | 18.4.5. | IWDG register map234 | |
| 19. | | Inter-integrated circuit interface236 | |
| | 19.1. | Introduction236 | |
| | 19.2. | I2C main features236 | |
| | 19.3. | I2C functional description236 | |
| | 19.3.1. | I2C block diagram 236 | |
| | 19.3.2. | Mode selection 237 | |
| | 19.3.3. | I2C Initialization 238 | |
| | 19.3.4. | I2C slave mode238 | |
| | 19.3.5. | I2C master mode240 | |
| | 19.3.6. | Error stage244 | |
| | 19.3.7. | SDA/SCL Control245 | |
| | 19.4. | I2C interrupts245 | |
| | 19.5. | I2C Registers246 | |
| | 19.5.1. | I2C control register 1 (I2C_CR1)246 | |
| | 19.5.2. | I2C Control register 2 (I2C_CR2)247 | |
| | 19.5.3. | I2C Own address register 1 (I2C_OAR1)248 | |
| | 19.5.4. | I2C Data register (I2C_DR)248 | |
| | 19.5.5. | I2C Stage register(I2C_SR1) 249 | |
| | 19.5.6. | I2C Stage register 2 (I2C_SR2) 251 | |
| | 19.5.7. | I2C Clock control register (I2C_CCR) 252 | |
| | 19.5.8. | I2C TRISE register (I2C_TRISE)252 | |
| | 19.5.9. | I2C register map253 | |
| 20. | | Universal synchronous asynchronous receiver transmitter (USART) 254 | |
| | 20.1. | Introduction254 | |
| | 20.2. | USART main features 254 | |
| | 20.3. | USART function description 255 | |
| | 20.3.1. | USART character description256 | |
| | 20.3.2. | Transmitter 257 | |
| | 20.3.3. | Recevier 259 | |
| | 20.3.4. | USART baud rate generation 262 | |
| | 20.3.5. | USART receiver's tolerance to clock deviation 263 | |
| | 20.3.6. | USART auto baud rate detection 263 | |
| | 20.3.7. | Multi processor communication using USART264 | |
| | 20.3.8. | USART synchronous mode266 | |
| | 20.3.9. | USART single-wire half-duplex communication267 | |
| | 20.3.10. | Hardware flow control268 | |
| | 20.4. | USART interrupt request269 | |
| | 20.5. | USART register 270 | |
| | 20.5.1. | Status register (USART_SR)270 | |
|-----|----------|------------------------------------------------------|--|
| | 20.5.2. | USART Data register(USART_DR)272 | |
| | 20.5.3. | Baud rate register (USART_BRR)272 | |
| | 20.5.4. | USART control register 1 (USART_CR1) 273 | |
| | 20.5.5. | USART control register 2 (USART_CR2) 274 | |
| | 20.5.6. | USART control register 3 (USART_CR3) 275 | |
| | 20.5.7. | USART register map 276 | |
| 21. | | Serial peripheral interface (SPI) 277 | |
| | 21.1. | Introduction277 | |
| | 21.2. | SPI main features277 | |
| | 21.3. | SPI function description 277 | |
| | 21.3.1. | Overview277 | |
| | 21.3.2. | Communications between one master and one slave 278 | |
| | 21.3.3. | Multi-slave communication 280 | |
| | 21.3.4. | Multi-master commnunication 281 | |
| | 21.3.5. | Slave select (NSS) pin management 282 | |
| | 21.3.6. | Comminication formats283 | |
| | 21.3.7. | SPI configuration 284 | |
| | 21.3.8. | SPI enabling procedure284 | |
| | 21.3.9. | Data transmission and reception procedures285 | |
| | 21.3.10. | Status flags 288 | |
| | 21.3.11. | Error flags 289 | |
| | 21.3.12. | SPI interrupts 289 | |
| | 21.4. | SPI register289 | |
| | 21.4.1. | SPI control register 1 (SPI_CR1) 289 | |
| | 21.4.2. | SPI control register2 (SPI_CR2) 291 | |
| | 21.4.3. | SPI status register (SPI_SR)291 | |
| | 21.4.4. | SPI data register (SPI_DR) 292 | |
| | 21.4.5. | SPI register map293 | |
| 22. | | Debug support 294 | |
| | 22.1. | Overview 294 | |
| | 22.2. | Pinout and debug port pins 294 | |
| | 22.2.1. | SWD port pins 294 | |
| | 22.2.2. | Flexible SW-DP pin assignment294 | |
| | 22.2.3. | Internal pull-up and pu;;-down on SWD pins295 | |
| | 22.3. | ID codes and locking mechanism 295 | |
| | 22.4. | SWD debug port295 | |
| | 22.4.1. | SWD protocol introduction295 | |
| | 22.4.2. | SWD protocol sequence295 | |
| | 22.4.3. | SW-DP state machine (reset, idle states, ID code)296 | |
| 22.4.4. | DP and AP read/write accesses296 | |
|---------|-------------------------------------------------|--|
| 22.4.5. | SW-DP registers296 | |
| 22.4.6. | SW-AP register297 | |
| 22.5. | Core debug297 | |
| 22.6. | Break Point Unit 297 | |
| 22.6.1. | BPU functionality 297 | |
| 22.7. | DWT (Data Watchpoint)297 | |
| 22.7.1. | DWTfunctionality 298 | |
| 22.7.2. | DWT program counter sample register 298 | |
| 22.8. | MCU debug component (DBGMCU)298 | |
| 22.8.1. | Debug support for low-power modes 298 | |
| 22.8.2. | Debug support for timers, watchdog and IIC298 | |
| 22.9. | DBG register298 | |
| 22.9.1. | DBG device ID code register(DBG_IDCODE) 298 | |
| 22.9.2. | Debug MCUconfiguration register (DBGMCU_CR) 299 | |
| 22.9.3. | DBG APB freeze register 1 (DBG_APB_FZ1) 299 | |
| 22.9.4. | DBG APB freeze register 2(DBG_APB_FZ2) 300 | |
| 22.9.5. | DBG register map300 | |
| 23. | Version history302 | |
## <span id="page-13-0"></span>**1. List of abbreviations for register**
| Abbreviation | Description | |
|---------------------------|----------------------------------------------------------------------------------------------------------------------------------|--|
| read/write (rw) | Software can read and write to this bit. | |
| read-only (r) | Software can only read this bit. | |
| write-only (w) | Software can only write to this bit. Reading this bit returns the reset value. | |
| read/clear write0 (rc_w0) | Software can read as well as clear this bit by writing 0. Writing '1' has no effect on the bit<br>value. | |
| read/clear write1 (rc_w1) | Software can read as well as clear this bit by writing 1. Writing '0' has no effect on the bit<br>value. | |
| read/clear write (rc_w) | Software can read as well as clear this bit by writing register. Writing to this bit has no<br>effect. | |
| read/clear by read (rc_r) | Software can read this bit. Reading this bit automatically clears it to '0'. Writing this bit<br>has no effect on the bit value. | |
| read/set by read (rs_r) | Software can read this bit. Reading this bit automatically sets it to '1'. Writing this bit has<br>no effect on the bit value. | |
| read/set (rs) | Software can read as well as set this bit to '1'. Writing '0' has no effect on the bit value. | |
| toggle (t) | Software can toggle this bit by writing '1'. Writing '0' has no effect. | |
| Reserved (Res) | Reserved bit, must be kept at reset value. | |
![](_page_14_Figure_1.jpeg)
<span id="page-14-0"></span>**2. System architecture**
Figure 2-1 System architecture
# <span id="page-15-0"></span>**3. Memory and bus architecture**
## <span id="page-15-1"></span>**3.1. System architecture**
The system consists of the following parts::
- One Master
- Cortex-M0+
- Three Slaves
- Internal SRAM
- Internal Flash Memory
- AHB with AHB-APB Bridge
![](_page_15_Figure_10.jpeg)
Figure 3-1 System architecture
## System bus
This bus connects the system bus of the Cortex-M0+ core to a BusMatrix which manages the arbitration of the CPU.
## BusMatrix
The BusMatrix manages the access arbitration of the CPU bus.This arbitration uses the Round Robin algorithm.The BusMatrix is composed of Master(CPU)and slaves(Flash memory、SRAM and AHB-to-APB bridge)。
## AHB-to-APB bridge(APB)
The AHB-to-APB bridge provides a synchronous connection between the AHB and APB buses to the peripheral address mapping of the Bridge.
## <span id="page-15-2"></span>**3.2. Memory organization**
## <span id="page-15-3"></span>**3.3. Introduction to memory structure**
Program memory, data memory, registers and I/O ports are organized within the same linear 4- Gbytes address space. The bytes are coded in memory in Little Endian format (in a word, the lowest numbered byte is considered the world's least significant byte).
The addressable memory space is divided into 8 mian blocks, each of 512 Mbyte.
![](_page_16_Figure_3.jpeg)
Figure 3-2 Memory map
| Type | Boundary Address | Size | Memory Area | Description |
|------|-------------------------|-----------|-------------------------------------------------------------------------------------------|---------------------|
| SRAM | 0x2000 C000-0x3FFF FFFF | 512MBytes | Reserved | |
| | 0x2000 0000-0x2000 0BFF | 3KBytes | SRAM | |
| Code | 0x1FFF 0300-0x1FFF FFFF | 4KBytes | Reserved | |
| | 0x1FFF 0280-0x1FFF 02FF | 128Bytes | USER OTP memory | Store user data |
| | 0x1FFF 0200-0x1FFF 027F | 128Bytes | Reserved | |
| | 0x1FFF 0180-0x1FFF 01FF | 128Bytes | Factory config. bytes | Store trimming data |
| | 0x1FFF 0100-0x1FFF 017F | 128Bytes | Factory config. bytes | Store triming data |
| | 0x1FFF 0080-0x1FFF 00FF | 128Bytes | Option bytes | Option bytes |
| | 0x1FFF 0000-0x1FFF 007F | 128Bytes | UID | Unique ID |
| | 0x0800 6000-0x1FFE FFFF | 384MBytes | Reserved | |
| | 0x0800 0000-0x0800 5FFF | 24KBytes | Main flash memory | |
| | 0x0000 6000-0x07FF FFFF | 8MBytes | Reserved | |
| | 0x0000 0000-0x0000 5FFF | 24KBytes | According to the Boot con<br>figuration:<br>1)Main flash memory<br>2)Load flash<br>3)SRAM | |
#### Table 3-1 Memory boundary addresses
#### Table 3-2 Peripheral register address
| Bus | Boundary Address | Size | Peripheral |
|-------------------------|-------------------------|------------|------------|
| 0xE000 0000-0xE00F FFFF | | 1 Mbytes | M0+ |
| IOPORT | 0x5000 1800-0x5FFF FFFF | 256 MBytes | Reserved |
| | 0x5000 1400-0x5000 17FF | 1 KBytes | Reserved |
| | 0x5000 1000-0x5000 13FF | 1 KBytes | Reserved |
| | 0x5000 0C00-0x5000 0FFF | 1 Kbytes | Reserved |
| | 0x5000 0800-0x5000 0BFF | 1 Kbytes | GPIOC |
| | 0x5000 0400-0x5000 07FF | 1 Kbytes | GPIOB |
| | 0x5000 0000-0x5000 03FF | 1 Kbytes | GPIOA |
| | 0x4002 3400-0x4FFF FFFF | | Reserved |
| | 0x4002 300C-0x4002 33FF | | Reserved |
| | 0x4002 3000-0x4002 3008 | 1 Kbytes | CRC |
| | 0x4002 2400-0x4002 2FFF | | Reserved |
| | 0x4002 2000-0x4002 23FF | | Flash |
| | 0x4002 1C00-0x4002 1FFF | 3KBytes | Reserved |
| | 0x4002 1900-0x4002 1BFF | | Reserved |
| AHB | 0x4002 1800-0x4002 18FF | 1Kbytes | EXTI |
| | 0x4002 1400-0x4002 17FF | 1Kbytes | Reserved |
| | 0x4002 1080-0x4002 13FF | | Reserved |
| | 0x4002 1000-0x4002 107F | 1KBytes | RCC |
| | 0x4002 0C00-0x4002 0FFF | 1KBytes | Reserved |
| | 0x4002 0040-0x4002 03FF | | Reserved |
| | 0x4002 0000-0x4002 003C | 1KBytes | Reserved |
| APB | 0x4001 5C00-0x4001 FFFF | 32KBytes | Reserved |
| | 0x4001 5880-0x4001 5BFF | | Reserved |
| | 0x4001 5800-0x4001 587F | 1KBytes | DBG |
| | 0x4001 4C00-0x4001 57FF | 3KBytes | Reserved |
| | 0x4001 4850-0x4001 4BFF | | Reserved |
| | 0x4001 4800-0x4001 484C | 1KBytes | Reserved |
| | 0x4001 4450-0x4001 47FF | | Reserved |
| | 0x4001 4400-0x4001 404C | 1KBytes | Reserved |
| Bus | Boundary Address | Size | Peripheral |
|-------------------------|------------------------------------|----------|------------|
| | 0x4001 3C00-0x4001 43FF | 2KBytes | Reserved |
| | 0x4001 381C-0x4001 3BFF | | Reserved |
| | 0x4001 3800-0x4001 3018 | 1KBytes | USART |
| | 0x4001 3400-0x4001 37FF | 1Kbytes | Reserved |
| | 0x4001 3010-0x4001 33FF | | Reserved |
| | 0x4001 3000-0x4001 300C | 1Kbytes | SPI |
| | 0x4001 2C50-0x4001 2FFF | | Reserved |
| | 0x4001 2C00-0x4001 2C4C | 1Kbytes | TIM1 |
| | 0x4001 2800-0x4001 2BFF | 1Kbytes | Reserved |
| | 0x4001 270C-0x4001 27FF | | Reserved |
| | 0x4001 2400-0x4001 2708 | 1Kbytes | ADC |
| | 0x4001 0400-0x4001 23FF | 8Kbytes | Reserved |
| | 0x4001 0220-0x4001 03FF | | Reserved |
| | 0x4001 0200-0x4001 021F | 1KBytes | COMP1/2 |
| | 0x4001 0000-0x4001 01FF | | SYSCFG |
| | 0x4000 B400-0x4000 FFFF | 19KBytes | Reserved |
| | 0x4000 B000-0x4000 B3FF | 1KBytes | Reserved |
| | 0x4000 8400-0x4000 AFFF | 11KBytes | Reserved |
| | 0x4000 7C28-0x4000 7FFF | | Reserved |
| | 0x4000 7C00-0x4000 7C24 | 1KBytes | LPTIM |
| | 0x4000 7400-0x4000 7BFF | 2KBytes | Reserved |
| | 0x4000 7018-0x4000 73FF | | Reserved |
| | 0x4000 7000-0x4000 7014 | 1KBytes | PWR |
| | 0x4000 5800-0x4000 6FFF | 6KBytes | Reserved |
| | 0x4000 5434-0x4000 57FF | | Reserved |
| | 0x4000 5400-0x4000 5430 | 1KBytes | I2C |
| | 0x4000 4800-0x4000 53FF | 3KBytes | Reserved |
| | 0x4000 441C-0x4000 47FF | | Reserved |
| | 0x4000 4400-0x4000 4418 | 1KBytes | Reserved |
| | 0x4000 3C00-0x4000 43FF | 1KBytes | Reserved |
| | 0x4000 3810-0x4000 3BFF | | Reserved |
| | 0x4000 3800-0x4000 380C | 1KBytes | Reserved |
| | 0x4000 3400-0x4000 37FF | 1KBytes | Reserved |
| | 0x4000 3014-0x4000 33FF | 1KBytes | Reserved |
| | 0x4000 3000-0x4000 0010 | | IWDG |
| | 0x4000 2C0C-0x4000 2FFF | 1KBytes | Reserved |
| | 0x4000 2C00-0x4000 2C08 | | Reserved |
| | 0x4000 2830-0x4000 2BFF | 1KBytes | Reserved |
| 0x4000 2800-0x4000 282C | | | Reserved |
| | 0x4000 2420-0x4000 27FF | 1KBytes | Reserved |
| 0x4000 2400-0x4000 241C | | | Reserved |
| | 0x4000 2054-0x4000 23FF<br>1KBytes | | Reserved |
| 0x4000 2000-0x4000 0050 | | | TIM14 |
| | 0x4000 1800-0x4000 1FFF | 2KBytes | Reserved |
| | 0x4000 1400-0x4000 17FF | 1KBytes | Reserved |
| | 0x4000 1030-0x4000 13FF<br>1KBytes | | Reserved |
| | 0x4000 1000-0x4000 102C | | Reserved |
| | 0x4000 0800-0x4000 0FFF | 2KBytes | Reserved |
| | 0x4000 0450-0x4000 07FF | 1Kbytes | Reserved |
| | 0x4000 0400-0x4000 044C | | Reserved |
| | 0x4000 0000-0x4000 03FF | 1KBytes | Reserved |
## <span id="page-19-0"></span>**3.4. Embedded SRAM**
The PY32F002B features up to 3 kbytes of SRAM. It can be accessed as bytes, half-word(16 bits) or full words(32 bits). A hard fault will be generated when the software reads and writes the space outside the setting range.
## <span id="page-19-1"></span>**3.5. Flash Memory**
Flash memory consists of two physical areas:
Main flash area,24 Kbytes,it contains application and user data,used to store user programs and user data. In addition, a maximum of 4 kBytes can be set according to customer configuration for use as a load flash.
Information area,0.75 Kbytes,it includes the following parts:
Factory config. Bytes 0:128 Bytes,uesd to store:
—HSI frequency selection control value and corresponding Trimming value
—Parameter values for erasure time configuration corresponding to different frequencies of HSI
Factory config. Bytes 1:128 Bytes,used to store power-on reading check code.
UID:128 Bytes,uesd to store the UID of the chip.
Option byte:128 Bytes,used to store the configuration values of hardware and storage protection.
User OTP Memory:128 Bytes,uesd to store user data.
Flash memory interface implements instruction of reading and data access based on the AHB protocol, and it also implements the basic program/erase operations of the Flash through registers.
## <span id="page-19-2"></span>**3.6. Boot mode**
Three different boot mode can be selected through the BOOT0 pin and boot selector option bit nBOOT1 (stored in the Option bytes), as shown in the following table:
| Boot mode configuration | | Mode | | |
|-------------------------|------------|----------------------|----------------------|--|
| nBOOT1 bit | nBOOT0 bit | Boot memory size ==0 | Boot memory size !=0 | |
| X | 0 | Main flash start | Main Flash start | |
| 0 | 1 | SRAM start | SRAM start | |
| 1 | 1 | N/A | Load Flash start | |
| Table 3-3 Boot mood | | | |
|---------------------|--|--|--|
|---------------------|--|--|--|
The values on the Boot pins are latched on the 4th SYSCLK after a reset. It is up to the user to set the boot mode to choose according to the table above.
After this startup has completed, the CPU fetches the top-of-stack value from address 0x0000 0000, then starts code executes from the boot memory starting from 0x0000 0004. Depending on the selected boot mode, main Flash memory or SRAM is accessible as follows:
Boot from main Flash memory: the main Flash memory is aligned in the boot memory space
(0x0000 0000), but still accessible from its original memory space (0x0800 0000). In other word, the Flash memory contents can be accessed starting from address 0x0000 0000 or 0x0800 0000.
Boot from Load Flash:Load Flash memory is aligned in the memory space (0x0000 0000) ,but still accessed from the following address spaces based on the Load Flash size setting.
| User Bootloader | Access address |
|-----------------|-------------------------|
| N/A | 0x0800 5C00~0x0800 5FFF |
| 1 Kbyte | 0x0800 5800~0x0800 5FFF |
| 2 Kbyte | 0x0800 5400~0x0800 5FFF |
| 3 Kbyte | 0x0800 5400~0x0800 5FFF |
| 4 Kbyte | 0x0800 5000~0x0800 5FFF |
Boot from the embedded SRAM: the SRAM is aligned in the boot memory space (0x0000 0000), but still accessible at address 0x2000 0000.
## <span id="page-20-0"></span>**3.6.1. Memory physical mapping**
If boot mode is selected, the application software can modify the memory accessible in the program space. This modification is determined by the MEM\_MODE bit selection in the SYS-CFG\_CFGR1 register (see the SYSCFG chapter for details).
## <span id="page-21-0"></span>**4. Embedded Flash memory**
## <span id="page-21-1"></span>**4.1. Key features**
- Main flash block: maximum 24kBytes(6k x 32bit)
- Information block: 0.75kBytes(192 x 32bit)
- Page size: 128Bytes
- Sector size: 4kBytes
The Flash control interface circuit features:
- Flash write and erase
- Write protection
## <span id="page-21-2"></span>**4.2. Flash memory function introduction**
## <span id="page-21-3"></span>**4.2.1. Flash structure**
Flash memory is composed of 32-bit wide storage units, which can be used for program and data storage,Page size is 128 ytes,Sector size is 4 bytes.
In terms of function, Flash memory is divided into main Flash and information Flash, the former has a maximum capacity of 24 Bytes, and the latter has a capacity of 0.75 Bytes.
Page erase operation can be applied to Main flash.
Mass erase can be applied to main Flash if there is no write protection setting, otherwise it cannot be applied to main Flash.
| Block | sector | Page | Base address | Size | | | | |
|------------------|----------|--------------|-------------------------|----------|--|--|--|--|
| | Sector 0 | Page 0-31 | 0x0800 0000-0x0800 0FFF | 4Kbytes | | | | |
| | Sector 1 | Page 32-63 | 0x0800 1000-0x0800 1FFF | 4Kbytes | | | | |
| | Sector 2 | Page 64-95 | 0x0800 2000-0x0800 2FFF | 4Kbytes | | | | |
| Main flash | Sector 3 | Page 96-127 | 0x0800 3000-0x0800 3FFF | 4Kbytes | | | | |
| | Sector 4 | Page 128-159 | 0x0800 4000-0x0800 4FFF | 4Kbytes | | | | |
| | Sector 5 | Page 160-191 | 0x0800 5000-0x0800 5FFF | 4Kbytes | | | | |
| UID | | Page 0 | 0x1FFF 0000-0x1FFF 007F | 128bytes | | | | |
| Opthion bytes | | Page 1 | 0x1FFF 0080-0x1FFF 00FF | 128bytes | | | | |
| Factory config 0 | | Page 2 | 0x1FFF 0100-0x1FFF 017F | 128bytes | | | | |
| Factory config 1 | Sector 6 | Page 3 | 0x1FFF 0180-0x1FFF 01FF | 128bytes | | | | |
| Reserved | | Page 4 | 0x1FFF 0200-0x1FFF 027F | 128bytes | | | | |
| USER OTP memory | | Page 5 | 0x1FFF 0280-0x1FFF 02FF | 128bytes | | | | |
Table 4-1 Flash structure and boundary addresses
## <span id="page-21-4"></span>**4.2.2. Flash read operation and access latency**
Flash can be used as a general memory space to accessed direct addressing. The contents of the Flash memory can be read through a special read control sequence.
The instruction fetch and data access are both done through the AHB bus. Read can mange through the Latency of the FLASH\_ACR register, which is the read operation increase the wait state or not. When it is 0, the wait state of the Flash read operation is not added, when it is 1, the Flash read operation adds one wait state. This mechanism is specially designed to match high-speed system clock and relatively low-speed Flash read speed.
## <span id="page-22-0"></span>**4.2.3. Flash program and erase operations**
The Flash memory can be programmed by In -circuit programming (ICP) or In -application programming (IAP).
**ICP:** It is used to update the entire contents of the Flash memory, using the SWD protocol or the boot loader to load the user application into the MCU. ICP provides quick and efficient design iterations and eliminates unnecessary package handling or socketing of devices.
**IAP:** It can use any communication interface supported by the microcontroller to download programming data into Flash memory. The IAP allows the user to re-program the Flash memory while the application is running. Then, part of the application has to have been previously programmed in the Flash memory using ICP.
If a reset occurs during Flash program and erase operations, the contents of the Flash memory are not protected.
During a program and erase operations to the Flash memory, any attempt to read the Flash memory will stall the bus. The read operation will proceed correctly once the program and erase operations has completed. This means that code or data fetches cannot be made while programming and erasing operations are in progress.
For program and erase operations, the HSI must be turned on.
Program and erase operations can be implemented through the following control interface-related registers :
- Acess control register(FLASH\_ACR)
- KEY register(FLASH\_KEYR)
- Option byte key register (FLASH\_OPTKEYR)
- Flash status register (FLASH\_SR)
- Flash control register (FLASH\_CR)
- Flash option register(FLASH\_OPTR)
- Flash SDK address register(FLASH\_SDKR)
- Flash boot control register(FLASH\_BTCR)
- Flash write protection resister (FLASH\_WRPR)
- FLASH sleep time config register (FLASH\_STCR)
- Flash TS0 register(FLASH\_TS0)
- Flash TS1 register(FLASH\_TS1)
- Flash TS2P register(FLASH\_TS2P)
- Flash TPS3 register(FLASH\_TPS3)
- Flash TS3 register(FLASH\_TS3)
- Flash page erase TPE register(FLASH\_PERTPE)
- Flash sector/mass erase TPE register(FLASH\_SMERTPE)
- Flash program TPE register(FLASH\_PRGTPE)
- Flash pre-program TPE register(FLASH\_PRETPE)
#### **4.2.3.1. Unlocking the Flash memory**
After reset, the Flash memory is protected against unwanted (like caused by electrical interference) write or erase operations. The FLASH\_CR register is not accessible in write mode, except for the OB L\_LAUNCH bits,used to reload option bit. Every time to write or erase the Flash, must write the FLASH\_KEYR register, to generate an unlock sequence, and to open the access to the FLASH\_CR register.
This sequence consists of two steps:
Step 1: Write KEY1 = 0x4567 0123 to the FLASH\_KEYR register
Step 2: Write KEY2 = 0xCDEF 89AB to the FLASH\_KEYR register
Any wrong sequence locks up the FLASH\_CR register until the next reset. In the case of a wrong key sequence, a bus error is detected and a Hard Fault interrupt is generated. This is done after the first write cycle if KEY1 does not match, or during the second write cycle if KEY1 has been correctly written but KEY2 does not match.
The FLASH\_CR register can be locked again by user software by writing the LOCK bit in the FLASH\_CR register.
In addition, the FLASH\_CR register cannot be written when the BSY bit of the FLASH\_SR register is set. In the meantime, any attempt to write FLASH\_CR register will cause the AHB bus to stall until the BSY bit is cleared.
#### **4.2.3.2. Flash memory programming**
The Flash memory can be programmed the entire page in units of 32 bits each time (hardfault will be generated when the half word or byte operation is performed). The program operation is started when the CPU writes a half-word into a main Flash memory address with the PG bit of the FLASH\_CR register set. Any non 32-bit write will cause a hard fault interrupt.
If the address is write-protected by the FLASH\_WRPR register, the program operation is skipped and a warning is issued by the WRPRTERR bit in the FLASH\_CR register. At the end of the program operation, the EOP bit in the FLASH\_CR register will be set.
The Flash memory programming sequence is as follows:
- 1) Check that no Flash memory operation is ongoing by checking the BSY in the FLASH\_SR register.
- 2) If no Flash memory erase or program operation is ongoing, the software reads out the 32 words of the page (if the page already has data stored, perform this step, otherwise skip this step).
- 3) To release the protection of the FLASH\_CR register by programming KEY1 and KEY2 to the FLASH\_KEYR register.
- 4) Set the PG bit and the EOPIE bit in the FLASH\_CR register.
- 5) Programming to the target address from the 1st to 31st word (only accept 32 bit program).
- 6) Set the PGSTRT in FLASH\_CR register.
- 7) Write the 32nd word.
- 8) Wait until the BSY bit of the FLASH\_SR register to be cleared.
- 9) Check the EOP flag in the FLASH\_SR register (It is set when the programming operation has succeeded), and then clear it by software.
- 10) If there are no more program operations, software will clear the PG bit.
When the above step 7) is successfully executed, the program operation is automatically started, and the BSY bit is set by hardware at the same time.
#### **Flash Erase Operation**
The Flash memory can be erased by page, or sector and mass erase (sector and mass erase do not work for information memory).
#### **4.2.3.3. Page erase**
When a page is protected by WRP, it will not be erased and the WRPERR bit is set at this time.In addition,when some main flash areas used as Load Flash,the selected pages will not be erased,and the WRPERR bit will also be set To excution the page erase operation, the following steps need to be performed:
- 1) Check that no Flash memory operation is ongoing by checking the BSY in the FLASH\_SR register.
- 2) To release the protection of the FLASH\_CR register by programming KEY1 and KEY2 to the FLASH\_KEYR register.
- 3) Set the PER bit and the EOPIE bit in the FLASH\_CR register.
- 4) Write arbitrary data (32-bit data) to the page
- 5) Wait for the BSY bit to be cleared.
- 6) Check that the EOP flag is set.
- 7) Clear the EOP flag.
#### **4.2.3.4. Mass erase**
The Mass erase can used to completely erase the entire main Flash memory, but the information block is unaffected by this procedure. Additionally, when WRP is enabled, the mass erase function is disabled and no mass erase operation occurs, the WEPERR bit is set. The following sequence for mass erase:
- 1) Check that no Flash memory operation is ongoing by checking the BSY.
- 2) To release the protection of the FLASH\_CR register by programming KEY1 and KEY2 to the FLASH\_KEYR register.
- 3) Set the MER bit and the EOPIE bit in the FLASH\_CR register.
- 4) Write arbitrary data (32-bit data) to the main Flash memory.
- 5) Wait for the BSY bit to be cleared.
- 6) Check that the EOP flag is set.
- 7) Clear the EOP flag.
#### **4.2.3.5. Sector erase**
The sector erase can be used to erase the main Flash of 4 kbytes, but the information block is unaffected by this procedure. In addition, when a sector is protected by WRP, it will not be erased, and the WRPERR bit is set.when some main flash areas used as Load Flash,if sector5 is selected as the erase object,sector5 will not be erased,and the WRPERR bit will also be set.
The following sequence for sector erase:
- 1) Check that no Flash memory operation is ongoing by checking the BSY.
- 2) To release the protection of the FLASH\_CR register by programming KEY1 and KEY2 to the FLASH\_KEYR register.
- 3) Set the SER bit and the EOPIE bit in the FLASH\_CR register.
- 4) Write arbitrary data to the sector.
- 5) Wait for the BSY bit to be cleared.
- 6) Check that the EOP flag is set.
- 7) Clear the EOP flag.
Information memory other than USER OTP memory is read-only and will never be programmed/erased.
#### **4.2.3.6. Program and erase time configuration**
The program and erase time need to be strictly controlled, otherwise the operation will fail. By default, the hardware design sets the time parameters of program and erase operations that the HSI is 24 MHz. When the HSI output frequency is changed, the Flash program and erase time need to be configured the register correctly.
## <span id="page-25-0"></span>**4.3. Unique Identification Code(UID)**
Typical application scenarios for UID:
- Used as serial number
- When programming internal flash memory, use it as a key or encryption primitive to improve code security
- Activate secure bootstrap process, etc
- The product unique identification provides a reference number that is unique to any device.
- Users can never change these bits. The unique identity identifier can also be read in different ways such as single byte/half word/word, and then connected using custom algorithms.
| | | UID Bits | | | | | | | | | |
|----------------|--------------|------------------|---|---|---|---|---|---|---|--|--|
| Offset Address | Description | 7 | 6 | 5 | 4 | 3 | 2 | 1 | 0 | | |
| 0 | Lot Numer | Lot Number ASCII | | | | | | | | | |
| 1 | Lot Numer | Lot Number ASCII | | | | | | | | | |
| 2 | Lot Numer | Lot Number ASCII | | | | | | | | | |
| 3 | Lot Numer | Lot Number ASCII | | | | | | | | | |
| 4 | Wafer Number | Wafer Number | | | | | | | | | |
| 5 | Lot Numer | Lot Number ASCII | | | | | | | | | |
| 6 | Lot Numer | Lot Number ASCII | | | | | | | | | |
| 7 | Lot Numer | Lot Number ASCII | | | | | | | | | |
#### Base address:0x1FFF 0000
| Offset Address | | UID Bits | | | | | | | | | |
|----------------|----------------------------|---------------------------------------------------|---|---|---|---|---|---|---|--|--|
| | Description | 7 | 6 | 5 | 4 | 3 | 2 | 1 | 0 | | |
| 8 | internal code | internal code | | | | | | | | | |
| 9 | Y coordinate low order | Y coordinate low order | | | | | | | | | |
| 10 | X coordinate low order | X coordinate low order | | | | | | | | | |
| 11 | X,YCoordinate high address | Y coordinate high order<br>X coordinate high orde | | | | | | | | | |
| 12 | Fixed code | 0x78 | | | | | | | | | |
| 13 | internal code | internal code | | | | | | | | | |
| 14 | internal code | internal code | | | | | | | | | |
| 15 | internal code | internal code | | | | | | | | | |
## <span id="page-26-0"></span>**4.4. Option Byte Description**
## <span id="page-26-1"></span>**4.4.1. Flash option byte**
Part of the information area is used as an option byte, which is used to store the hardware configuration that the chip or the user needs to perform for the application. For example, the watchdog can be selected in hardware or software mode.
For data security, the option bytes are stored separately in the code and one's complement code.
| 31 | 30 | 29 | 28 | 27 | 26 | 25 | 24 | 23 | 22 | 21 | 20 | 19 | 18 | 17 | 16 |
|---------------|----------------------------|----|----|----|---------------|----------------------------|----|--------------------------------------|----|----|----|----|----|----|----|
| | Complemented Option byte 1 | | | | | Complemented Option byte 0 | | | | | | | | | |
| 15 | 14 | 13 | 12 | 11 | 10 | 9 | 8 | 7<br>6<br>5<br>4<br>3<br>2<br>1<br>0 | | | | | | | |
| Option byte 1 | | | | | Option byte 0 | | | | | | | | | | |
| | Table 4-2 Option byte format | |
|--|------------------------------|--|
| | | |
The option bytes can be read from the memory locations listed in the table option byte organiza-
tion or from the relevant registers of the following option bytes :
- FLASH user option register (FLASH\_OPTR)
- FLASH SDK area address register (FLASH\_SDKR)
- FLASH boot control register(FLASH\_BTCR)
- FLASH WRP address register (FLASH\_WRPR)
Table 4-3 Option byte organization
| Word Address | Description |
|--------------|-------------------------------------------------------------|
| 0x1FFF 0080 | Option byte for Flash User option and its complemented |
| 0x1FFF 0084 | Option byte for Flash SDK area address and its complemented |
| 0x1FFF 0088 | Option byte for FLASH boot control and its complemented |
| 0x1FFF 008C | Option byte for Flash WRP address and its complemented |
| 0x1FFF 0090 | Reserved |
| 0x1FFF 0094 | Reserved |
| … | Reserved |
| … | Reserved |
| … | Reserved |
| 0x1FFF 00FC | Reserved |
**Option byte for Flash User option**
**Flash memory address:** 0x1FFF 0080
#### **Production value:**0x0155 BEAA
After the power-on reset(POR/BOR/OBL\_LAUNCH)is released, the corresponding value is read from the option bytes area of the Flash information memory and written to the corresponding op-
| 31 | 30 | 29 | 28 | 27 | 26 | 25 | 24 | 23 | 22 | 21 | 20 | 19 | 18 | 17 | 16 |
|----------|--------|----------|-------|--------------------------------|---------------|----|-------|----|----|----|----------|----|----|----|----|
| | ~NRST_ | ~ | ~IWDG | | | | ~BOR_ | | | | | | | | |
| Reserved | MODE | SWD_MODE | _SW | | ~BOR_LEV[2:0] | | EN | | | | Reserved | | | | |
| | R | R | R | R | R | R | R | | | | | | | | |
| 15 | 14 | 13 | 12 | 11 | 10 | 9 | 8 | 7 | 6 | 5 | 4 | 3 | 2 | 1 | 0 |
| | NRST_ | | IWDG | | | | BOR_ | | | | | | | | |
| Reserved | MODE | SWD_MODE | _SW | BOR_LEV[2:0]<br>Reserved<br>EN | | | | | | | | | | | |
| | R | R | R | R | R | R | R | | | | | | | | |
tion bit of the register.
| Bit | Name | R/W | Function |
|-------|---------------|-----|------------------------------------------------------------|
| 31 | Reserved | - | - |
| 30 | ~NRST_MODE | R | One's complement of NRST_MODE |
| 29 | ~SWD_MODE | R | One's complement of SWD_MODE |
| 28 | ~IWDG_SW | R | One's complement of IWDG_SW |
| 27:25 | ~BOR_LEV[2:0] | R | One's complement of BOR_LEV |
| 24 | ~BOR_EN | R | One's complement of BOR_EN |
| 23:15 | Reserved | - | - |
| 14 | NRST_MODE | R | NRST_MODE SWD_MODE |
| | | | 0 X:PCO:NRST PB6:SWD |
| 13 | SWD_MODE | R | 1 0:PCO:GPIO PB6:SWD |
| | | | 1 1:PCO:SWD PB6:GPIO |
| | | | 0:Hardware watchdog |
| 12 | IWDG_SW | R | 1:Software watchdog |
| | | | 000:BOR rising threshold is 1.8V,falling threshold is 1.7V |
| | | | 001:BOR rising threshold is 2.0V,falling threshold is 1.9V |
| | | | 010:BOR rising threshold is 2.2V,falling threshold is 2.1V |
| | | | 011:BOR rising threshold is 2.4V,falling threshold is 2.3V |
| 11:9 | BOR_LEV[2:0] | R | 100:BOR rising threshold is 2.6V,falling threshold is 2.5V |
| | | | 101:BOR rising threshold is 2.8V,falling threshold is 2.7V |
| | | | 110:BOR rising threshold is 3.0V,falling threshold is 2.9V |
| | | | 111:BOR rising threshold is 3.2V,falling threshold is 3.1V |
| | | | BOR enable |
| 8 | BOR_EN | R | 0:BOR is disabled |
| | | | 1:BOR is enabled,BOR_LEV works |
| 7:0 | Reserved | - | - |
#### **Option byte for Flash SDK area address**
#### **Flash memory address:** 0x1FFF 0084
#### **Production value:** 0xF4FF 0B00
After the power-on reset(POR/BOR/OBL\_LAUNCH)is released, the corresponding value is read from the option bytes area of the Flash information memory and written to the corresponding option bit of the register.
| 31 | 30 | 29 | 28 | 27 | 26 | 25 | 24 | 23 | 22 | 21 | 20 | 19 | 18 | 17 | 16 |
|-----|-----|-----|-----|---------------|----|----|----|-----|-----|-----|-----|----------------|----|----|----|
| Res | Res | Res | Res | ~SDK_END[3:0] | | | | Res | Res | Res | Res | ~SDK_STRT[3:0] | | | |
| | | | | R | R | R | R | | | | | R | R | R | R |
| 15 | 14 | 13 | 12 | 11 | 10 | 9 | 8 | 7 | 6 | 5 | 4 | 3 | 2 | 1 | 0 |
|-----|-----|-----|-----|----|--------------|---|---|-----|-----|-----|-----|---|---|---------------|---|
| Res | Res | Res | Res | | SDK_END[3:0] | | | Res | Res | Res | Res | | | SDK_STRT[3:0] | |
| | | | | R | R | R | R | | | | | R | R | R | R |
| Bit | Name | R/W | Function |
|-------|-------------------------------|-----|-------------------------------------------------------------|
| 31:28 | Reserved | - | - |
| 27:24 | Complemented<br>SDK_END[3:0] | R | One's complement of SDK_END |
| 23:20 | Reserved | - | - |
| 19:16 | Complemented<br>SDK_STRT[3:0] | R | One's complement of SDK_STRT |
| 15:12 | Reserved | - | - |
| 11:8 | SDK_END[3:0] | R | SDK area end address, each corresponding STEP is 2 kbytes |
| 7:4 | Reserved | - | - |
| 3:0 | SDK_STRT[3:0] | R | SDK area start address, each corresponding STEP is 2 kbytes |
#### **Option byte for FLASH boot control**
**Flash memory address:** 0x1FFF 0088
#### **Production value:** 0xFFFF 0000
After the power-on reset(POR/BOR/OBL\_LAUNCH)is released, the corresponding value is read from the option bytes area of the Flash information memory and written to the corresponding option bit of the register.
| 31 | 30 | 29 | 28 | 27 | 26 | 25 | 24 | 23 | 22 | 21 | 20 | 19 | 18 | 17 | 1<br>6 |
|--------|--------|-----|-----|-----|-----|-----|-----|-----|-----|-----|-----|-----|----|--------------------|--------|
| ~nBOOT | ~BOOT | Res | Res | Res | Res | Res | Res | Res | Res | Res | Res | Res | | ~BOOT_SIZE | |
| 1 | 0 | | | | | | | | | | | | | [2:0] | |
| R | R | | | | | | | | | | | | R | R | R |
| 15 | 14 | 13 | 12 | 11 | 10 | 9 | 8 | 7 | 6 | 5 | 4 | 3 | 2 | 1 | 0 |
| nBOOT1 | BOOT0. | Res | Res | Res | Res | Res | Res | Res | Res | Res | Res | Res | | BOOT_SIZE<br>[2:0] | |
| R | R | | | | | | | | | | | | R | R | R |
| Bit | Name | R/W | Function | | |
|-------|---------------------------------|-----|--------------------------------------------------------------|--|--|
| 31 | Complemented nBOOT1 | R | One's complement of nBOOT1 | | |
| 30 | Complemented BOOT0 | R | One's complement of BOOT0 | | |
| 29:19 | Reserved | - | - | | |
| 18:16 | Complemented<br>BOOT_SIZE [2:0] | R | One's complement of BOOT_SIZE | | |
| 15 | nBOOT1 | R | nBOOT1,BOOT0 select chip startup mode | | |
| | | | X0:MainFlash startup mode | | |
| | | R | 11:Load Flash startup mode | | |
| 14 | BOOT0 | | 01:SRAM startup mode | | |
| 13:3 | Reserved | - | - | | |
| | | | Select the Main flash section as the Load Flash area for use | | |
| | | | 000:no Load Flash area | | |
| | | | 001:1Kbytes(0x0800 5C00~0x0800 5FFF) | | |
| 2:0 | BOOT_SIZE [2:0] | R | 010:2Kbytes(0x0800 5800~0x0800 5FFF) | | |
| | | | 011:3Kbytes(0x0800 5400~0x0800 5FFF) | | |
| | | | 1xx:4Kbytes(0x0800 5000~0x0800 5FFF) | | |
**Option Byte for Flash WRP Address**
#### **Flash memory address:** 0x1FFF 008C
#### **Production value:** 0xFFC0 003F
After the power-on reset(POR/BOR/OBL\_LAUNCH)is released, the corresponding value is read from the option bytes area of the Flash information memory and written to the corresponding option bit of the register.
| 31 | 30 | 29 | 28 | 27 | 26 | 25 | 24 | 23 | 22 | 21 | 20 | 19 | 18 | 17 | 16 |
|-----|-----|-----|-----|-----|-----|-----|-----|-----|-----|-----------|----|----------|----|----|----|
| Res | Res | Res | Res | Res | Res | Res | Res | Res | Res | ~WRP[5:0] | | | | | |
| | | | | | | | | | | R | R | R | R | R | R |
| 15 | | | | | | | | | | | | | | | |
| | 14 | 13 | 12 | 11 | 10 | 9 | 8 | 7 | 6 | 5 | 4 | 3 | 2 | 1 | 0 |
| Res | Res | Res | Res | Res | Res | Res | Res | Res | Res | | | WRP[5:0] | | | |
| Bit | Name | R/W | Function |
|-------|---------------------|-----|-----------------------------------------------------------------|
| 31:22 | Reserved | - | - |
| 21:16 | Complemented<br>WRP | R | One's complement of WRP |
| 15:6 | Reserved | - | - |
| 5:0 | WRP | R | 0:sector[y] is protected<br>1:sector[y] unprotected<br>y=0 to 5 |
### <span id="page-29-0"></span>**4.4.2. Flash option byte write**
After reset, the bits in the FLASH\_CR register associated with the option byte are write-protected. The OPTLOCK bit in the FLASH\_CR register must be cleared before the option byte can be manipulated.
The following steps are used to unlock this register:
- 1) Unlock sequence to unlock write protection of FLASH\_CR register.
- 2) Write OPTKEY1 = 0x0819 2A3B to the FLASH\_OPTKEYR register.
- 3) Write OPTKEY2 = 0x4C5D 6E7F to the FLASH\_OPTKEYR register.
Any wrong sequence locks up the FLASH\_CR register until the next reset. In the case of a wrong key sequence, a bus error is detected and a Hard Fault interrupt is generated.
User option (option bytes in information Flash memory) can be protected by software by writing the OPTLOCK bit of the FLASH\_CR register to prevent unwanted erase/program operations.
If software sets the Lock bit, the OPTLOCK bit is also automatically set.
#### **Modifying user option bytes**
Programming operation of the option byte is different from the operation to the main Flash memory. To modify the option bytes, the following steps are required:
- 1) Using the steps described previously to clear the OPTLOCK bit.
- 2) Check that no Flash memory operation is ongoing by checking the BSY.
- 3) Write the desired value (1~4 words) to the option bytes register FLASH\_OPTR / FLASH\_SDKR / FLASH\_BTCR / FLASH\_WRP.
- 4) Set OPTSTRT bit.
- 5) Write any 32 bit data to the main Flash memory address 0x4002 2080 (trigger a formal program operation).
- 6) Wait for the BSY bit to be cleared.
7) Wait for EOP to be pulled high, software to be cleared.
Any change to the option bytes, the hardware will first erase the entire page to the option byte, and then program the value of the FLASH\_OPTR, FLASH\_SDKR, FLASH\_BTCR or FLASH\_WRPR register to the option bytes. And, the hardware automatically calculates the corresponding complement, and programs the calculated value to the corresponding area of the option bytes.
#### **Reload Bytes Option**
After the BSY bit is cleared, all new option bytes are written into the Flash information memory, but they are not applied to the system. The read operation of the option bytes register still returns the value in the last loaded option bytes. Once they are loaded with new values, it will work on the system.
The loading of option bytes is performed in the following two cases:
- OBL\_LAUNCH bit in the FLASH\_CR register is set.
- After power-on reset(POR、BOR)
Loading option bytes is: read the option bytes in the information memory area, and then store the read data in the internal option registers (FLASH\_OPTR, FLASH\_SDKR and FLASH\_WRPR). These internal registers configure the system and can be read by software. The OBL\_LAUNCH bit is set to generate a reset, so that the loading of option bytes can be carried out under the reset of the system.
Each option bit has a corresponding complement at its same doubleword address (next half word). During the loading of the option bytes, the validation of the option bit and its complement ensures that the loading was performed correctly.
If the one's complement matches, the option bytes are copied into the option register.
If the one's complement does not match, the OPTVERR status bit in the FLASH\_SR register is set. Unmatched values are written to the option register:
- For user option
- BOR\_LEV is written as 000 (the lowest threshold)
- The BOR\_EN bit is written as 0 (BOR is not enabled)
- NRST\_MODE bit written to 0 (reset input only)
- The rest of the mismatched values are written as 1
- For SDK area option, SDKR\_STRT [3:0] = 0x0, SDKR\_END [3:0] = 0xB, all Flash memory is set as SDK
- For FLASH boot control option
- nBOOT1,BOOT0 bits are written as 00 (i.e. select Main flash as the startup area)
- BOOT\_SIZE bits is written as 0 (i.e. no Load Flash area)
- For the WRP option, the unmatched value is the default "no protection"
After system reset, the contents of option bytes are copied to the following option registers (readable and writable by software):
- FLASH\_OPTR
- FLASH\_SDKR
- FLASH\_BTCR
#### FLASH\_WRPR
These registers are also used to modify option bytes. If these registers are not modified by the user, they reflect the state of the system option.
## <span id="page-31-0"></span>**4.5. Flash configuration bytes**
Part of the interval (one page in total) of the information area of the Flash memory is used as factory config.byte.
## **Page 0 is stored for software to read information (only code, no one's complement code is stored):**
- HSI frequency selection control value, and corresponding trimming value
- Parameter values for erasure time configuration corresponding to different frequencies of HSI
- Trimming values corresponding to different frequencies of LSI
- Trimming values corresponding to different output voltages of VREFBUF
- Page 1 stores chip hardware factory information (forward and reverse code storage)
- Chip power on read verification code
- Chip hardware Trimming configuration values
For the sake of data security, the factory configuration of Page 1 Bytes are stored separately in text and reverse form.
| Page | Word | Address | Contents |
|------|-------|-----------------------------|--------------------------------------------------------------------------------------------------------------------------------|
| | 0-3 | 0x1FFF 0000-<br>0x1FFF 000F | UID |
| 1 | 4-7 | 0x1FFF 0010-<br>0x1FFF 001F | Reserved |
| | 8 | 0x1FFF 0020 | 1.2 Vrefint(Decimal with positive values in the upper 16 bits) |
| | 9-10 | 0x1FFF 0024-<br>0x1FFF 002B | Reserved |
| | 11 | 0x1FFF 002C | 1.5 Vrefbuf(Decimal with positive values in the upper 16 bits ) |
| | 12-31 | 0x1FFF 0030-<br>0x1FFF 007F | Reserved |
| | 0 | 0x1FFF 0100 | Store HSI 24<br>Hz frequency selection control and corresponding trimming<br>value |
| | 1 | 0x1FFF 0104 | Reserved |
| | 2 | 0x1FFF 0108 | Reserved |
| | 3 | 0x1FFF 010C | Reserved |
| | 4 | 0x1FFF 0110 | Reserved |
| | 5 | 0x1FFF 0114 | Store the count value of the flash low power control(FLASH_LPCR)register |
| 2 | 6 | 0x1FFF 0118 | Reserved |
| | 7 | 0x1FFF 011C | Store the configuration values of the corresponding FLASH_TS0、FLASH_<br>TS1 and FLASH_TS3 registers at the HSI 24MHz frequency |
| | 8 | 0x1FFF 0120 | Store the configuration values of the corresponding<br>FLASH_TS2P and<br>FLASH_TPS3 registers at the HSI 24MHz frequency |
| | 9 | 0x1FFF 0124 | Store the configuration value of the corresponding FLASH_PERTPE register<br>at the HSI 24MHz frequency |
| | 10 | 0x1FFF 0128 | Store the cpnfiguration value of the corresponding FLASH_SMERTPE regis<br>ter at the HSI 24MHz frequency |
#### Table 4-4 Factory config. byte organization
| | 11 | 0x1FFF 012C | Store the cpnfiguration values of the corresponding FLASH_PRGTPE and<br>FLASH_PRETPE registers at the HSI 24MHz frequency. | | | | |
|---|-------|-----------------------------|----------------------------------------------------------------------------------------------------------------------------|--|--|--|--|
| | 12-31 | 0x1FFF 0130-<br>0x1FFF 017F | Reserved | | | | |
| | 0 | 0x1FFF 0180 | Power on read verification code 0x55AA AA55 | | | | |
| | 1 | 0x1FFF 0184 | Power on read verification code 0xAA55 55AA | | | | |
| | 2 | 0x1FFF 0188 | Power on read verification code 0x55AA AA55 | | | | |
| | 3 | 0x1FFF 018C | Power on read verification code 0xAA55 55AA | | | | |
| | 4 | 0x1FFF 0190 | PMU trimming bit and its complemented bit | | | | |
| | 5 | 0x1FFF 0194 | PMU trimming bit and its complemented bit | | | | |
| | 6 | 0x1FFF 0198 | PMU trimming bit and its complemented bit | | | | |
| | 7 | 0x1FFF 019C | Reserved | | | | |
| | 8 | 0x1FFF 01A0 | HSI 24MHz frequency selection, trimming and its complemented bit | | | | |
| | 9 | 0x1FFF 01A4 | LSI 32.768K frequency Trimming and its complemented bit | | | | |
| | 10 | 0x1FFF 01A8 | Reserved | | | | |
| | 11 | 0x1FFF 01AC | Reserved | | | | |
| | 12 | 0x1FFF 01B0 | Reserved | | | | |
| | 13 | 0x1FFF 01B4 | Reserved | | | | |
| | 14 | 0x1FFF 01B8 | Flash Trimming and its complemented bit | | | | |
| | 15 | 0x1FFF 01BC | Flash Trimming and its complemented bit | | | | |
| 3 | 16 | 0x1FFF 01C0 | Flash Trimming and its complemented bit | | | | |
| | 17 | 0x1FFF 01C4 | Flash Trimming and its complemented bit | | | | |
| | 18 | 0x1FFF 01C8 | Flash Trimming and its complemented bit | | | | |
| | 19 | 0x1FFF 01CC | Flash Trimming and its complemented bit | | | | |
| | 20 | 0x1FFF 01D0 | TS trimming and its complemented bit | | | | |
| | 21 | 0x1FFF 01D4 | Reserved | | | | |
| | 22 | 0x1FFF 01D8 | Reserved | | | | |
| | 23 | 0x1FFF 01DC | Reserved | | | | |
| | 24 | 0x1FFF 01E0 | Reserved | | | | |
| | 25 | 0x1FFF 01E4 | Reserved | | | | |
| | 26 | 0x1FFF 01E8 | Reserved | | | | |
| | 27 | 0x1FFF 01EC | Reserved | | | | |
| | 28 | 0x1FFF 01F0 | Reserved | | | | |
| | 29 | 0x1FFF 01F4 | Reserved | | | | |
| | 30 | 0x1FFF 01F8 | Device ID code | | | | |
| | 31 | 0x1FFF 01FC | Reserved | | | | |
| | | | | | | | |
## <span id="page-32-0"></span>**4.5.1. HSI\_TRIMMING\_FOR\_USER**
#### **Address:** 0x1FFF 0100~0x1FFF 0104
| 31 | 30 | 29 | 28 | 27 | 26 | 25 | 24 | 23 | 22 | 21 | 20 | 19 | 18 | 17 | 16 |
|-----|-----|-----|-----|-----|-----|----------------|-----|-----|-----|-----|-----|-----|----|-------------|----|
| Res | Res | Res | Res | Res | Res | Res | Res | Res | Res | Res | Res | Res | | HSI_FS[2:0] | |
| | | | | | | | | | | | | | R | R | R |
| 15 | 14 | 13 | 12 | 11 | 10 | 9 | 8 | 7 | 6 | 5 | 4 | 3 | 2 | 1 | 0 |
| Res | | | | | | HSI_TRIM[12:0] | | | | | | | | | |
| | | | R | R | R | R | R | R | R | R | R | R | R | R | R |
The software needs to read data from this address, and then write to HSI\_FS[2:0] and
HSI\_TRIM[12:0] corresponding to the RCC\_ICSCR register to change the HSI frequency.
#### <span id="page-32-1"></span>**4.5.2. FLASH\_SLEEPTIME\_CONFIG**
| 31 | 30 | 29 | 28 | 27 | 26 | 25 | 24 | 23 | 22 | 21 | 20 | 19 | 18 | 17 | 16 |
|-----|-----|-----|-----|-----|-----|-----|-----|-----|-----|-----|-----|-----|-----|-----|-----|
| Res | Res | Res | Res | Res | Res | Res | Res | Res | Res | Res | Res | Res | Res | Res | Res |
| | | | | | | | | | | | | | | | |
| 15 | 14 | 13 | 12 | 11 | 10 | 9 | 8 | 7 | 6 | 5 | 4 | 3 | 2 | 1 | 0 |
| FLASH_SLEEPTIME[7:0] | | | | | | | | Res | Res | Res | Res | Res | Res | Res | Res |
|----------------------|---|---|---|---|---|---|---|-----|-----|-----|-----|-----|-----|-----|-----|
| R | R | R | R | R | R | R | R | | | | | | | | |
The software needs to read data from this address,and then write to [15:8] corresponding to the FLASH\_SLEEPTIME register.
## <span id="page-33-0"></span>**4.5.3. HSI\_24M\_EPPARA0**
#### **Address:** 0x1FFF 011C(24MHz)
| 31 | 30 | 29 | 28 | 27 | 26 | 25 | 24 | 23 | 22 | 21 | 20 | 19 | 18 | 17 | 16 |
|----------|-----|-----|-----|----|----|----|----------|----|----|----|----|----|----|----|----------|
| Res | Res | Res | Res | | | | TS1[9:0] | | | | | | | | TS3[8:7] |
| | | | | | | | R | R | R | R | R | R | R | R | R |
| 15 | 14 | 13 | 12 | 11 | 10 | 9 | 8 | 7 | 6 | 5 | 4 | 3 | 2 | 1 | 0 |
| TS3[6:0] | | | | | | | TS0[8:0] | | | | | | | | |
| R | R | R | R | R | R | R | R | R | R | R | R | R | R | R | R |
The software needs to set the HSI clock frequency according to the need, choose to read the data from the corresponding address, and then write the FLASH\_TS0, FLASH\_TS1, FLASH\_TS3 registers to realize the configuration of the erasing and programming time required by the corresponding HSI frequency.
## <span id="page-33-1"></span>**4.5.4. HSI\_24M \_EPPARA1**
| 31 | 30 | 29 | 28 | 27 | 26 | 25 | 24 | 23 | 22 | 21 | 20 | 19 | 18 | 17 | 16 |
|-----|-----|-----|-----|-----|------------|-----|-----------|----|----|----|----|----|----|----|----|
| Res | Res | Res | Res | | TPS3[11:0] | | | | | | | | | | |
| | | | | R | R | R | R | R | R | R | R | | R | R | R |
| 15 | 14 | 13 | 12 | 11 | 10 | 9 | 8 | 7 | 6 | 5 | 4 | 3 | 2 | 1 | 0 |
| Res | Res | Res | Res | Res | Res | Res | TS2P[8:0] | | | | | | | | |
| | | | | | | | R | R | R | R | R | R | R | R | R |
**Address:** 0x1FFF 0120(24MHz)
The software needs to set the HSI clock frequency according to the need, choose to read the data from the corresponding address, and then write the FLASH\_TS2P and FLASH\_TPS3 registers to realize the configuration of the erasing and programming time required for the corresponding HSI frequency.
## <span id="page-33-2"></span>**4.5.5. HSI\_24M \_EPPARA2**
#### **Address:** 0x1FFF 0124(24MHz)
| 31 | 30 | 29 | 28 | 27 | 26 | 25 | 24 | 23 | 22 | 21 | 20 | 19 | 18 | 17 | 16 |
|-----|--------------|-----|-----|-----|-----|-----|-----|-----|-----|-----|-----|-----|-----|-------------------|----|
| Res | Res | Res | Res | Res | Res | Res | Res | Res | Res | Res | Res | Res | Res | PERTPE<br>[17:16] | |
| | | | | | | | | | | | | | | | R |
| 15 | 14 | 13 | 12 | 11 | 10 | 9 | 8 | 7 | 6 | 5 | 4 | 3 | 2 | 1 | 0 |
| | PERTPE[15:0] | | | | | | | | | | | | | | |
| R | R | R | R | R | R | R | R | R | R | R | R | R | R | R | R |
The software needs to set the HSI clock frequency according to the need, choose to read the data from the corresponding address, and then write it into the FLASH\_PERTPE register to realize the configuration of the erasing and programming time required for the corresponding HSI frequency.
## <span id="page-33-3"></span>**4.5.6. HSI\_24M \_EPPARA3**
| Address: 0x1FFF 0128(24MHz) | | | |
|-----------------------------|--|--|--|
|-----------------------------|--|--|--|
| 31 | 30 | 29 | 28 | 27 | 26 | 25 | 24 | 23 | 22 | 21 | 20 | 19 | 18 | 17 | 16 | |
|-----|---------------|-----|-----|-----|-----|-----|-----|-----|-----|-----|-----|-----|-----|--------------------|----|--|
| Res | Res | Res | Res | Res | Res | Res | Res | Res | Res | Res | Res | Res | Res | SMER<br>TPE[17:16] | | |
| | | | | | | | | | | | | | | | R | |
| 15 | 14 | 13 | 12 | 11 | 10 | 9 | 8 | 7 | 6 | 5 | 4 | 3 | 2 | 1 | 0 | |
| | SMERTPE[15:0] | | | | | | | | | | | | | | | |
| R | R | R | R | R | R | R | R | R | R | R | R | R | R | R | R | |
The software needs to set the HSI clock frequency according to the need, choose to read the data from the corresponding address, and then write it into the FLASH\_SMERTPE register to realize the configuration of the erasing and programming time required for the corresponding HSI frequency.
## <span id="page-34-0"></span>**4.5.7. HSI\_24M \_EPPARA4**
| 31 | 30 | 29 | 28 | 27 | 26 | 25 | 24 | 23 | 22 | 21 | 20 | 19 | 18 | 17 | 16 |
|-----|--------------|----|--------------|----|----|----|----|----|----|----|----|----|----|----|----|
| Res | Res | | PRETPE[13:0] | | | | | | | | | | | | |
| | | R | R | R | R | R | R | R | R | R | R | R | R | R | R |
| 15 | 14 | 13 | 12 | 11 | 10 | 9 | 8 | 7 | 6 | 5 | 4 | 3 | 2 | 1 | 0 |
| | PRGTPE[15:0] | | | | | | | | | | | | | | |
| R | R | R | R | R | R | R | R | R | R | R | R | R | R | R | R |
#### **Address:** 0x1FFF 012C(24MHz)
The software needs to set the HSI clock frequency according to the need, choose to read the data from the corresponding address, and then write it into the FLASH\_PRGTPE and FLASH\_PRETPE registers to realize the configuration of the erasing and programming time required for the corresponding HSI frequency.
## <span id="page-34-1"></span>**4.5.8. LSI\_32.768K/38.4K\_TRIMMING**
| 31 | 30 | 29 | 28 | 27 | 26 | 25 | 24 | 23 | 22 | 21 | 20 | 19 | 18 | 17 | 16 |
|-----|-----|-----|-----|-----|-----|-----|---------------|-----|-----|-----|-----|-----|-----|-----|-----|
| Res | Res | Res | Res | Res | Res | Res | Res | Res | Res | Res | Res | Res | Res | Res | Res |
| | | | | | | | | | | | | | | | |
| 15 | 14 | 13 | 12 | 11 | 10 | 9 | 8 | 7 | 6 | 5 | 4 | 3 | 2 | 1 | 0 |
| Res | Res | Res | Res | Res | Res | Res | LSI_TRIM[8:0] | | | | | | | | |
| | | | | | | | R | R | R | R | R | R | R | R | R |
**Address:** 0x1FFF 0144(32.768K)、0x1FFF 0148(38.4K)
The software needs to read data from this address, and then write to LSI\_TRIM[8:0] corresponding
to the RCC\_ICSCR register to change the LSI frequency.
## <span id="page-34-2"></span>**4.5.9. VREFBUF\_1.5V\_TRIMMING**
| 31 | 30 | 29 | 28 | 27 | 26 | 25 | 24 | 23 | 22 | 21 | 20 | 19 | 18 | 17 | 16 |
|-----|-----|-----|-----|-----|-----|-----|-----|-----|-----|-----|-------------------|-----|-----|-----|-----|
| Res | Res | Res | Res | Res | Res | Res | Res | Res | Res | Res | Res | Res | Res | Res | Res |
| | | | | | | | | | | | | | | | |
| 15 | 14 | 13 | 12 | 11 | 10 | 9 | 8 | 7 | 6 | 5 | 4 | 3 | 2 | 1 | 0 |
| Res | Res | Res | Res | Res | Res | Res | Res | Res | Res | Res | VREFBUF_TRIM[4:0] | | | | |
| | | | | | | | | | | | R | R | R | R | R |
**Address:** 0x1FFF 014C(1.5V)
The software needs to read data from this address, and then write to VREFBUF\_TRIM[4:0] corre-
sponding to the ADC\_CR register to change the output voltage of the VREFBUF.
## <span id="page-34-3"></span>**4.5.10. Flash USER OTP memory Bytes**
Part of the information area of the flash within the chip is used as Flash USER OTP memory Bytes.
Table 4-5 USER OTP memory Bytes organization
| Page | Word | Address | Contents |
|------|------|--------------|---------------------------------------------------------------|
| 5 | 0 | 00x1FFF 0280 | Bit[31:16]:store user data<br>Bit[15:0]: USER OTP MEMORY_LOCK |
| | 1 | 00x1FFF 0284 | store user data |
| | 2 | 00x1FFF 0288 | store user data |
| | … | … | store user data |
| | … | … | store user data |
| | … | … | store user data |
| | 31 | 00x1FFF 02FC | store user data |
This page is configured in the information area, and the program and erasure in this page area are processed using the Main flash method. Additionally, the mass erase in the Main Flash area is not valid for this area.
Set USER OTP MEMORY\_ LOCK content will not be updated immediately until power on reset (POR/BOR/PDR), which will activate the protection function.
There are the following protections for this Page Write.
| USER OTP MEMORY_LOCK | Write protection | | | | | | |
|-------------------------------|-------------------------------------------------------|--|--|--|--|--|--|
| 0xAA55 | Read:allow<br>Program and erase operation:not allowed | | | | | | |
| Any value other than (0xAA55) | Read、program and erase operation:allow | | | | | | |
#### Table 4-6 Flash USER OTP memory Bytes write protection status
## <span id="page-35-0"></span>**4.6. Flash protection**
The protection of Flash main memory includes the following mechanisms:
- Software design kit (SDK) is used to protect access to specific program areas, and the granularity is 2kbytes.
- Wrtie protection (WRP) control is used to prevent unwanted writes (due to confusion of the program memory pointer PC). The granularity of write protection is designed to be 4 kbytes.
- Option byte write protection, special unlocking design.
## <span id="page-35-1"></span>**4.6.1. Flash software development kit (SDK) area protection**
The protection area is defined by SDKR \_STRT[3:0], SDKR\_END[3:0] of the FLASH\_SDKR register, and each bit corresponds to 2 kbytes.
#### **Start address**
FLASH memory base address + SDK\_STRT[3:0] x 0x800(included)
#### **End address**
FLASH memory base address + (SDK\_END[3:0]+1) x 0x800(excluded)
When SDK \_STRT[3:0] is greater than SDK\_END[3:0], SDK protection is invalid. When SDK \_STRT[3:0] is less than or equal to SDK \_END[3:0], SDK protection is effective.
In the protection effective state, when the FLASH\_SDKR register is unprotected (writing SDK \_STRT[3:0] is greater than SDK\_END[3:0]), the hardware will first trigger mass erase (the protected program in the SDK area has been written before, and the mass erase is used to protect the program in the SDK area), and then the value of the SDK option in the Flash option byte is updated (the updated value at this time is that the SDK protection is invalid).The mass erase generated by SDK protection rewriting will also erase the Load Flash area.
At this time, the content of the FLASH\_SDKR register will not be updated, until the power-on reset (POR/BOR/PDR) or OBL reset, the register content will be loaded from the SDK option in the Flash option byte into the register.
| | | Boot form Main Flash(CPU) | | | | | | | |
|--------------|---------------------------------------|---------------------------|-------|------|-----------------------------------|-------|----------------------------|-------|-------|
| Area | User execution<br>(From Non SDK Area) | | | | User execution<br>(From SDK Area) | | Debug/<br>Execute from RAM | | |
| | Read | Write | Erase | Read | Write | Erase | Read | Write | Erase |
| Non SDK Area | Yes | Yes | Yes | Yes | Yes | Yes | Yes | Yes | Yes |
| SDK<br>Area | No | No | No | Yes | Yes | Yes | No | No | No |
Table 4-7 The relationship between access status and protection level and execution mode
1. Mass erase command issued from any area will erase the SDK area.
2. There are two cases for executing programs from SRAM or system memory: one is Boot from, the other is boot from other memory, and the program jumps to SRAM or system memory.
#### <span id="page-36-0"></span>**4.6.2. Flash write protection**
Flash can be set to be write-protected against unwanted writes. Define the control granularity of each bit of the WRP register as a write protection (WRP) area of 4 kbytes, that is, the size of 1 sector. See the description of the WRP register for details.
When the WRP area is activated, erase or program operations are not allowed. Accordingly, the mass erase function does not work even if only one area is set as write-protected.
In addition, if an attempt is made to erase or program a write-protected area, the write-protection error flag(WRPERR) of the FLASH\_SR register will be set.
Note: Write protection only works on main Flash.
## <span id="page-36-1"></span>**4.6.3. Load Flash area protection**
When Load Flash is valid, erasing the selected area will be ignored, and The WRPRTERR bit of the FLASH\_CR register will also be set.
Modify FLASH\_ BOOT of the BTCR\_ SIZE setting hardware will perform a mass erase operation on the main flash. The mass erase generated by rewriting will also erase the Load Flash area.
## <span id="page-36-2"></span>**4.6.4. Option byte write protection**
By default, Option bytes are readable and write-protected. To gain erase or program access to option bytes, the correct sequence needs to be written to the OPTKEYR register.
## <span id="page-36-3"></span>**4.7. Flash interrupt**
| Interrupt event | Event flag | Time stamp/interrupt clear method | Control bit enable | | |
|------------------|------------|-----------------------------------|--------------------|--|--|
| End of operation | EOP | Write EOP=1 | EOPIE | | |
| Write protection | WRPERR | Write WRPERR=1 | ERRIE | | |
Note: The following events do not have a separate interrupt flag, but will generate a Hard fault:
- Sequence error of FLASH\_CR register of unlock Flash memory.
- Unlock Flash option bytes write sequence error.
- Flash program operation is not aligned with 32-bit data.
- Flash erase (including page erase, sector erase and mass erase) operations do not perform 32-bit data alignment.
- To the option byte register is not aligned with 32-bit data.
## <span id="page-37-0"></span>**4.8. Flash register description**
## <span id="page-37-1"></span>**4.8.1. Flash access control register (FLASH\_ACR)**
#### **Address offset:** 0x00
**Reset value:** 0x0000 0000
| 31 | 30 | 29 | 28 | 27 | 26 | 25 | 24 | 23 | 22 | 21 | 20 | 19 | 18 | 17 | 16 |
|-----|-----|-----|-----|-----|-----|-----|-----|-----|-----|-----|-----|-----|-----|-----|-------------|
| Res | Res | Res | Res | Res | Res | Res | Res | Res | Res | Res | Res | Res | Res | Res | Res |
| | | | | | | | | | | | | | | | |
| 15 | 14 | 13 | 12 | 11 | 10 | 9 | 8 | 7 | 6 | 5 | 4 | 3 | 2 | 1 | 0 |
| Res | Res | Res | Res | Res | Res | Res | Res | Res | Res | Res | Res | Res | Res | Res | LA<br>TENCY |
| | | | | | | | | | | | | | | | RW |
| Bit | Name | R/W | Reset Value | Function |
|------|----------|-----|-------------|-------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------|
| 31:1 | Reserved | | | |
| 0 | LATENCY | RW | 0 | The wait state corresponding to the read operation:<br>0: There is no wait state for Flash read operation.<br>1: The Flash read operation has one wait state, which is<br>two system clock cycles are required for each Flash read. |
## <span id="page-37-2"></span>**4.8.2. Flash key register (FLASH\_KEYR)**
#### **Address offset:** 0x08
**Reset value:** 0x0000 0000
All register bits are write-only and read as 0.
| 31 | 30 | 29 | 28 | 27 | 26 | 25 | 24 | 23 | 22 | 21 | 20 | 19 | 18 | 17 | 16 |
|------------|-----------|----|----|----|----|----|----|----|----|----|----|----|----|----|----|
| KEY[31:16] | | | | | | | | | | | | | | | |
| W | W | W | W | W | W | W | W | W | W | W | W | W | W | W | W |
| 15 | 14 | 13 | 12 | 11 | 10 | 9 | 8 | 7 | 6 | 5 | 4 | 3 | 2 | 1 | 0 |
| | KEY[15:0] | | | | | | | | | | | | | | |
| W | W | W | W | W | W | W | W | W | W | W | W | W | W | W | W |
| Bit | Name | R/W | Reset Value | Function |
|------|-----------|-----|-------------|-----------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------|
| 31:0 | KEY[31:0] | W | 0x0000 | The following values must be written consecutively to un<br>lock the FLASH_CR register and enable the program/erase<br>operation of the Flash<br>KEY1: 0x4567 0123<br>KEY2: 0xCDEF 89AB |
## <span id="page-37-3"></span>**4.8.3. Flash option key register (FLASH\_OPTKEYR)**
**Address offset:** 0x0C
#### **Reset value:** 0x0000 0000
All register bits are write-only and read as 0.
| 31 | 30 | 29 | 28 | 27 | 26 | 25 | 24 | 23 | 22 | 21 | 20 | 19 | 18 | 17 | 16 |
|---------------|----|----|----|----|----|----|----|----|----|----|----|----|----|----|----|
| OPTKEY[31:16] | | | | | | | | | | | | | | | |
| W | W | W | W | W | W | W | W | W | W | W | W | W | W | W | W |
| 15 | 14 | 13 | 12 | 11 | 10 | 9 | 8 | 7 | 6 | 5 | 4 | 3 | 2 | 1 | 0 |
| OPTKEY[15:0] | | | | | | | | | | | | | | | |
| W | W | W | W | W | W | W | W | W | W | W | W | W | W | W | W |
| Bit | Name | R/W | Reset Value | Function |
|------|--------------|-----|-------------|---------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------|
| 31:0 | OPTKEY[31:0] | W | 0x0000 0000 | The following values must be written consecutively to<br>unlock the option register of the Flash and enable the<br>program/erase operation of the option byte<br>KEY1: 0x0819 2A3B<br>KEY2: 0x4C5D 6E7F |
## <span id="page-38-0"></span>**4.8.4. Flash status register (FLASH\_SR)**
#### **Address offset:** 0x10
#### **Reset value:** 0x0000 0000
| 31 | 30 | 29 | 28 | 27 | 26 | 25 | 24 | 23 | 22 | 21 | 20 | 19 | 18 | 17 | 16 |
|-------------|-----|-----|-----|-----|-----|-----|-----|-----|-----|-----|------------|-----|-----|-----|-------|
| Res | Res | Res | Res | Res | Res | Res | Res | Res | Res | Res | Res | Res | Res | Res | BSY |
| | | | | | | | | | | | | | | | R |
| 15 | 14 | 13 | 12 | 11 | 10 | 9 | 8 | 7 | 6 | 5 | 4 | 3 | 2 | 1 | 0 |
| OPTV<br>ERR | Res | Res | Res | Res | Res | Res | Res | Res | Res | Res | WRP<br>ERR | Res | Res | Res | EOP |
| RC_W1 | | | | | | | | | | | RC_W1 | | | | RC_W1 |
| Bit | Name | R/W | Reset Value | Function |
|-------|----------|-------|-------------|-------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------|
| 31:17 | Reserved | | | |
| 16 | BSY | R | 0 | Busy bit<br>This bit indicates that the operation of the Flash is in pro<br>gress. This bit is set by hardware at the beginning of a Flash<br>operation, and is cleared by hardware when the operation<br>is completed or an error occurs |
| 15 | OPTVERR | RC_W1 | 0 | Option and trimming bits loading validity error<br>when the option and trimming bits and their one's comple<br>ments do not match. Load unmatched option bytes, co<br>erced to safe values.<br>Software writes 1 to clear |
| 14:5 | Reserved | | | |
| 4 | WRPERR | RC_W1 | 0 | Write protection error<br>This bit is set by hardware when the address to be pro<br>grammed/erased<br>is<br>in<br>a<br>write-protected<br>Flash<br>re<br>gion(WRP).<br>Write 1 to clear this bit. |
| 3:1 | Reserved | | | |
| 0 | EOP | RC_W1 | 0 | When the program/erase operation of the Flash completes<br>successfully. This bit is only set if the EOPIE bit in the<br>FLASH_CR register is enabled.<br>Write 1 to clear this bit. |
## <span id="page-38-1"></span>**4.8.5. Flash control register (FLASH\_CR)**
#### **Address offset:** 0x14
| 31 | 30 | 29 | 28 | 27 | 26 | 25 | 24 | 23 | 22 | 21 | 20 | 19 | 18 | 17 | 16 |
|----------|-----------------|---------|---------|----------------|---------|---------------|---------------|---------|---------|---------|---------|------------|-----|-----------------|---------|
| LOC<br>K | OPT<br>LOC<br>K | Re<br>s | Re<br>s | OBL_LAUN<br>CH | Re<br>s | ER<br>R<br>IE | EO<br>P<br>IE | Re<br>s | Re<br>s | Re<br>s | Re<br>s | PGSTR<br>T | Res | OPT<br>STR<br>T | Re<br>s |
| RS | RS | | | RC_W1 | | RW | RW | | | | | RW | | RW | |
| 15 | 14 | 13 | 12 | 11 | 10 | 9 | 8 | 7 | 6 | 5 | 4 | 3 | 2 | 1 | 0 |
| Res | Res | Re | Re | SER | Re | Res | Res | Re | Re | Re | Re | | ME | PER | |
|-----|-----|----|----|-----|----|-----|-----|----|----|----|----|-----|----|-----|--------|
| | | s | s | | s | | | s | s | s | s | Res | R | | PG |
| | | | | RW | | | | | | | | | RW | RW | R<br>W |
| Bit | Name | R/W | Reset<br>Value | Function |
|-------|------------|-------|----------------|---------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------|
| 31 | Lock | RS | | FLASH_CR Lock bit.<br>Software can only set this bit. When set, the FLASH_CR<br>register is locked. When the unlock timing is successfully<br>given, this bit is cleared by hardware, and the FLASH_CR<br>register is unlocked.<br>The software should set this bit after the program/erase op<br>eration is completed.<br>When an unsuccessful unlock sequence is given, this bit<br>remains set until the next system reset. |
| 30 | OPTLOCK | RS | | Option bytes Lock bit.<br>Software can only set this bit. When set, the bits related to<br>option bytes in the FLASH_CR register are locked. When<br>the unlock timing is successfully given, this bit is cleared by<br>hardware, and the FLASH_CR register is unlocked.<br>The software should set this bit after the program/erase op<br>eration is completed.<br>When an unsuccessful unlock sequence is given, this bit<br>remains set until the next system reset. |
| 29:28 | Reserved | | | |
| 27 | OBL_LAUNCH | RC_W1 | | Force the option bytes loading.<br>When set, this bit forces the system to perform a reload of<br>option bytes. This bit is only cleared by hardware when the<br>option byte load has been completed. This bit cannot be<br>written if the OPTLOCK bit is set.<br>0: Option byte loading completed<br>1: Option byte loading request is generated, the system re<br>sets, and the option byte is reloaded. |
| 25 | ERRIE | RW | | Error interrupt enable bit, when the WRPERR bit in the<br>FLASH_SR register is set, if this bit is enabled, an interrupt<br>request is generated.<br>0: No interrupt is generated<br>1: An interrupt is generated |
| 24 | EOPIE | RW | | End of operation interrupt enable<br>When the EOP bit of FLASH_SR register is set, an interrupt<br>request is generated if this bit is enabled.<br>0: EOP interrupt disabled<br>1: EOP interrupt enable |
| 23:18 | Reserved | RW | | |
| 19 | PGSTRT | RW | | The start bit of the program operation of the Flash main<br>memory.<br>Program operation of the main Flash memory, and is set by<br>software. After the BSY bit of the FLASH_SR register is<br>cleared, the hardware clears this bit. |
| 18 | Reserved | | | |
| 17 | OPTSTRT | RW | | Flash option bytes modified start bit<br>This bit initiates modification of option bytes. Set by soft<br>ware and cleared by hardware after the BSY bit in the<br>FLASH_SR register is cleared.<br>Note: When modifying the Flash option bytes, the hardware<br>will automatically perform the erase operation on the entire<br>page of 128 bytes, and then perform the program operation,<br>which also includes the automatic writing of the two's com<br>plement code. |
| 16:12 | Reserved | | | |
| 11 | SER | RW | | 4 kbyte Sector erase operation<br>0: Sector erase operation of Flash is not selected<br>1: Select the sector erases operation of Flash<br>Note:<br>1)Sector erase will not work on Flash information memory.<br>2)Sector erase has no effect on areas set to WRP. |
| 10:3 | Reserved | | | |
| Bit | Name | R/W | Reset<br>Value | Function |
|-----|------|-----|----------------|------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------|
| 2 | MER | RW | | Mass erase operation<br>0: Mass erase operation of Flash is not selected<br>1: Select the mass erases operation of Flash<br>Note:<br>Mass<br>erase<br>will<br>not<br>work<br>on<br>Flash<br>information<br>memory.Mass erase does not work when WRP is set |
| 1 | PER | RW | | Page erase operation<br>0: Page erase operation of the Flash is not selected<br>1: Select the page erase operation of Flash |
| 0 | PG | RW | | Program operation<br>0: Program operation of Flash is not selected<br>1: Select the program operation of Flash |
## <span id="page-40-0"></span>**4.8.6. Flash option register (FLASH\_OPTR)**
#### **Address offset:** 0x20
**Reset value:** 0x0000 xxxx。
After the power-on reset (POR/BOR/OBL\_LAUNCH) is released, the corresponding value is read from the option bytes area of the Flash in formation memory and written to the corresponding option bit of the register
| 31 | 30 | 29 | 28 | 27 | 26 | 25 | 24 | 23 | 22 | 21 | 20 | 19 | 18 | 17 | 16 |
|----------|---------------|----------|-------------|--------------|----|----|------------|----------|----|----|----|----|----|----|----|
| Reserved | | | | | | | | | | | | | | | |
| | | | | | | | | | | | | | | | |
| 15 | 14 | 13 | 12 | 11 | 10 | 9 | 8 | 7 | 6 | 5 | 4 | 3 | 2 | 1 | 0 |
| Reserved | NRST_<br>MODE | SWD_MODE | IWDG<br>_SW | BOR_LEV[2:0] | | | BOR_<br>EN | Reserved | | | | | | | |
| | RW | RW | RW | RW | RW | RW | RW | | | | | | | | |
| Bit | Name | R/W | Function | | | | | | |
|-------|--------------|-----|------------------------------------------------------------|--|--|--|--|--|--|
| 31:15 | Reserved | - | - | | | | | | |
| 14 | NRST_MODE | RW | NRST_MODE SWD_MODE | | | | | | |
| | | | 0 X:PCO:NRST PB6:SWD | | | | | | |
| 13 | SWD_MODE | RW | 1 0:PCO:GPIO PB6:SWD | | | | | | |
| | | | 1 1:PCO:SWD PB6:GPIO | | | | | | |
| | | | 0:Hardware watchdog | | | | | | |
| 12 | IWDG_SW | RW | 1:Software watchdog | | | | | | |
| | | | 000:BOR rising threshold is 1.8V,falling threshold is 1.7V | | | | | | |
| | | | 001:BOR rising threshold is 2.0V,falling threshold is 1.9V | | | | | | |
| | | | 010:BOR rising threshold is 2.2V,falling threshold is 2.1V | | | | | | |
| | BOR_LEV[2:0] | | 011:BOR rising threshold is 2.4V,falling threshold is 2.3V | | | | | | |
| 11:9 | | RW | 100:BOR rising threshold is 2.6V,falling threshold is 2.5V | | | | | | |
| | | | 101:BOR rising threshold is 2.8V,falling threshold is 2.7V | | | | | | |
| | | | 110:BOR rising threshold is 3.0V,falling threshold is 2.9V | | | | | | |
| | | | 111:BOR rising threshold is 3.2V,falling threshold is 3.1V | | | | | | |
| | | | BOR enable | | | | | | |
| 8 | BOR_EN | RW | 0:BOR is not enabled | | | | | | |
| | | | 1:BOR is enabled,BOR_LEV works | | | | | | |
| 7:0 | Reserved | - | - | | | | | | |
## <span id="page-40-1"></span>**4.8.7. Flash SDK address register (FLASH\_SDKR)**
#### **Address offset:** 0x24
**Reset value:** 32'b0000 0000 0000 0000 000X XXXX 000X XXXX。
After the power-on reset (POR/BOR/OBL\_LAUNCH) is released, the corresponding value is read from the option bytes area of the Flash information memory and written to the corresponding option bit of the register.
| 31 | 30 | 29 | 28 | 27 | 26 | 25 | 24 | 23 | 22 | 21 | 20 | 19 | 18 | 17 | 16 |
|-----|-----|-----|-----|----|--------------|----|----|-----|-----|-----|-----|----|----|---------------|----|
| Res | | | | | | | | | | | | | | | |
| | | | | | | | | | | | | | | | |
| 15 | 14 | 13 | 12 | 11 | 10 | 9 | 8 | 7 | 6 | 5 | 4 | 3 | 2 | 1 | 0 |
| Res | Res | Res | Res | | SDK_END[3:0] | | | Res | Res | Res | Res | | | SDK_STRT[3:0] | |
| | | | | RW | RW | RW | RW | | | | | RW | RW | RW | RW |
| Bit | Name | R/W | Function |
|-------|---------------|-----|------------------------------------------------------------|
| 31:12 | Reserved | - | - |
| 11:8 | SDK_END[3:0] | RW | SDK area end address, each corresponding STEP is 2kbytes |
| 7:4 | Reserved | - | - |
| 3:0 | SDK_STRT[3:0] | RW | SDK area start address, each corresponding STEP is 2kbytes |
## <span id="page-41-0"></span>**4.8.8. FLASH boot control (FLASH\_BTCR)**
#### **Address offset:** 0x28
Reset value: 32'b0000 0000 0000 0000 XX00 0000 0000 0XXX。 After the power-on reset (POR/BOR/OBL\_LAUNCH) is released, the corresponding value is read from the option bytes area of the Flash information memory and written to the corresponding option bit of the register.
| 31 | 30 | 29 | 28 | 27 | 26 | 25 | 24 | 23 | 22 | 21 | 20 | 19 | 18 | 17 | 16 |
|-------|-------|-----|-----|-----|-----|-----|-----|-----|-----|-----|-----|-----|----|-----------|----|
| Res | | | | | | | | | | | | | | | |
| | | | | | | | | | | | | | | | |
| 15 | 14 | 13 | 12 | 11 | 10 | 9 | 8 | 7 | 6 | 5 | 4 | 3 | 2 | 1 | 0 |
| nBOOT | BOOT0 | Res | Res | Res | Res | Res | Res | Res | Res | Res | Res | Res | | BOOT_SIZE | |
| 1 | | | | | | | | | | | | | | [2:0] | |
| | | | | | | | | | | | | | R | R | R |
| RW | RW | | | | | | | | | | | | W | W | W |
| Bit | Name<br>R/W | | Function |
|-------|-----------------|----|--------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------|
| 31:16 | Reserved | - | - |
| 15 | nBOOT1 | | nBOOT1,BOOT0 select chip startup mode<br>X0:MainFlash startup mode |
| 14 | BOOT0 | RW | 11:Load Flash stratup mode<br>01:SRAM stratup mode |
| 13:3 | Reserved | - | - |
| 2:0 | BOOT_SIZE [2:0] | RW | Select the Main flash section as the Load Flash area for use<br>000:no Load Flash area<br>001:1Kbytes(0x0800 5C00~0x0800 5FFF)<br>010:2Kbytes(0x0800 5800~0x0800 5FFF)<br>011:3Kbytes(0x0800 5400~0x0800 5FFF)<br>1xx:4Kbytes(0x0800 5000~0x0800 5FFF) |
## <span id="page-41-1"></span>**4.8.9. Flash WRP address register (FLASH\_WRPR)**
**Address offset:** 0x2C
#### **Reset value:** 0x0000 XXXX
After the power-on reset (POR/BOR/OBL\_LAUNCH) is released, the corresponding value is read
from the option bytes area of the Flash in formation memory and written to the corresponding op-
tion bit of the register.
| 31 | 30 | 29 | 28 | 27 | 26 | 25 | 24 | 23 | 22 | 21 | 20 | 19 | 18 | 17 | 16 |
|-----|-----|-----|-----|-----|-----|-----|-----|-----|-----|----|----|----------|----|----|----|
| | | | | | | | Res | | | | | | | | |
| | | | | | | | | | | | | | | | |
| | | | | | | | | | | | 4 | | | | |
| 15 | 14 | 13 | 12 | 11 | 10 | 9 | 8 | 7 | 6 | 5 | | 3 | 2 | 1 | 0 |
| Res | Res | Res | Res | Res | Res | Res | Res | Res | Res | | | WRP[5:0] | | | |
| Bit | Name | R/W | Function |
|------|----------|-----|-----------------------------------------------------------------|
| 31:6 | Reserved | - | - |
| 5:0 | WRP | RW | 0:sector[y] is protected<br>1:sector[y] unprotected<br>y=0 to 5 |
## <span id="page-42-0"></span>**4.8.10. Flash sleep time configuration register (FLASH\_STCR)**
#### **Address offset:** 0x90
#### **Reset value:** 0x0000 6400
| 31 | 30 | 29 | 28 | 27 | 26 | 25 | 24 | 23 | 22 | 21 | 20 | 19 | 18 | 17 | 16 |
|----------------------------------------------------------|-----|-----|-----|-----|-----|-----|-----|-----|-----|-----|-----|-----|-----|-----|----------|
| Res | Res | Res | Res | Res | Res | Res | Res | Res | Res | Res | Res | Res | Res | Res | Res |
| | | | | | | | | | | | | | | | |
| | | | | | | | | | | | | | | | |
| 15<br>14<br>13<br>12<br>11<br>10<br>9<br>SLEEP_TIME[7:0] | | | | | 8 | 7 | 6 | 5 | 4 | 3 | 2 | 1 | 0 | | |
| | | | | | | | | Res | Res | Res | Res | Res | Res | Res | SLEEP_EN |
| Bit | Name | R/W | Reset<br>Value | Function |
|------|------------|-----|----------------|----------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------|
| 31:8 | Reserved | | | |
| 15:8 | SLEEP_TIME | RW | 0x64 | FLASH sleep time count (counter based on HSI_10M<br>clock)<br>When the system clock selects LSI or LSE, in order to ob<br>tain more optimized power consumption in Run<br>mode,which can use the function of this register (it is only<br>recommended to use this function when LSI or LSE is the<br>system clock).<br>When this function is enabled, the time width of the Flash<br>in the Sleep state in each half system clock low period is:<br>tHSI_10M * SLEEP_TIME<br>Note :<br>tHSI_10M is the period of HSI_10M.<br>To ensure the correct Flash function, the maximum setting<br>value of this register is recommended to be set to 0x28. |
| 7:1 | Reserved | | | |
| 0 | SLEEP_EN | RW | 0 | FLASH Sleep enable<br>1: Enable Flash sleep<br>0: Disable Flash sleep |
## <span id="page-42-1"></span>**4.8.11. Flash TS0 register (FLASH\_TS0)**
#### **Address offset:** 0x100
#### **Reset value:** 0x0000 xxxx
| 31 | 30 | 29 | 28 | 27 | 26 | 25 | 24 | 23 | 22 | 21 | 20 | 19 | 18 | 17 | 16 |
|-----|-----|-----|-----|-----|-----|-----|-----|-----|-----|-----|-----|-----|-----|-----|-----|
| Res | Res | Res | Res | Res | Res | Res | Res | Res | Res | Res | Res | Res | Res | Res | Res |
| | | | | | | | | | | | | | | | |
| 15 | 14 | 13 | 12 | 11 | 10 | 9 | 8 | 7 | 6 | 5 | 4 | 3 | 2 | 1 | 0 |
| Res | Res | Res | Res | Res | Res | Res | TS0 | | | | | | | | |
| | | RW | RW | RW | RW | RW | RW | RW | RW | RW |
|--|--|----|----|----|----|----|----|----|----|----|
| Bit | Name | R/W | Reset<br>Value | Function |
|------|----------|-----|----------------|--------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------|
| 31:9 | Reserved | | | |
| 8:0 | TS0 | RW | 0x XXXX | The software reads the data stored at the corresponding<br>address in the information area and writes it to the corre<br>sponding register to achieve the configuration of the eras<br>ure time required for the corresponding HSI frequency.<br>Save in Flash at the following address:<br>24MHz calibration value storage address: 0x1FFF 011C |
## <span id="page-43-0"></span>**4.8.12. Flash TS1 register (FLASH\_TS1)**
#### **Address offset:** 0x104
**Reset value:** 0x0000 xxxx
| 31 | 30 | 29 | 28 | 27 | 26 | 25 | 24 | 23 | 22 | 21 | 20 | 19 | 18 | 17 | 16 |
|-----|-----|-----|-----|-----|-----|-----|-----|-----|-----|-----|-----|-----|-----|-----|-----|
| Res | Res | Res | Res | Res | Res | Res | Res | Res | Res | Res | Res | Res | Res | Res | Res |
| | | | | | | | | | | | | | | | |
| 15 | 14 | 13 | 12 | 11 | 10 | 9 | 8 | 7 | 6 | 5 | 4 | 3 | 2 | 1 | 0 |
| Res | Res | Res | Res | Res | Res | TS1 | | | | | | | | | |
| | | | | | | RW | RW | RW | RW | RW | RW | RW | RW | RW | RW |
| Bit | Name | R/W | Reset<br>Value | Function |
|-------|----------|-----|----------------|--------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------|
| 31:10 | Reserved | | | |
| 9:0 | TS1 | RW | 0x XXXX | The software reads the data stored at the corresponding<br>address in the information area and writes it to the corre<br>sponding register to achieve the configuration of the eras<br>ure time required for the corresponding HSI frequency.<br>Save in Flash at the following address:<br>24MHz calibration value storage address: 0x1FFF 011C |
## <span id="page-43-1"></span>**4.8.13. Flash TS2P register (FLASH\_TS2P)**
#### **Address offset:** 0x108
**Reset value:** 0x0000 xxxx
| 31 | 30 | 29 | 28 | 27 | 26 | 25 | 24 | 23 | 22 | 21 | 20 | 19 | 18 | 17 | 16 |
|-----|-----|-----|-----|-----|-----|-----|-----|-----|-----|-----|-----|------|-----|-----|-----|
| Res | Res | Res | Res | Res | Res | Res | Res | Res | Res | Res | Res | Res | Res | Res | Res |
| | | | | | | | | | | | | | | | |
| 15 | 14 | 13 | 12 | 11 | 10 | 9 | 8 | 7 | 6 | 5 | 4 | 3 | 2 | 1 | 0 |
| Res | Res | Res | Res | Res | Res | Res | Res | | | | | TS2P | | | |
| | | | | | | | | RW | RW | RW | RW | RW | RW | RW | RW |
| Bit | Name | R/W | Reset<br>Value | Function |
|------|----------|-----|----------------|--------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------|
| 31:9 | Reserved | | | |
| 8:0 | TS2P | RW | 0x XXXX | The software reads the data stored at the corresponding<br>address in the information area and writes it to the corre<br>sponding register to achieve the configuration of the eras<br>ure time required for the corresponding HSI frequency.<br>Save in Flash at the following address:<br>24MHz calibration value storage address: 0x1FFF 0120 |
## <span id="page-43-2"></span>**4.8.14. Flash TPS3 register (FLASH\_TPS3)**
#### **Address offset:** 0x10C
**Reset value:** 0x0000 xxxx
| 31 | 30 | 29 | 28 | 27 | 26 | 25 | 24 | 23 | 22 | 21 | 20 | 19 | 18 | 17 | 16 |
|-----|-----|-----|-----|-----|-----|-----|-----|-----|-----|-----|-----|-----|-----|-----|-----|
| Res | Res | Res | Res | Res | Res | Res | Res | Res | Res | Res | Res | Res | Res | Res | Res |
| 15 | 14 | 13 | 12 | 11 | 10 | 9 | 8 | 7 | 6 | 5 | 4 | 3 | 2 | 1 | 0 |
|-----|-----|-----|-----|----|------|----|----|----|----|----|----|----|----|----|----|
| Res | Res | Res | Res | | TPS3 | | | | | | | | | | |
| | | | | RW | RW | RW | RW | RW | RW | RW | RW | RW | RW | RW | RW |
| Bit | Name | R/W | Reset<br>Value | Function |
|-------|----------|-----|----------------|--------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------|
| 31:12 | Reserved | | | |
| 11:0 | TPS3 | RW | 0x XXXX | The software reads the data stored at the corresponding<br>address in the information area and writes it to the corre<br>sponding register to achieve the configuration of the eras<br>ure time required for the corresponding HSI frequency.<br>Save in Flash at the following address:<br>24MHz calibration value storage address: 0x1FFF 0120 |
## <span id="page-44-0"></span>**4.8.15. Flash TS3 register (FLASH\_TS3)**
#### **Address offset:** 0x110
#### **Reset value:** 0x0000 xxxx
| 31 | 30 | 29 | 28 | 27 | 26 | 25 | 24 | 23 | 22 | 21 | 20 | 19 | 18 | 17 | 16 |
|-----|-----|-----|-----|-----|-----|-----|-----|-----|-----|-----|-----|-----|-----|-----|-----|
| Res | Res | Res | Res | Res | Res | Res | Res | Res | Res | Res | Res | Res | Res | Res | Res |
| | | | | | | | | | | | | | | | |
| | | | | | | | | | | | | | | | |
| 15 | 14 | 13 | 12 | 11 | 10 | 9 | 8 | 7 | 6 | 5 | 4 | 3 | 2 | 1 | 0 |
| Res | Res | Res | Res | Res | Res | Res | Res | | | | TS3 | | | | |
| Bit | Name | R/W | Reset<br>Value | Function |
|------|----------|-----|----------------|--------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------|
| 31:9 | Reserved | | | |
| 8:0 | TS3 | RW | 0x XXXX | The software reads the data stored at the corresponding<br>address in the information area and writes it to the corre<br>sponding register to achieve the configuration of the eras<br>ure time required for the corresponding HSI frequency.<br>Save in Flash at the following address:<br>24MHz calibration value storage address: 0x1FFF 011C |
## <span id="page-44-1"></span>**4.8.16. Flash page erase TPE register (FLASH\_PERTPE)**
#### **Address offset:** 0x114
**Reset value:** 0x0001 xxxx
| 31 | 30 | 29 | 28 | 27 | 26 | 25 | 24 | 23 | 22 | 21 | 20 | 19 | 18 | 17 | 16 |
|--------|-----|-----|-----|-----|-----|-----|-----|-----|-----|-----|-----|-----|-----|----|--------|
| Res | Res | Res | Res | Res | Res | Res | Res | Res | Res | Res | Res | Res | Res | | PERTPE |
| | | | | | | | | | | | | | | RW | RW |
| 15 | 14 | 13 | 12 | 11 | 10 | 9 | 8 | 7 | 6 | 5 | 4 | 3 | 2 | 1 | 0 |
| PERTPE | | | | | | | | | | | | | | | |
| RW | RW | RW | RW | RW | RW | RW | RW | RW | RW | RW | RW | RW | RW | RW | RW |
| Bit | Name | R/W | Reset<br>Value | Function |
|-------|----------|-----|----------------|--------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------|
| 31:18 | Reserved | | | |
| 17:0 | PERTPE | RW | 0x XXXX | The software reads the data stored at the corresponding<br>address in the information area and writes it to the corre<br>sponding register to achieve the configuration of the eras<br>ure time required for the corresponding HSI frequency.<br>Save in Flash at the following address:<br>24MHz calibration value storage address: 0x1FFF 0124 |
## <span id="page-44-2"></span>**4.8.17. FLASH SECTOR/MASS ERASE TPE Register (FLASH\_SMERTPE)**
**Address offset:** 0x118
| 31 | 30 | 29 | 28 | 27 | 26 | 25 | 24 | 23 | 22 | 21 | 20 | 19 | 18 | 17 | 16 |
|---------|-----|-----|-----|-----|-----|-----|-----|-----|-----|-----|-----|-----|-----|----|---------|
| Res | Res | Res | Res | Res | Res | Res | Res | Res | Res | Res | Res | Res | Res | | SMERTPE |
| | | | | | | | | | | | | | | RW | RW |
| 15 | 14 | 13 | 12 | 11 | 10 | 9 | 8 | 7 | 6 | 5 | 4 | 3 | 2 | 1 | 0 |
| SMERTPE | | | | | | | | | | | | | | | |
| RW | RW | RW | RW | RW | RW | RW | RW | RW | RW | RW | RW | RW | RW | RW | RW |
| | | | | | | | | | | | | | | | |
| Bit | Name | R/W | Reset<br>Value | Function | | | | | | |
|-------|----------|-----|----------------|--------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------|--|--|--|--|--|--|
| 31:18 | Reserved | | | | | | | | | |
| 17:0 | SMERTPE | RW | 0x XXXX | The software reads the data stored at the corresponding<br>address in the information area and writes it to the corre<br>sponding register to achieve the configuration of the eras<br>ure time required for the corresponding HSI frequency.<br>Save in Flash at the following address:<br>24MHz calibration value storage address: 0x1FFF 0128 | | | | | | |
## <span id="page-45-0"></span>**4.8.18. FLASH PROGRAM TPE register (FLASH\_PRGTPE)**
#### **Address offset:** 0x11C
#### **Reset value:** 0x0000 xxxx
| 31 | 30 | 29 | 28 | 27 | 26 | 25 | 24 | 23 | 22 | 21 | 20 | 19 | 18 | 17 | 16 |
|-----|-----|-----|-----|-----|-----|-----|-----|--------|-----|-----|-----|-----|-----|-----|-----|
| Res | Res | Res | Res | Res | Res | Res | Res | Res | Res | Res | Res | Res | Res | Res | Res |
| | | | | | | | | | | | | | | | |
| | | | | | | | | | | | | | | | |
| 15 | 14 | 13 | 12 | 11 | 10 | 9 | 8 | 7 | 6 | 5 | 4 | 3 | 2 | 1 | 0 |
| | | | | | | | | PRGTPE | | | | | | | |
| Bit | Name | R/W | Reset<br>Value | Function |
|-------|----------|-----|----------------|--------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------|
| 31:16 | Reserved | | | |
| 15:0 | PRGTPE | RW | 0x XXXX | The software reads the data stored at the corresponding<br>address in the information area and writes it to the corre<br>sponding register to achieve the configuration of the eras<br>ure time required for the corresponding HSI frequency.<br>Save in Flash at the following address:<br>24MHz calibration value storage address: 0x1FFF 012C |
## <span id="page-45-1"></span>**4.8.19. FLASH PRE-PROGRAM TPE Register (FLASH\_PRETPE)**
| | | Reset value: 0x0000 xxxx | | | | | | | | | | | | | | |
|-----|-----|--------------------------|-----|-----|-----|-----|-----|-----|--------------|-----|-----|-----|-----|-----|-----|--|
| 31 | 30 | 29 | 28 | 27 | 26 | 25 | 24 | 23 | 22 | 21 | 20 | 19 | 18 | 17 | 16 | |
| Res | Res | Res | Res | Res | Res | Res | Res | Res | Res | Res | Res | Res | Res | Res | Res | |
| | | | | | | | | | | | | | | | | |
| 15 | 14 | 13 | 12 | 11 | 10 | 9 | 8 | 7 | 6 | 5 | 4 | 3 | 2 | 1 | 0 | |
| Res | Res | | | | | | | | PRETPE[13:0] | | | | | | | |
| | | RW | RW | RW | RW | RW | RW | RW | RW | RW | RW | RW | | RW | RW | |
| | | | | | RW | | | | | | | | | | | |
| Bit | Name | R/W | Reset<br>Value | Function | | | | | | |
|-------|----------|-----|----------------|--------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------|--|--|--|--|--|--|
| 31:14 | Reserved | | | | | | | | | |
| 13:0 | PRETPE | RW | 0x12C0 | The software reads the data stored at the corresponding<br>address in the information area and writes it to the corre<br>sponding register to achieve the configuration of the eras<br>ure time required for the corresponding HSI frequency.<br>Save in Flash at the following address:<br>24MHz calibration value storage address: 0x1FFF 012C | | | | | | |
## <span id="page-45-2"></span>**4.8.20. Flash register mapping**
**Address offset:** 0x120
| O<br>ffs<br>et | Reg<br>ister | 31 | 30 | 29 | 28 | 27 | 26 | 25 | 24 | 23 | 22 | 21 | 20 | 19 | 18 | 17 | 16 | 15 | 14 | 13 | 12 | 11 | 10 | 9 | 8 | 7 | 6 | 5 | 4 | 3 | 2 | 1 | 0 |
|----------------|------------------------|------------|---------|------|------|------------|------|-------|-------|---------------|------|------|------|-----------|------|---------|------|----------------|---------------|-----------------|---------|------|------------------|--------------|--------|------|------|------|------------------|------------------|------|-------------|----------|
| 0x<br>00 | FLAS<br>H_AC<br>R | Res. | Res. | Res. | Res. | Res. | Res. | Res. | Res. | Res. | Res. | Res. | Res. | Res. | Res. | Res. | Res. | Res. | Res. | Res. | Res. | Res. | Res. | Res. | Res. | Res. | Res. | Res. | Res. | Res. | Res. | Res. | LATENCY |
| | Reset<br>value<br>FLAS | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | 0 |
| 0x<br>08 | H_KE<br>YR<br>Reset | KEY[31:16] | | | | | | | | | | | | KEY[15:0] | | | | | | | | | | | | | | | | | | | |
| | value<br>FLAS | 0 | 0 | 0 | 0 | 0 | 0 | 0 | 0 | 0 | 0 | 0 | 0 | 0 | 0 | 0 | 0 | 0 | 0 | 0 | 0 | 0 | 0 | 0 | 0 | 0 | 0 | 0 | 0 | 0 | 0 | 0 | 0 |
| 0x<br>0C | H_OP<br>TKEY<br>R | | | | | | | | | OPTKEY[31:16] | | | | | | | | | | | | | | OPTKEY[15:0] | | | | | | | | | |
| | Reset<br>value | 0 | 0 | 0 | 0 | 0 | 0 | 0 | 0 | 0 | 0 | 0 | 0 | 0 | 0 | 0 | 0 | 0 | 0 | 0 | 0 | 0 | 0 | 0 | 0 | 0 | 0 | 0 | 0 | 0 | 0 | 0 | 0 |
| 0x<br>10 | FLAS<br>H_SR | Res. | Res. | Res. | Res. | Res. | Res. | Res. | Res. | Res. | Res. | Res. | Res. | Res. | Res. | Res. | BSY | OPTVERR | Res. | Res. | Res. | Res. | Res. | Res. | Res. | Res. | Res. | Res. | WRPERR | Res. | Res. | Res. | EOP |
| | Reset<br>value | | | | | | | | | | | | | | | | 0 | 0 | | | | | | | | | | | 0 | | | | 0 |
| 0x<br>14 | FLAS<br>H_CR | LOCK | OPTLOCK | Res. | Res. | OBL_LAUNCH | Res. | ERRIE | EOPIE | Res. | Res. | Res. | Res. | PGSTRT | Res. | OPTSTRT | Res. | Res. | Res. | Res. | Res. | SER | Res. | Res. | Res. | Res. | Res. | Res. | Res. | Res. | MER | PER | PG |
| | Reset<br>value | 0 | 0 | | | 0 | | | | | | | | 0 | | 0 | | | | | | 0 | | | | | | | | | 0 | 0 | 0 |
| 0x<br>20 | FLAS<br>H_OP<br>TR | Res. | Res. | Res. | Res. | Res. | Res. | Res. | Res. | Res. | Res. | Res. | Res. | Res. | Res. | Res. | Res. | Res. | NRST_MODE | SWD_MODE | IWDG_SW | | BOR_LEV [2:0] | | BOR_EN | | | | Res | | | | |
| | Reset<br>value | | | | | | | | | | | | | | | | | | X | X | X | X | X | X | X | X | X | X | X | X<br>X<br>X<br>X | | | |
| 0x | FLAS<br>H_SD | Res. | Res. | Res. | Res. | Res. | Res. | Res. | Res. | Res. | Res. | Res. | Res. | Res. | Res. | Res. | Res. | Res. | Res. | Res. | Res. | | SDK_END[3:0<br>] | | | Res. | Res. | Res. | Res. | | 0] | SDK_STRT[3: | |
| 24 | KR<br>Reset<br>value | | | | | | | | | | | | | | | | | | | | | X | X | X | X | | | | | X | X | X | X |
| 0x<br>28 | FLAS<br>H_BT<br>CR | Res. | Res. | Res. | Res. | Res. | Res. | Res. | Res. | Res. | Res. | Res. | Res. | Res. | Res. | Res. | Res. | NB<br>OO<br>T1 | BO<br>OT<br>0 | Res. | Res. | Res. | Res. | Res. | Res. | Res. | Res. | Res. | Res. | Res. | ZE | BOOT_SI | |
| | Reset<br>value | | | | | | | | | | | | | | | | | 0 | 0 | | | | | | | | | | | | 0 | 0 | 0 |
| 0x | FLAS<br>H_W<br>RPR | Res. | Res. | Res. | Res. | Res. | Res. | Res. | Res. | Res. | Res. | Res. | Res. | Res. | Res. | Res. | Res. | Res. | Res. | Res. | Res. | Res. | Res. | Res. | Res. | Res. | Res. | | WRP[5:0] | | | | |
| 2C | Reset<br>value | | | | | | | | | | | | | | | | | | | | | | | | | | | X | X | X | X | X | X |
| 0x<br>90 | FLAS<br>H_ST<br>CR | Res. | Res. | Res. | Res. | Res. | Res. | Res. | Res. | Res. | Res. | Res. | Res. | Res. | Res. | Res. | Res. | | | SLEEP_TIME[7:0] | | | | | | Res. | Res. | Res. | Res. | Res. | Res. | Res. | SLEEP_EN |
| | Reset<br>value | | | | | | | | | | | | | | | | | 0 | 1 | 1 | 0 | 0 | 1 | 0 | 0 | | | | | | | | 0 |
| 0x | FLAS<br>H_TS<br>0 | Res. | Res. | Res. | Res. | Res. | Res. | Res. | Res. | Res. | Res. | Res. | Res. | Res. | Res. | Res. | Res. | Res. | Res. | Res. | Res. | Res. | Res. | Res. | Res. | | | | TS0[8:0] | | | | |
| 10<br>0 | Reset<br>value | | | | | | | | | | | | | | | | | | | | | | | | | X | X | X | X | X | X | X | X |
| 0x | FLAS<br>H_TS<br>1 | Res. | Res. | Res. | Res. | Res. | Res. | Res. | Res. | Res. | Res. | Res. | Res. | Res. | Res. | Res. | Res. | Res. | Res. | Res. | Res. | Res. | Res. | Res. | | | | | TS1[8:0] | | | | |
| 10<br>4 | Reset<br>value | | | | | | | | | | | | | | | | | | | | | | | | X | X | X | X | X | X | X | X | X |
| 0x | FLAS<br>H_TS<br>2P | Res. | Res. | Res. | Res. | Res. | Res. | Res. | Res. | Res. | Res. | Res. | Res. | Res. | Res. | Res. | Res. | Res. | Res. | Res. | Res. | Res. | Res. | Res. | Res. | | | | TS2P[8:0] | | | | |
| 10<br>8 | Reset<br>value | | | | | | | | | | | | | | | | | | | | | | | | X | X | X | X | X | X | X | X | X |
| 0x | FLAS<br>H_TP<br>S3 | Res. | Res. | Res. | Res. | Res. | Res. | Res. | Res. | Res. | Res. | Res. | Res. | Res. | Res. | Res. | Res. | Res. | Res. | Res. | Res. | Res. | | | | | | | FLASH_TPS3[11:0] | | | | |
| 10<br>C | Reset<br>value | | | | | | | | | | | | | | | | | | | | | | X | X | X | X | X | X | X | X | X | X | X |
| 0x<br>11 | FLAS<br>H_TS<br>3 | Res. | Res. | Res. | Res. | Res. | Res. | Res. | Res. | Res. | Res. | Res. | Res. | Res. | Res. | Res. | Res. | Res. | Res. | Res. | Res. | Res. | Res. | Res. | Res. | | | | TS3[8:0] | | | | |
| 0 | Reset<br>value | | | | | | | | | | | | | | | | | | | | | | | X | X | X | X | X | X | X | X | X | X |
| O<br>ff<br>s<br>et | Reg<br>ister | 31 | 30 | 29 | 28 | 27 | 26 | 25 | 24 | 23 | 22 | 21 | 20 | 19 | 18 | 17 | 16 | 15 | 14 | 13 | 12 | 11 | 10 | 9 | 8 | 7 | 6 | 5 | 4 | 3 | 2 | 1 | 0 |
|--------------------|---------------------------|------|------|------|------|------|------|------|------|------|------|------|------|------|------|------|--------|------|------|----|----|----|----|---|---------------|--------------|---|---|---|---|---|---|---|
| 0<br>x<br>1 | FLAS<br>H_PE<br>RTPE | Res. | Res. | Res. | Res. | Res. | Res. | Res. | Res. | Res. | Res. | Res. | Res. | Res. | Res. | Res. | PERTPE | | | | | | | | WRP[17:0] | | | | | | | | |
| 1<br>4 | Reset<br>value | | | | | | | | | | | | | | | X | X | X | X | X | X | X | X | X | X | X | X | X | X | X | X | X | X |
| 0<br>x<br>1 | FLAS<br>H_SM<br>ERTP<br>E | Res. | Res. | Res. | Res. | Res. | Res. | Res. | Res. | Res. | Res. | Res. | Res. | Res. | Res. | Res. | | | | | | | | | SMERTPE[17:0] | | | | | | | | |
| 1<br>8 | Reset<br>value | | | | | | | | | | | | | | | X | X | X | X | X | X | X | X | X | X | X | X | X | X | X | X | X | X |
| 0<br>x<br>1 | FLAS<br>H_PR<br>GTPE | Res. | Res. | Res. | Res. | Res. | Res. | Res. | Res. | Res. | Res. | Res. | Res. | Res. | Res. | Res. | Res. | | | | | | | | | PRGTPE[15:0] | | | | | | | |
| 1<br>C | Reset<br>value | | | | | | | | | | | | | | | | | X | X | X | X | X | X | X | X | X | X | X | X | X | X | X | X |
| 0<br>x<br>1 | FLAS<br>H_PR<br>ETPE | Res. | Res. | Res. | Res. | Res. | Res. | Res. | Res. | Res. | Res. | Res. | Res. | Res. | Res. | Res. | Res. | Res. | Res. | | | | | | | PRETPE[13:0] | | | | | | | |
| 2<br>0 | Reset<br>value | | | | | | | | | | | | | | | | | | | X | X | X | X | X | X | X | X | X | X | X | X | X | X |
## <span id="page-48-0"></span>**5. Power control**
## <span id="page-48-1"></span>**5.1. Power supply**
## <span id="page-48-2"></span>**5.1.1. Power block diagram**
![](_page_48_Figure_4.jpeg)
Figure 5-1 Power block diagram
Table 5-1 Power block
| Num<br>bering | Power supply | Power value | Description |
|---------------|--------------|-------------|-----------------------------------------------------------------------------------------------------------------|
| 1 | VCC | 1.7v~5.5v | Provide power to the chip through the power pin, and its power<br>supply module is a partial analog circuit. |
| 2 | VCCA | 1.7v~5.5v | Provide power to most of the analog modules from VCC PAD (a<br>separate power supply PAD can also be designed). |
| 3 | VCCIO | 1.7v~5.5v | Power supply to IO, from VCC PAD |
## <span id="page-48-3"></span>**5.2. Voltage regulator**
The microcontroller designs two voltage regulators:
- Main regulator (MR) keeps working when the chip is in normal operating state.
- Low power regulator (LPR) provides a lower power consumption option in stop mode.
In run mode, MR keeps working, outputs is 1.2V, and LPR is turned off
In stop mode, power can be supplied from MR or LPR as determined by software.
## <span id="page-48-4"></span>**5.3. Dynamic voltage value management**
This project defines two voltage ranges:
#### **Range 1:High performance range**
The typically output of MR is 1.2V (VDD), and the system clock frequency can run as fast as 24 MHz.
#### **Range 2:Low power range**
Only in stop mode, it is allowed to enter the low power range, and the range only works for LPR.
## <span id="page-49-0"></span>**5.4. Power monitoring**
## <span id="page-49-1"></span>**5.4.1. Power-on reset (POR)/power-down reset (PDR)/brown-out reset (BOR)**
The POR/PDR module is designed in the chip and placed under the VDD power domain to provide power-on and power-off reset for the chip. The module keeps working in all modes. In addition to POR/PDR, BOR (brown out reset) is also implemented. BOR can only be enabled and
disabled through the option byte.
When the BOR is turned on, the BOR threshold can be selected by the option byte, and both the rising and falling detection points can be configured individually.
![](_page_49_Figure_8.jpeg)
Figure 5-2 POR/PDR/BOR threshold
## <span id="page-50-0"></span>**6. Low-power control**
By default, the chip enters normal operating mode after system or power reset. When the CPU does not require continuous operation, the chip can enter a low-power mode, for example, when waiting for external events. Software can compromise between power consumption, wake-up time, and wake-up source.
## <span id="page-50-1"></span>**6.1. Low-power mode**
### <span id="page-50-2"></span>**6.1.1. Introduction to low-power modes**
The chip has two low-power modes outside of its normal operating mode:
**Sleep mode**:The CPU clock is off, NVIC, Sys Tick, peripherals can be configured to keep working. (It is recommended to enable only the modules that must work, and close the modules after the modules work).
**Stop mode**:In this mode, the contents of SRAM and registers are maintained, the HSI and HSE are turned off.
In stop mode, LSI, LSE, LPTIMER, etc. can remain operational. Please refer to the table below for the specific working conditions of each module in this mode.
In stop mode, the corresponding of VR state can be controlled by software and set to MR or LPR power supply.When LPR is powered, the power consumption greatly reduced, but the wake-up time is longer. When maintaining MR power supply, the chip consumes a lot of power but has the ability to quickly wake up for several cycles.
In addition, in run mode, the power consumption can be reduced by the following methods:
- Decrease system clock frequency
- For unused peripherals, turn off peripheral clocks (system clock and module clock)
| | | wakeup | Wake-up | Effects on the clock | Voltage regulator | | | |
|----------------------|-------------------------------------------------------------------------------------------------------------------------|--------------------------------------------------------|------------------------------------------------------------------------------------------------------------------------------|-----------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------|-------------------|---------------------------|--|--|
| 模式 | 进入 | | clock | | MR | LPR | | |
| Sleep<br>(sleep-now | WFI or Return<br>from ISR | Any interruptipn | Same as be<br>fore entering | The CPU clock is off<br>and has no effect on | On(1) | off | | |
| or sleep-on<br>exit) | WFE | Wakeup event | sleep mode | other clocks and clock<br>sources | | | | |
| Stop | SLEEPDEEP bit<br>1.WFI or<br>2.Return<br>from ISR or<br>3.WFE<br>Note: The sys<br>tem clock cannot<br>select LSI or LSE | Any EXTI line<br>configured to<br>wake<br>up,IWGD,NRST | HSISYS<br>HSI maintains<br>the frequency<br>configuration<br>before entering<br>stop and does<br>not divide the<br>frequency | HSI Off.<br>LSI and LSE can be<br>turned on or off.<br>LPTIMER, IWDG:<br>Whether it is configured<br>by software or not.<br>Low-power wakeup and<br>some modules such as<br>RCC keep working.<br>Clocks of the remaining<br>modules are turned off. | On | Output<br>voltage<br>1.0v | | |
#### Table 6-1 Low power mode switch
1. The software must configure the VR state as MR mode to enter sleep mode
## <span id="page-50-3"></span>**6.1.2. Functions in each working mode**
Table 6-2 Functions in each working mode(1)
| | | | | Stop | | | | | |
|------------|-----|-------|-----------------|----------------|--|--|--|--|--|
| Peripheral | Run | Sleep | VR@LPR or VR@MR | Wakeup ability | | | | | |
| CPU | Y | - | - | - | | | | | |
| | | | Stop | | | | |
|------------------------------------|-----|-------|-----------------|----------------|--|--|--|
| Peripheral | Run | Sleep | VR@LPR or VR@MR | Wakeup ability | | | |
| Flash memory | Y | Y | -(2) | - | | | |
| SRAM | Y | O(3) | -(4) | - | | | |
| Brown-out reset (BOR) | Y | Y | O | O | | | |
| PVD | O | O | O | O | | | |
| HSI | O | O | - | - | | | |
| HSE | O | O | - | - | | | |
| LSI | O | O | O | - | | | |
| LSE | O | O | O | - | | | |
| LSE Clock Security System<br>(CSS) | O | O | O | O | | | |
| USART1 | O | O | - | - | | | |
| USART2 | O | O | - | - | | | |
| I2C | O | O | - | - | | | |
| SPI1 | O | O | - | - | | | |
| SPI2 | O | O | - | - | | | |
| ADC | O | O | - | - | | | |
| COMP1/COMP2 | O | O | O | O | | | |
| Temperature sensor | O | O | - | - | | | |
| Timers(TIM1/TIM14) | O | O | - | - | | | |
| LPTIM | O | O | O | O | | | |
| IWDG | O | O | O | O | | | |
| SysTick timer | O | O | - | - | | | |
| CRC | O | O | - | - | | | |
| GPIOs | O | O | O | O | | | |
1. Y = Yes (enable), O = Optional (default disabled, can be enabled by software), - = Not available.
2. Flash is not powered off, but no clock is provided, and it enters the lowest power consumption state.
3. SRAM clock can be turned on or off.
4. SRAM is not powered off, but no clock is provided, and it enters the lowest power consumption state.
5. Before entering stop mode, if LSE CSS is enabled, when a problem with LSE CSS, it will wake up the system and enter the NMI interrupt.
## <span id="page-51-0"></span>**6.2. Sleep mode**
#### <span id="page-51-1"></span>**6.2.1. Entering sleep mode**
The sleep mode is entered by executing the WFI (wait for interrupt) or WFE (wait for event) instructions. Two option are available to select the sleep mode entry mechanism, depending on the SLEEPONEXIT bit in the Cortex M0+ System Control Register.
- Sleep-now: If the SLEEPONEXIT bit is 0, to enter sleep mode as soon as WFI or WFE instruction is excuted.
- Sleep-on-exit: If the SLEEPONEXIT bit is 1, to enter sleep mode as soon as it exits the low priority ISR.In the sleep mode, all IO pins keep the same state as in the run mode.
#### <span id="page-51-2"></span>**6.2.2. Exiting sleep mode**
If the WFI instruction is used to enter sleep mode, any peripheral interrupt acknowledged by NVIC can wake up the device from sleep mode.
If the WFE instruction is used to enter sleep mode, the chip exits sleep mode as soon as an event occurs. The wakeup events can be generated in the following ways:
- Enable interrupts in the peripheral control register but not in the NVIC, and enabling the SEVONPEND bit in the Cortex M0+. When the chip wakes up from WFE and continues execution, the peripheral interrupt pending bit and the peripheral NVIC IRQ channel pending bit (in the NVIC interrupt clear pending register) must be cleared.
- Or configuring an external or internal EXTI line in event mode. When the CPU wakes up from WFE and continues execution. it is not necessary to clear the peripheral interrupt pending bit or the NVIC IRQ channel pending bit corresponding to the event line is not set.
- This mode offer the shortest wakeup time, and no time is wasted in interrupt entry and exit.
| Sleep-now | Description | | | | | | |
|----------------|---------------------------------------------------------------------|--|--|--|--|--|--|
| | WFI(Wait for Interrupt) or WFE(Wait for Event) while: | | | | | | |
| Mode entry | - - SLEEPDEEP = 0 and | | | | | | |
| | - - SLEEPONEXIT = 0 | | | | | | |
| | Enter the sleep mode through WFI, the exit method is: interrupt. | | | | | | |
| Mode exit | Enter the sleep mode through WFE, the exit method is: wakeup event. | | | | | | |
| Wakeup latency | None | | | | | | |
| | Table 6-4 Sleep-on-exit |
|--|-------------------------|
| | |
| Sleep-on-exit | Description | | | | | |
|----------------|------------------------------------------------------------|--|--|--|--|--|
| Mode entry | WFI while:<br>- - SLEEPDEEP = 0 and<br>- - SLEEPONEXIT = 1 | | | | | |
| Mode exit | Interrupt | | | | | |
| Wakeup latency | None | | | | | |
## <span id="page-52-0"></span>**6.3. Stop mode**
The stop mode is based on the Cortex-M0+ Deepsleep mode combined with peripheral clock gating, The voltage regulator(VR) can be configured either in MR or Low-power mode. In stop mode, HSI and HSE are turned off, SRAM and register contents are kept in a state, LSI, LSE, LPTIMER, IWDG can be configured by software whether to work, low-power wake-up and partial RCC logic maintenance work, the clock inputs to the digital blocks of the remaining VCORE domains are turned off. In the stop mode, all I/O pins keep the same state as in Run mode.
## <span id="page-52-1"></span>**6.3.1. Entering stop mode**
To further reduce power consumption in stop mode, when PWR\_CR.LPR = 1, VR can enter LPR to supply power.
If Flash memory programming is ongoing, the stop mode entry is delayed until the memory access is finished (the BSY bit of the FLASH\_SR register is read by software to determine whether the current erase and program operations have been completed).
If an access to the APB domain is ongoing, the stop mode entry is delayed until the APB access is finished (controlled by software).
## <span id="page-52-2"></span>**6.3.2. Exiting Stop mode**
When exiting stop mode by issuing an interrupt or a wakeup event, the HIS oscillator is selected as system clock.
In stop mode, if VR is in LPR state, there is an additional stabilization delay for wakup in stop mode.
In stop mode, if VR is in MR state, the current consumption will be large, but the wakeup time will be reduced.
| Table 6-5 stop mode | | | | | | | |
|---------------------|--------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------|--|--|--|--|--|--|
| Stop mode | Description | | | | | | |
| Mode entry | WFI (wait for interrupt) or WFE (wait for event) while:<br>- Configuration settings:<br>1)Configure the LPR bit of PWR_CR, to select VR to work under MR or LPR.<br>2)Configure the MRRDY_TIME and FLS_SLPTIME of PWR_CR, to set wake-up time of MR and<br>Flash.<br>- Set the SLEEPDEEP bit of Cortex M0+<br>Note:<br>To enter stop mode, all EXTI line pending bits (EXTI_PR register), all peripheral interrupt pending<br>bits and RTC alarm flags must be reset. OtheRWise, the stop mode entry proceduce is ignored<br>and program execution continues.<br>If the application needs to disable HSE before entering stop mode, the system clock source must<br>be first switched to HSI and then clear the HSEON bit.<br>To make the change of chip power consumption as balanced as possible, the software needs to<br>follow the principle of gradual shutdown: gradually shut down the clock of each module, select HSI<br>as the system clock, close PLL and HSE.<br>To shorten the wakeup time, before entering the stop mode, the system clock should be configured | | | | | | |
| | to select the HSI high-frequency clock, and the HPRE of the RCC_CFGR register is set to 0,<br>otheRWise the hardware switching clock after wake-up will consume extra clocks. | | | | | | |
| Mode exit | If using WFI to enter stop mode:<br>- Any EXTI Line configured in interrupt mode (the corresponding EXTI interrupt vector must be<br>enabled in the NVIC).<br>If using WFE to enter stop mode:<br>- Any EXTI Line configured in event mode.<br>- Interrupt pending bit when the CPU SEVONPEND bit is set. | | | | | | |
| Wakeup latency | MR from LPR wakeup time+HIS wakeup time+FLASH wakeup time | | | | | | |
## <span id="page-53-0"></span>**6.4. Decreasing system clock frequency**
In run mode, the frequency divided of the system clock (SYSCLK, HCLK, PCLK) can be reduced through the prescaler register configuration. These prescalers can also be used to reduce the frequency of peripherals before entering sleep mode.
When the system runs at a lower frequency (32.768 kHz), to obtain less power consumption, software can set the drive capability configuration bit of the voltage regulator (MR) (PWR\_CR1 register BIAS\_CR [3:0]), which greatly reduces the power consumption of MR itself. But it should be noted that the system clock frequency should be reduced first, and then the driving capability of the MR should be adjusted. On the contrary, when exiting the lower frequency and entering the higher operating frequency, it need increase the driving capacity of the MR first, and then change the operating frequency of the system clock.
## <span id="page-53-1"></span>**6.5. Peripheral clock gating**
In run mode, the AHB clock (HCLK) and APB clock (PCLK) for individual peripherals and memories can be stopped at any time to reduce power consumption.
To reduce the power consumption in sleep mode, peripheral clocks can be stopped before executing WFI or WFE instructions.
## <span id="page-53-2"></span>**6.6. Power management register**
The peripheral 's registers can be accessed through half-word or word.
## <span id="page-54-0"></span>**6.6.1. Power control register 1 (PWR\_CR1)**
#### **Address offset:** 0x00
| | Reset value: 0x0007 0000(reset by POR) | | | | | | | | | | | | | | |
|---------|----------------------------------------|-----|-----|---------|---------|---------|---------|---------|---------|---------|-----------------|------------------------|-----|--------------|---------|
| 31 | 30 | 29 | 28 | 27 | 26 | 25 | 24 | 23 | 22 | 21 | 20 | 19 | 18 | 17 | 16 |
| R<br>es | R<br>es | Res | Res | R<br>es | R<br>es | Re<br>s | Re<br>s | R<br>es | R<br>es | R<br>es | Res | HSI<br>ON<br>_CT<br>RL | Res | SRAM_<br>RET | R<br>es |
| | | | | | | | | | | | | RW | | RW | R<br>W |
| 15 | 14 | 13 | 12 | 11 | 10 | 9 | 8 | 7 | 6 | 5 | 4 | 3 | 2 | 1 | 0 |
| | FLS_SLP<br>LPR<br>TIME[1:0] | | | R<br>es | R<br>es | Re<br>s | Re<br>s | R<br>es | R<br>es | R<br>es | BIAS_CR<br>_SEL | BIAS_CR[3:0] | | | |
| RW | | | RW | | | | | | | | RW | RW | | | |
| Bit | Name | R/W | Reset<br>Value | Function |
|-------|-------------|-----|----------------|--------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------|
| 31:20 | Reserved | - | - | Reserved |
| 19 | HSION_CTRL | RW | 0 | HSI turns on time control when wakeup from stop mode.<br>0: After waiting for MR to stabilize, enable HIS.<br>1: Turn on the VR, as well as enable HSI when wakeup |
| 18 | Reserved | - | - | Reserved |
| 17 | SRAM_RETV | RW | 1'b1 | SRAM retention voltage control in stop mode<br>1:SRAM voltage is consistent with digital LDO output.<br>0:SRAM voltage is the low. |
| 15:14 | LPR | | 0 | Low power regulator<br>VR_LPR_CR=2'b00, MR mode (default set)<br>VR_LPR_CR=2'b01, Low Power Run mode<br>Others:Reseved |
| 13:12 | FLS_SLPTIME | RW | 2'b00 | Wakeup sequence from stop mode, after the HSI is stable, a<br>waiting time is required before the Flash operation.<br>2'b00: 5us<br>2'b01: 2us<br>2'b10: 3us<br>2'b11: 0us<br>Note: When this register is set to 2'b11, it means that the pro<br>gram is executed from SRAM instead of Flash after wakeup. And<br>the program guarantees that Flash will not be accessed within 3<br>us after waking up the execution program. |
| 11:5 | Reserved | - | - | Reserved |
| 4 | BIAS_CR_SEL | RW | 0 | Select the MR bias current from the configuration of the<br>BIAS_CR register or from the loading of the Factory config.bytes<br>area of the information memory.<br>0: Select the load from the Factory config.bytes area<br>1: Select from BIAS_CR register |
| 3:0 | BIAS_CR | RW | 4'b0000 | MR bias current configuration.<br>4'b0000:<br>… |
## <span id="page-54-1"></span>**6.6.2. PWR register map**
| Of<br>fs<br>et | Reg<br>iste<br>r | 31 | 30 | 29 | 28 | 27 | 26 | 25 | 24 | 23 | 22 | 21 | 20 | 19 | 18 | 17 | 16 | 15 | 14 | 13 | 12 | 11 | 10 | 9 | 8 | 7 | 6 | 5 | 4 | 3 | 2 | 1 | 0 |
|----------------|------------------------|------|------|------|------|------|------|------|------|------|------|------|------|------------|------|-----------|------|------|-----|----|------------------|----------------|----|------|------|------|------|------|-------------|---|--------------|---|---|
| 0x<br>00 | PW<br>R_C<br>R1 | Res. | Res. | Res. | Res. | Res. | Res. | Res. | Res. | Res. | Res. | Res. | Res. | HSION_CTRL | Res. | SRAM_RETV | Res. | Res. | LPR | | FLS_SLPTIME[1:0] | MRRD_TIME[1:0] | | Res. | Res. | Res. | Res. | Res. | BIAS_CR_SEL | | BIAS_CR[3:0] | | |
| | Re<br>set<br>valu<br>e | | | | | | | | | | | | | 0 | | 1 | | | 0 | 0 | 0 | | | | | | | | 0 | 0 | 0 | 0 | 0 |
## <span id="page-55-0"></span>**7. Reset**
There are two types of resets defined as power reset and system reset.
## <span id="page-55-1"></span>**7.1. Reset source**
## <span id="page-55-2"></span>**7.1.1. Power reset**
A power reset sets all registers to their reset value, which occurs in the following situations:
- Power on/Down reset(POR/PDR)
- Brown-out reset(BOR)
#### <span id="page-55-3"></span>**7.1.2. System reset**
A system reset sets most registers to their reset values, except some special registers, such as the reset flag register.
A system reset generates when the following events occur:
- Reset of NRST pin
- Independent watchdog reset (IWDG)
- SYSRESETREQ software reset
- Option byte load reset (OBL)
- Power reset (POR/PDR, BOR)
The reset source can be identified by checking the reset flag bits of the RCC\_CSR register.
### <span id="page-55-4"></span>**7.1.3. NRST pin (external reset)**
By loading the option byte (NRST\_MODE bit), the NRST pin can be configured in the following modes (see option byte description for specific configuration):
Reset input
In this mode, any valid reset signal on the NRST pin is passed to the internal logic, but the reset generated inside the chip is not output on the NRST pin.
In this configuration mode, the PC0 function of the GPIO is invalid.
There is burr filtering for NRST pin. The design ensures that NRST must meet the minimum width of 20 us, and the signal less than this width will be filtered out.
GPIO
In this mode, the PIN can be used as a standard GPIO, like PC0. The reset function on the pin does not work. Resets are only generated internally by the chip and cannot be passed to the pin.
![](_page_56_Figure_1.jpeg)
Figure 7-1 Simplified diagram of the reset circuit
## <span id="page-56-0"></span>**7.1.4. Watchdog reset**
See independent watchdog for details.
#### <span id="page-56-1"></span>**7.1.5. Software reset**
A software reset can be achieved by setting the SYSRESETREQ bit in the ARM M0+ interrupt and reset control register.
### <span id="page-56-2"></span>**7.1.6. Option byte loader reset**
By configuring FLASH\_CR.OBL\_LAUNCH = 1, the software generates an option byte load reset, thereby starting the option byte load again.
# <span id="page-57-0"></span>**8. Clock**
## <span id="page-57-1"></span>**8.1. Clock source**
## <span id="page-57-2"></span>**8.1.1. High-speed external clock (HSE)**
The high-speed external clock can be generated from two sources:
- External clock input from PA6.
- PA6 automatically enables the input of the I/O when the external clock signal is enabled,and PA6 is prohibited from being used as GPIO.
## **8.1.2. Low-speed external clock (LSE)**
<span id="page-57-3"></span>The low-speed external clock (LSE) can be generated from two sources:
- Through an external crystal , with the internal start-up circuit, a clock signal of 32.768 kHz is generated.
- Input high-speed clock source directly from external.
LSERDY flag in the RCC\_BDCR register shows whether the LSE is stable.LSE can be turned on or off by the LSEON bit.The drive capability can be adjusted via LSEDRV[1:0] to obtain a compromise between robustness and short startup time.
#### **External clock source(LSE bypass)**
In this mode, an external clock source is provided. This mode is selected by software through the LSEBYP and LSEON bits of RCC\_CR.
## <span id="page-57-4"></span>**8.1.3. High-speed internal clock (HSI)**
The high-speed internal clock is the most important source of the chip system clock. The center frequency of the HSI clock source is designed to be 24 MHz.
## <span id="page-57-5"></span>**8.1.4. Low-speed internal clock (LSI)**
The low-speed internal clock, as the clock for IWDG and LPTIM, and as the system clock when the chip is running at low speed. The clock center frequency is designed at 32.768 kHz and 38.4KHz.
## <span id="page-57-6"></span>**8.2. Clock tree**
![](_page_58_Figure_1.jpeg)
Figure 8-1 System clock structure
## <span id="page-58-0"></span>**8.3. Clock security system (CSS)**
The clock security system can be activated by software. In this case, the clock detection is enable after the LSE oscillator startup delay, and disabled when this oscillator is stopped.
If a failure is detected on the LSE clock, the LSE oscillator is automatically disable, a clock failure event is sent to the break input of advanced-control timer (TIM1) and General-purpose timer (TIM14) and an interrupt is generated to inform the software of the failure (Clock Security System Interrupt CSSI), which allows the MCU to perform rescue operations. CSSI is linked to the Cortex-M0+ NMI (Non-maskable interrupt) exception vector.
Note: Once the CSS is enabled and if the LSE clock fails, the CSS interrupt occurs and an NMI is automatically generated. The NMI will be executed indefinitely unless the CSS interrupt pending bit is cleared. Therefore, in the NMI processing programs,it is necessary to clear the CSS interrupt by setting the CSSC bit in the clock interrupt register (RCC\_CICR).
If the LSE oscillator is used directly or indirectly as the system clock, a detected failure cause a switch of the system clock to the LSI oscillator and the disabling of the LSE oscillator.
## <span id="page-58-1"></span>**8.4. Clock-out capability**
In order to facilitate board-level applications, save BOM costs and debug requirements, the chip needs to provide a clock output function. That is, the divided MCO signal in the following table is used to realize the clock output function through the multiplexing function of GPIO.
| Clock source | MCO output clock source |
|--------------|-------------------------|
| HSI | √ |
| SYSCLK | √ |
| HSE | √ |
| LSE | √ |
| LSI | √ |
Table 8-1 Output clock selection
Note: When switching the MCO clock source and selecting the GPIO AF function as the initial stage of the MCO,the MCO may generate glitches, and this period of time needs to be avoided.
## <span id="page-59-0"></span>**8.5. Internal and external clock calibration with TIM14**
Due to factors of temperature, voltage, process and production, the frequency of internal clock sources (such as HSI, LSI, etc.) drifts. Therefore, it is necessary to take some necessary measures to calibrate the frequency drift according to the change of the external working environment of the system.
The basic idea of clock drift processing is: when the external environment of the system changes, the internal clock of the chip is dynamically measured in real time to detect and find problems. Then, the trimming parameters of the internal clock are fine-tuned by software to achieve the purpose of dynamic calibration.
## <span id="page-59-1"></span>**8.5.1. HSI calibration**
HSI clock calibration is divided into two parts: clock detection and clock calibration.
### **Clock measurement**
The rationale is based on relative measurements (such as the ratio of HSI/LSE), and the accuracy is closely related to the ratio of the two clock sources. The higher the ratio, the better the measurement.
HSI clock counts between consecutive edges of the LSE signal. Using the high accuracy (ppm level) of the LSE, the user can measure the clock frequency with the same resolution and can compensate for production, process, temperature and voltage related frequency deviations by fine-tuning the clock source.
HSI oscillators have dedicated calibration bits for this purpose and are user accessible. If LSE is not available, select HSE/32 for the most accurate calibration possible. The frequency of the HSI is measured by capturing the signal through the channel 1 input of the TIM14.
![](_page_59_Figure_14.jpeg)
Figure 8-2 Frequency measurement with TIM14 in capture mode
The input capture channel of TIM14 can be a GPIO or an in-chip clock. The selection of these clocks is implemented through the TI1\_RMP [1:0] register of TIM14\_OR. The four options are as follows:
- TIM14 channel 1 is connected to GPIO
- TIM14 channel 1 is connected to HSE/32 Clock
- TIM14 channel 1 is connected to MCO (Microcontroller clock output)
#### **Clock division**
Once the abnormality of HSI clock is detected, it will notify the software to deal with it through interrupt. The software achieves the purpose of dynamic calibration by fine-tuning the trimming parameters of the internal clock.
Connect LSE to the input capture of TIM14 channel 1 through MCO multiplexer, its main purpose is to measure HSI accurately (in this case, HSI should be set as the system clock source). Such a mechanism provides a measure of the internal clock period by counting the number of HSI clocks during two consecutive LSE signal transition edges.
the LSE high precision (ppm) when an external crystal oscillators is used, so that it is possible to determine the internal clock frequency with the same resolution, and then trim the clock source to compensate for the frequency drift related to process, temperature and voltage.
HSI is therefore designed with special user-accessible calibration register bits.
The rationale for this implementation mechanism is a relative measure (eg, the ratio of HSI/LSE): the accuracy is thus closely related to the ratio of the frequencies of the two clock sources. The higher the ratio, the better the measure.
#### <span id="page-60-0"></span>**8.5.2. LSI calibration**
Like HSI, the clock frequency of LSI is also affected by voltage, temperature, process and production drift. The calibration of LSI adopts HSE or HSI whose frequency differs greatly from the calibration, and the calibration method is similar to that of HSI.
The calibration of the LSI is to connect the output of the LSI and the input capture of the TIM14. Define the HSE as the system clock source, and provide a measure of the LSI cycle in the number of HSE clocks of two consecutive LSIs.
In principle, it is still the relationship between relative frequencies, that is, the frequency ratio of HSE/LSI: the calibration accuracy is closely related to this. The larger the ratio value, the better the measurement.
## <span id="page-60-1"></span>**8.6. Reset/clock register**
The registers of this module can be accessed with word (32-bit), half-word (16-bit) and byte (8-bit).
## <span id="page-60-2"></span>**8.6.1. Clock control register (RCC\_CR)**
#### **Address offset:**0x00
| 31 | 30 | 29 | 28 | 27 | 26 | 25 | 24 | 23 | 22 | 21 | 20 | 19 | 18 | 17 | 16 |
|-----|-----|-----|-----|-----|-----|-----|-----|-----|-----|-----|-----|-----|-----------|-----|-----|
| Res | Res | Res | Res | Res | Res | Res | Res | Res | Res | Res | Res | Res | HSE<br>ON | Res | Res |
| | | | | | | | | | | | | | RW | | |
| 15 | 14 | 13 | 12 | 11 | 10 | 9 | 8 | 7 | 6 | 5 | 4 | 3 | 2 | 1 | 0 |
|-----|-----|-------------|----|----|------------|-----|-------|-----|-----|-----|-----|-----|-----|-----|-----|
| Res | Res | HSIDIV[2:0] | | | HSI<br>RDY | Res | HSION | Res | Res | Res | Res | Res | Res | Res | Res |
| | | | RW | | R | RW | RW | | | | | | | | |
| Bit | Name | R/W | Reset Value | Function | | | | | | | |
|-------|-------------|-----|-------------|--------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------|--|--|--|--|--|--|--|
| 31:19 | Reserved | - | - | Reserved | | | | | | | |
| 18 | HSEEN | RW | 0 | external clock enable | | | | | | | |
| 17:14 | Reserved | - | - | Reserved | | | | | | | |
| 13:11 | HSIDIV[2:0] | RW | 0 | HSI clock division factor.<br>Software controls these bits to set the frequency division<br>factor of HSI to generate the HSISYS clock<br>000:1<br>001:2<br>010:4<br>011:8<br>100:16<br>101:32<br>110:64<br>111:128 | | | | | | | |
| 10 | HSIRDY | R | 0 | HSI clock ready flag.<br>Set by hardware to indicate HSI OSC is stable.This bit is<br>only valid when HSION=1<br>0:HSI OSC not ready;<br>1:HSI OSC ready;<br>When HSION is cleared, HSIRDY will be pulled low imme<br>diately. | | | | | | | |
| 9 | Reserved | - | - | Reserved | | | | | | | |
| 8 | HSION | RW | 1 | HSI clock enable bit. Software can set and clear this bit.<br>When entering s top mode, the hardware clears this bit to<br>stop HSI.<br>When the HSI is used directly or indirectly as the system<br>clock (also when exiting stop mode, or when the HSE is<br>used as the system clock and fails).<br>0: HSI OFF<br>1: HSI ON | | | | | | | |
| 7:0 | Reserved | - | - | Reserved | | | | | | | |
## <span id="page-61-0"></span>**8.6.2. Internal clock source calibration register (RCC\_ICSCR)**
#### **Address offset:**0x04
#### **Reset value:**0x00FF 10FF, reset by POR/BOR
| 31 | 30 | 29 | 28 | 27 | 26 | 25 | 24 | 23 | 22 | 21 | 20 | 19 | 18 | 17 | 16 | | | |
|-----|-------------|-----|-----|----|-------------|-----|---------------|----------------|----|----|----|----|----|----|----|--|--|--|
| Res | Res | Res | Res | | LSI_STARTUP | Res | LSI_TRIM[8:0] | | | | | | | | | | | |
| | | | | RW | RW | | RW | RW | RW | RW | RW | RW | RW | RW | RW | | | |
| 15 | 14 | 13 | 12 | 11 | 10 | 9 | 8 | 7 | 6 | 5 | 4 | 3 | 2 | 1 | 0 | | | |
| | HSI_FS[2:0] | | | | | | | HSI_TRIM[12:0] | | | | | | | | | | |
| RW | RW | RW | RW | RW | RW | RW | RW | RW | RW | RW | RW | RW | RW | RW | RW | | | |
| Bit | Name | R/W | Reset Value | Function |
|-------|-------------|-----|-------------|--------------------------------------------------------------------------------------------------------------------------------------------------------------------------|
| 31:28 | Reserved | | - | Reserved |
| 27:26 | LSI_STARTUP | RW | 2'b00 | Low-speed internal clock (LSI) stabilization time selec<br>tion:<br>11:256 LSI clock cycles<br>10:64 LSI clock cycles<br>01:16 LSI clock cycles<br>00:4 LSI clock cycles |
| 25 | Reserved | | | |
| Bit | Name | R/W | Reset Value | Function |
|-------|----------|-----|-------------|-------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------|
| 24:16 | LSI_TRIM | RW | 0x0FF | Low-speed internal clock frequency calibration. Low<br>speed internal clock can output 32.768 kHz and<br>38.4KHz frequency though calibration.<br>After power-on, the chip hardware will write the factory<br>information (stored in 0x1FFF 0144) into this register to<br>achieve calibtration at a specific output frequency of the<br>LSI.<br>The calibration values are saved in Flash at the follow<br>ing address:<br>32.768KHz calibration value address: 0x1FFF 0144<br>38.4KHz calibration value address: 0x1FFF 0148<br>By rewriting the value of this register, the software in<br>creases (decrease) the output frequency of LSI by about<br>0.2% for each increase (decrease) by 1. |
| 15:13 | HSI_FS | RW | 3'b000 | HSI frequency selection:<br>100:24 MHz<br>others: reserved<br>After power-on,24 MHz is selected by default. |
| 12:0 | HSI_TRIM | RW | 0x10FF | Clock frequency calibration value.<br>After power-on,the hardware uses the default calibration<br>value of HSI 24 MHz,and the factory information(stored<br>in 0x1FFF 0100) will be written into this register when<br>trimming.<br>The software reads out the data stored in the correspond<br>ing address in the information area and writes it into the<br>register to realize the calibration under the specific output<br>frequency of the HSI.<br>Save it in the following address of Flash:<br>24 MHz calibration value storage address offset: 0x1FFF<br>0100<br>After writing the calibration value to this register,it can<br>also be used as the centre value.Modify the value of this<br>register.and for each increase(decrease)by 1,the output<br>frequency of the HSI will increase(decrease)by about<br>0.1%. |
## <span id="page-62-0"></span>**8.6.3. Clock configuration register (RCC\_CFGR)**
#### **Address offset:**0x08
| 31 | 30 | 29 | 28 | 27 | 26 | 25 | 24 | 23 | 22 | 21 | 20 | 19 | 18 | 17 | 16 |
|-----|----|-------------|----|-----|-------------|-----------|----|-----|-----|-----|----------|-----|-----|---------|-----|
| Res | | MCOPRE[2:0] | | Res | MCOSEL[2:0] | | | Res | Res | Res | Res | Res | Res | Res | Res |
| | | RW | | | RW | | | | | | | | | | |
| 15 | 14 | | | | | | | | | | | | | | |
| | | 13 | 12 | 11 | 10 | 9 | 8 | 7 | 6 | 5 | 4 | 3 | 2 | 1 | 0 |
| Res | | PPRE[2:0] | | | | HPRE[3:0] | | Res | Res | | SWS[2:0] | | | SW[2:0] | |
| Bit | Name | R/W | Reset Value | Function |
|-------|-------------|-----|-------------|---------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------|
| 31 | Reserved | - | - | Reserved |
| 30:28 | MCOPRE[2:0] | RW | 0 | Microcontroller clock output(MCO) division factor. Soft<br>ware controls these bits to set the division factor of the<br>MCO output:<br>000:1<br>001:2<br>010:4<br>011:8<br>100:16<br>101:32<br>110:64<br>111:128<br>Set these bits before enabling the MCO output. |
| 27 | Reserved | - | - | Reserved |
| Bit | Name | R/W | Reset Value | Function |
|-------|-------------|-----|-------------|---------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------|
| | | | | MCO selection |
| 26:24 | MCOSEL[2:0] | RW | 0 | 000: No clock, MCO output disabled<br>001: SYSCLK<br>010: Reserved<br>011: HSI<br>100: HSE<br>101: Reserved<br>110: LSI<br>111: LSE<br>Note: Incomplete output clock conditions may occur during<br>the clock startup or switchover phase. |
| 23:15 | Reserved | - | - | Reserved |
| 14:12 | PPRE[2:0] | RW | 0 | This bit is controlled by software. To generate the PCLK<br>clock, it sets the division factor of HCLK as follows:<br>0xx:1<br>100:2<br>101:4<br>110:8 |
| | | | | 111:16<br>AHB clock division factor. |
| 11:8 | HPRE[3:0] | RW | 0 | Software controls this bit. In order to generate the HCLK<br>clock, it sets the frequency division factor of SYSCLK as<br>follows:<br>0xxx: 1<br>1000: 2<br>1001: 4<br>1010: 8<br>1011: 16<br>1100: 64<br>1101: 128<br>1110: 256<br>1111: 512<br>In order to ensure the normal operation of the system, it is<br>necessary to configure an appropriate frequency according<br>to the VR power supply.<br>Note: It is recommended to switch the division factor step<br>by step. |
| 7:6 | Reserved | - | - | Reserved |
| 5:3 | SWS[2:0] | R | 0 | System clock switch status bits<br>These bits are controlled by hardware and indicate which<br>clock source is currently being used as the system clock:<br>000: HSISYS<br>001: HSE<br>010: Reserved<br>011: LSI<br>100: LSE<br>Others: Reserved |
| 2:0 | SW[2:0] | RW | 0 | System clock source selection bits.<br>Controlled by software and hardware, these bits select the<br>system clock:<br>000: HSISYS<br>001: HSE<br>010: Reserved<br>011: LSI<br>100: LSE<br>Others: Reserved<br>The hardware is configured as HSISYS include:<br>1) The system exits from stop mode<br>2) Software configuration 001 (HSE), HSE failure occurs<br>(HSE is the system clock source) |
## <span id="page-63-0"></span>**8.6.4. External clock source control register (RCC\_ECSCR)**
**Address offset:**0x10
| 31 | 30 | 29 | 28 | 27 | 26 | 25 | 24 | 23 | 22 | 21 | 20 | 19 | 18 | 17 | 16 |
|-----|-----|-----|-----|-----|-----|-----|-----|-----|-----|-------------|-----|-----|----|------------|----|
| Res | Res | Res | Res | Res | Res | Res | Res | Res | Res | LSE_STARTUP | | Res | | LSE_DRIVER | |
| | | | | | | | | | | RW | | | | RW | |
| 15 | 14 | 13 | 12 | 11 | 10 | 9 | 8 | 7 | 6 | 5 | 4 | 3 | 2 | 1 | 0 |
| Res | Res | Res | Res | Res | Res | Res | Res | Res | Res | Res | Res | Res | | Res | |
| | | | | | | | | | | | | | | | |
| | | | | | | | | | | | | | | | |
#### **Reset value:** 0x0001\_0000
| 31:18<br>Reserved<br>RES<br>-<br>Reserved<br>LSE crystal oscillator stability time selection.<br>LSEBYP=0:<br>00:4096 LSE clock cycles.<br>01:2048 LSE clock cycles.<br>10:8192 LSE clock cycles.<br>11: Directly output without considering stabil<br>21:20<br>LSE_STARTUP<br>RW<br>0x0<br>ity time<br>LSEBYP=1:<br>00:2048 LSE clock cycles.<br>01:1024 LSE clock cycles.<br>10:4096 LSE clock cycles.<br>11: Directly output without considering stabil<br>ity time<br>Low-speed crystal oscillator drive capability se<br>lection<br>00:The weakest driving ability<br>01:Weak driving ability<br>10:Default drive capability (recommended)<br>11:The strongest driving ability<br>17:16<br>LSE_DRIVER<br>RW<br>0x10<br>tion. | Bit | Name | R/W | Reset Value | Function |
|-----------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------|------|----------|-----|-------------|--------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------|
| | | | | | |
| | | | | | |
| | | | | | Note: The proper drive capability needs to be se<br>lected according to the crystal characteristics,<br>load capacitance and parasitic parameters of the<br>circuit board. The greater the driving ability, the<br>greater the power consumption and the weaker<br>the driving ability, the less the power consump |
| | 15:0 | Reserved | | - | |
## <span id="page-64-0"></span>**8.6.5. Clock interrupt enable register (RCC\_CIER)**
#### **Address offset:**0x18
| 31 | 30 | 29 | 28 | 27 | 26 | 25 | 24 | 23 | 22 | 21 | 20 | 19 | 18 | 17 | 16 |
|-----|-----|-----|-----|-----|-----|-----|-----|-----|-----|-----|-----|-------|-----|-------|-------|
| Res | Res | Res | Res | Res | Res | Res | Res | Res | Res | Res | Res | Res | Res | Res | Res |
| | | | | | | | | | | | | | | | |
| 15 | 14 | 13 | 12 | 11 | 10 | 9 | 8 | 7 | 6 | 5 | 4 | 3 | 2 | 1 | 0 |
| | | | | | | | | | | | | HSI | | LSE | LSI |
| Res | Res | Res | Res | Res | Res | Res | Res | Res | Res | Res | Res | RDYIE | Res | RDYIE | RDYIE |
| | | | | | | | | | | | | RW | | RW | RW |
| Bit | Name | R/W | Reset Value | Function |
|------|----------|-----|-------------|-----------------------------------|
| 31:4 | Reserved | - | - | Reserved |
| | | | | HSI clock ready interrupt enable. |
| 3 | HSIRDYIE | RW | 0 | 0:Disable |
| | | | | 1:Enable |
| 2 | Reserved | - | - | Reserved |
| 1 | LSERDYIE | RW | 0 | LSE clock ready interrupt enable. |
| Bit | Name | R/W | Reset Value | Function |
|-----|----------|-----|-------------|-----------------------------------|
| | | | | 0:Disable |
| | | | | 1:Enable |
| | | | | LSI clock ready interrupt enable. |
| 0 | LSIRDYIE | RW | 0 | 0:Disable |
| | | | | 1:Enable |
## <span id="page-65-0"></span>**8.6.6. Clock interrupt flag register (RCC\_CIFR)**
#### **Address offset:**0x1C
**Reset value:**0x0000 0000
| 31 | 30 | 29 | 28 | 27 | 26 | 25 | 24 | 23 | 22 | 21 | 20 | 19 | 18 | 17 | 16 |
|-----|-----|-----|-----|-----|-----|-------------|-----|-----|-----|-----|-----|-------------|-----|-------------|-------------|
| Res | Res | Res | Res | Res | Res | Res | Res | Res | Res | Res | Res | Res | Res | Res | Res |
| | | | | | | | | | | | | | | | |
| 15 | 14 | 13 | 12 | 11 | 10 | 9 | 8 | 7 | 6 | 5 | 4 | 3 | 2 | 1 | 0 |
| Res | Res | Res | Res | Res | Res | LSE<br>CSSF | Res | Res | Res | Res | Res | HSI<br>RDYF | Res | LSE<br>RDYF | LSI<br>RDYF |
| | | | | | | R | | | | | | R | | R | R |
| Bit | Name | R/W | Reset Value | Function | | | | |
|-------|----------|-----|-------------|----------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------|--|--|--|--|
| 31:10 | Reserved | - | - | Reserved | | | | |
| 9 | LSECSSF | R | 0 | LSE clock security system (CSS) interrupt flag.<br>When hardware detects LSE, this register is set when the<br>OSC clock fails.<br>0: LSE clock detection failure interrupt is not generated,<br>1: LSE clock detection failure interrupt generation,<br>Programming LSECSSC register 1 clears this bit. | | | | |
| 8:4 | Reserved | - | - | Reserved | | | | |
| 3 | HSIRDYF | R | 0 | HIS ready interrupt flag<br>This bit is set by hardware when HSI is stable and<br>HSIRDYIE is enabled. Software clears this bit by setting<br>the HSIRDYC bit.<br>0: No clock ready interrupt caused by HSI<br>1: Clock ready interrupt caused by HSI | | | | |
| 2 | Res | - | - | Reserved | | | | |
| 1 | LSERDYF | R | 0 | LSE ready interrupt flag<br>This bit is set by hardware when LSE is stable and LSE<br>RDYIE is enabled. Software clears this bit by setting the<br>LSERDYC bit.<br>0: No clock ready interrupt caused by LSE<br>1: Clock ready interrupt caused by LSE | | | | |
| 0 | LSIRDYF | R | 0 | LSI ready interrupt flag<br>This bit is set by hardware when LSI is stable and<br>LSIRDYIE is enabled. Software clears this bit by setting the<br>LSIRDYC bit.<br>0: No clock ready interrupt caused by LSI<br>1: Clock ready interrupt caused by LSI | | | | |
## <span id="page-65-1"></span>**8.6.7. Clock interrupt clear register (RCC\_CICR)**
#### **Address offset:**0x20
| 31 | 30 | 29 | 28 | 27 | 26 | 25 | 24 | 23 | 22 | 21 | 20 | 19 | 18 | 17 | 16 |
|-----|-----|-----|-----|-----|-----|---------|-----|-----|-----|-----|-----|------|-----|------|------|
| Res | Res | Res | Res | Res | Res | Res | Res | Res | Res | Res | Res | Res | Res | Res | Res |
| | | | | | | | | | | | | | | | |
| 15 | 14 | 13 | 12 | 11 | 10 | 9 | 8 | 7 | 6 | 5 | 4 | 3 | 2 | 1 | 0 |
| | | | | | | | | | | | | HSI | | LSE | LSI |
| Res | Res | Res | Res | Res | Res | LSECSSC | Res | Res | Res | Res | Res | RDYC | Res | RDYC | RDYC |
| | | | | | | W | | | | | | W | | W | W |
| Bit | Name | R/W | Reset Value | Function |
|-------|----------|-----|-------------|----------|
| 31:10 | Reserved | - | - | Reserved |
| Bit | Name | R/W | Reset Value | Function |
|-----|----------|-----|-------------|----------------------------------------------------------------------------------------------------------|
| 9 | LSECSSC | W | 0 | LSE clock security system (CSS) interrupt flag is cleared.<br>0: No effect,<br>1: Clear the LSECSSF flag |
| 8:4 | Reserved | - | - | Reserved |
| 3 | HSIRDYC | W | 0 | HSI ready flag is cleared.<br>0: No effect.<br>1: Clear the HSIRDYF bit. |
| 2 | Reserved | - | - | Reserved |
| 1 | LSERDYC | W | 0 | LSE ready flag is cleared.<br>0: No effect.<br>1: Clear the LSERDYF bit. |
| 0 | LSIRDYC | W | 0 | LSI ready flag is cleared.<br>0: No effect.<br>1: Clear the LSIRDYF bit. |
## <span id="page-66-0"></span>**8.6.8. I/O interface reset register (RCC\_IOPRSTR)**
#### **Address offset:**0x24
#### **Reset value:**0x0000 0000
| 31 | 30 | 29 | 28 | 27 | 26 | 25 | 24 | 23 | 22 | 21 | 20 | 19 | 18 | 17 | 16 |
|-----|-----|-----|-----|-----|-----|-----|-----|-----|-----|-----|-----|-----|-------|-------|-------|
| Res | Res | Res | Res | Res | Res | Res | Res | Res | Res | Res | Res | Res | Res | Res | Res |
| | | | | | | | | | | | | | | | |
| | | | | | | | | | | | | | | | |
| 15 | 14 | 13 | 12 | 11 | 10 | 9 | 8 | 7 | 6 | 5 | 4 | 3 | 2 | 1 | 0 |
| | | | | | | | | | | | | | GPIOC | GPIOB | GPIOA |
| Res | Res | Res | Res | Res | Res | Res | Res | Res | Res | Res | Res | Res | RST | RST | RST |
| Bit | Name | R/W | Reset Value | Function |
|------|----------|-----|-------------|--------------------|
| 31:3 | Reserved | - | - | Reserved |
| | | | | I/O PortC reset。 |
| 2 | GPIOCRST | RW | 0 | 0:no effect; |
| | | | | 1:PortC I/O reset; |
| | | | | I/O PortB 复位。 |
| 1 | GPIOBRST | RW | 0 | 0:no effect; |
| | | | | 1:PortB I/O reset |
| | | | | I/O PortA reset。 |
| 0 | GPIOARST | RW | 0 | 0:no effect; |
| | | | | 1:PortA I/O reset |
## <span id="page-66-1"></span>**8.6.9. AHB peripheral reset register (RCC\_AHBRSTR)**
#### **Address offset:**0x28
| 31 | 30 | 29 | 28 | 27 | 26 | 25 | 24 | 23 | 22 | 21 | 20 | 19 | 18 | 17 | 16 |
|-----|-----|-----|------------|-----|-----|-----|--------------|-----|-----|-----|-----|-----|-----|-----|-----|
| Res | Res | Res | Res | Res | Res | Res | Res | Res | Res | Res | Res | Res | Res | Res | Res |
| | | | | | | | | | | | | | | | |
| 15 | 14 | | | | | | | | | | | | | | |
| | | 13 | 12 | 11 | 10 | 9 | 8 | 7 | 6 | 5 | 4 | 3 | 2 | 1 | 0 |
| Res | Res | Res | CRC<br>RST | Res | Res | Res | FLASH<br>RST | Res | Res | Res | Res | Res | Res | Res | Res |
| Bit | Name | R/W | Reset Value | Function |
|-------|----------|-----|-------------|------------------------------------------------------------|
| 31:13 | Reserved | - | - | Reserved |
| 12 | CRCRST | RW | 0 | CRC module reset.<br>0: no effect,<br>1: CRC module reset, |
| 11:9 | Reserved | - | - | Reserved |
| 8 | FLASHRST | RW | 0 | FLASH interface module reset。 |
| Bit | Name | R/W | Reset Value | Function |
|-----|----------|-----|-------------|---------------------------------|
| | | | | 0:no effect; |
| | | | | 1:FLASH interface module reset; |
| 7:0 | Reserved | - | - | Reserved |
## <span id="page-67-0"></span>**8.6.10. APB peripheral reset register 1 (RCC\_APBRSTR1)**
#### **Address offset:**0x2C
#### **Reset value:**0x0000 0000
| 31 | 30 | 29 | 28 | 27 | 26 | 25 | 24 | 23 | 22 | 21 | 20 | 19 | 18 | 17 | 16 |
|--------------|-----|-----|------------|------------|-----|-----|-----|-----|-----|------------|-----|-----|-----|-----|-----|
| LPTIM<br>RST | Res | Res | PWR<br>RST | DBG<br>RST | Res | Res | Res | Res | Res | I2C<br>RST | Res | Res | Res | Res | Res |
| RW | | | RW | RW | | | | | | RW | | | | | |
| 15 | 14 | 13 | 12 | 11 | 10 | 9 | 8 | 7 | 6 | 5 | 4 | 3 | 2 | 1 | 0 |
| Res | Res | Res | Res | Res | Res | Res | Res | Res | Res | Res | Res | Res | Res | Res | Res |
| | | | | | | | | | | | | | | | |
| Bit | Name | R/W | Reset Value | Function |
|-------|----------|-----|-------------|-------------------------------|
| | | | | LP Timer module reset. |
| 31 | LPTIMRST | RW | 0 | 0: no effect, |
| | | | | 1: The module is reset, |
| 30:29 | Reserved | - | - | Reserved |
| | | | | Power interface module reset. |
| 28 | PWRRST | RW | 0 | 0: no effect, |
| | | | | 1: The module is reset, |
| | | | | MCU Debug module reset. |
| 27 | DBGRST | RW | 0 | 0: no effect, |
| | | | | 1: The module is reset, |
| 26:22 | Reserved | - | - | Reserved |
| | | | | I2C1 module reset. |
| 21 | I2CRST | RW | 0 | 0: no effect, |
| | | | | 1: The module is reset, |
| 20:0 | Reserved | - | - | Reserved |
## <span id="page-67-1"></span>**8.6.11. APB peripheral reset register 2 (RCC\_APBRSTR2)**
#### **Address offset:**0x30
| 31 | 30 | 29 | 28 | 27 | 26 | 25 | 24 | 23 | 22 | 21 | 20 | 19 | 18 | 17 | 16 |
|------------------|-------------------|---------|-----------------|-----------------|---------|---------|---------|---------|------------------|------------------|----------------|---------|---------|---------|-----------------------|
| Res | Res | Re<br>s | Res | Res | Re<br>s | Re<br>s | Re<br>s | Re<br>s | COMP<br>2<br>RST | COMP<br>1<br>RST | AD<br>C<br>RST | Re<br>s | Re<br>s | Re<br>s | Res |
| | | | | | | | | | RW | RW | RW | | | | |
| 15 | 14 | 13 | 12 | 11 | 10 | 9 | 8 | 7 | 6 | 5 | 4 | 3 | 2 | 1 | 0 |
| TIM1<br>4<br>RST | USART<br>1<br>RST | Re<br>s | SPI<br>1<br>RST | TIM<br>1<br>RST | Re<br>s | Re<br>s | Re<br>s | Re<br>s | Res | Res | Res | Re<br>s | Re<br>s | Re<br>s | SYS<br>CF<br>G<br>RST |
| RW | RW | | RW | RW | | | | | | | | | | | RW |
| Bit | Name | R/W | Reset Value | Function |
|-------|----------|-----|-------------|------------------------|
| 31:23 | Reserved | - | - | Reserved |
| | | | | COMP2 module reset。 |
| 22 | COMP2RST | RW | 0 | 0:no effect; |
| | | | | 1:The module is reset; |
| | | | | COMP1 module reset。 |
| 21 | COMP1RST | RW | 0 | 0:no effect; |
| | | | | 1:The module is reset; |
| 20 | ADCRST | RW | 0 | ADC module reset。 |
| Bit | Name | R/W | Reset Value | Function |
|-------|-----------|-----|-------------|------------------------|
| | | | | 0:no effect; |
| | | | | 1:The module is reset; |
| 19:16 | Reserved | - | - | Reserved |
| | | | | TIM14 module reset。 |
| 15 | TIM14RST | RW | 0 | 0:no effect; |
| | | | | 1:The module is reset; |
| | | | | USART1 module reset。 |
| 14 | USART1RST | RW | 0 | 0:no effect; |
| | | | | 1:The module is reset; |
| 13 | Reserved | - | - | Reserved |
| | | RW | | SPI1 module reset。 |
| 12 | SPI1RST | | 0 | 0:no effect; |
| | | | | 1:The module is reset; |
| | | | | TIM1 module reset。 |
| 11 | TIM1RST | RW | 0 | 0:no effect; |
| | | | | 1:The module is reset; |
| 10:1 | Reserved | - | - | Reserved |
| | | | | SYSCFG module reset。 |
| 0 | SYSCFGRST | RWs | 0 | 0:no effect; |
| | | | | 1:The module is reset; |
## <span id="page-68-0"></span>**8.6.12. I/O interface clock enable register (RCC\_IOPENR)**
#### **Address offset:**0x34
#### **Reset value:**0x0000 0000
| 31 | 30 | 29 | 28 | 27 | 26 | 25 | 24 | 23 | 22 | 21 | 20 | 19 | 18 | 17 | 16 | | |
|-----|-----|-----|-----|-----|-----|-----|-----|-----|-----|-----|-----|-----|-----|-----|-------|-------|-------|
| Res | Res | Res | Res | Res | Res | Res | Res | Res | Res | Res | Res | Res | Res | Res | Res | | |
| | | | | | | | | | | | | | | | | | |
| 15 | 14 | 13 | 12 | 11 | 10 | 9 | 8 | 7 | 6 | 5 | 4 | 3 | 2 | 1 | 0 | | |
| | | | | | | | | | | | | | | | GPIOC | GPIOB | GPIOA |
| Res | Res | Res | Res | Res | Res | Res | Res | Res | Res | Res | Res | Res | EN | EN | EN | | |
| | | | | | | | | | | | | | RW | RW | RW | | |
| Bit | Name | R/W | Reset Value | Function |
|------|----------|-----|-------------|-------------------------|
| 31:6 | Reserved | - | - | Reserved |
| | | | | I/O PortC clock enable. |
| 5 | GPIOCEN | RW | 0 | 0:Clock disabled; |
| | | | | 1:Clock enable |
| 4:2 | Reserved | - | - | Reserved |
| | | | | I/O PortB clock enable。 |
| 1 | GPIOBEN | RW | 0 | 0:Clock disabled; |
| | | | | 1:Clock enable |
| | | | | I/O PortA clock enable。 |
| 0 | GPIOAEN | RW | 0 | 0:Clock disabled; |
| | | | | 1:Clock enable |
## <span id="page-68-1"></span>**8.6.13. AHB peripheral clock enable register (RCC\_AHBENR)**
#### **Address offset:**0x38
| 31 | 30 | 29 | 28 | 27 | 26 | 25 | 24 | 23 | 22 | 21 | 20 | 19 | 18 | 17 | 16 |
|----|----|----|----|----|----|----|----|----|----|----|----|----|----|----|----|
| Res | Res | Res | Res | Res | Res | Res | Res | Res | Res | Res | Res | Res | Res | Res | Res |
|-----|-----|-----|-----------|-----|-----|------------|-------------|-----|-----|-----|-----|-----|-----|-----|-----|
| | | | | | | | | | | | | | | | |
| 15 | 14 | 13 | 12 | 11 | 10 | 9 | 8 | 7 | 6 | 5 | 4 | 3 | 2 | 1 | 0 |
| Res | Res | Res | CRC<br>EN | Res | Res | SRA<br>MEN | FLASH<br>EN | Res | Res | Res | Res | Res | Res | Res | Res |
| | | | RW | | | RW | RW | | | | | | | | |
| Bit | Name | R/W | Reset Value | Function |
|-------|----------|-----|-------------|--------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------|
| 31:13 | Reserved | - | - | Reserved |
| 12 | CRCEN | RW | 0 | CRC module clock enable<br>0:Disable |
| | | | | 1:Enable |
| 11:10 | Reserved | - | - | Reserved |
| 9 | SRAMEN | RW | 1 | In sleep mode, the clock enable control of SRAM<br>0: The module clock is disabled in sleep mode<br>1: The module clock is enabled in sleep mode<br>Note: This bit only affects the clock enable of this module in<br>sleep mode, in run mode, the clock of this module will not<br>be disabled |
| 8 | FLASHEN | RW | 1 | In sleep mode, the clock enable control of FLASH<br>0: The module clock is disabled in sleep mode<br>1: The module clock is enabled in sleep mode<br>Note: This bit only affects the clock enable of this module in<br>sleep mode, in run mode, the clock of this module will not<br>be disabled |
| 7:0 | Reserved | - | - | Reserved |
## <span id="page-69-0"></span>**8.6.14. APB peripheral clock enable register 1 (RCC\_APBENR1)**
#### **Address offset:**0x3C
#### **Reset value:**0x0000 0000
| 31 | 30 | 29 | 28 | 27 | 26 | 25 | 24 | 23 | 22 | 21 | 20 | 19 | 18 | 17 | 16 |
|-------------|--------|-----|-----------|-----------|-----|-----|-----|-----|-----|-----------|-----|-----|-----|-----|-----|
| LPTIM<br>EN | Res | Res | PWR<br>EN | DBG<br>EN | Res | Res | Res | Res | Res | I2C<br>EN | Res | Res | Res | Res | Res |
| RW | | | RW | RW | | | | | | RW | | | | | |
| 15 | 14 | 13 | 12 | 11 | 10 | 9 | 8 | 7 | 6 | 5 | 4 | 3 | 2 | 1 | 0 |
| Res | SPI2EN | Res | Res | Res | Res | Res | Res | Res | Res | Res | Res | Res | Res | Res | Res |
| | RW | | | | | | | | | | | | | | |
| Bit | Name | R/W | Reset Value | Function | | | | |
|-------|---------------|--------|-------------|---------------------------------------|--|--|--|--|
| | | | | LP Timer1 module clock enable. | | | | |
| 31 | LPTIMEN | RW | 0 | 0: Disable | | | | |
| | | | | 1: Enable | | | | |
| 30:29 | Reserved | - | - | Reserved | | | | |
| | | | | Low power control block clock enable. | | | | |
| 28 | PWREN | RW | 0 | 0: Disable | | | | |
| | | | | 1: Enable | | | | |
| | | | | Debug module clock enable. | | | | |
| 27 | DBGEN | RW | 0 | 0: Disable | | | | |
| | | | | 1: Enable | | | | |
| 26:22 | Reserved | -<br>- | | Reserved | | | | |
| | | | | I2C1 module clock enable. | | | | |
| 21 | I2CEN | RW | 0 | 0: Disable | | | | |
| | | | | 1: Enable | | | | |
| 20:15 | Reserved<br>- | | - | Reserved | | | | |
| | | | | SPI2 module clock enable. | | | | |
| 14 | SPI2EN | RW | 0 | 0: Disable | | | | |
| | | | | 1: Enable | | | | |
| 13:0 | Reserved | - | - | Reserved | | | | |
## <span id="page-69-1"></span>**8.6.15. APB peripheral clock enable register 2 (RCC\_APBENR2)**
**Address offset:**0x40
| 31 | 30 | 29 | 28 | 27 | 26 | 25 | 24 | 23 | 22 | 21 | 20 | 19 | 18 | 17 | 16 |
|-----------------|------------------|---------|----------------|----------------|---------|---------|---------|---------|-----------------|-----------------|---------------|---------|---------|---------|----------------------|
| Res | Res | Re<br>s | Res | Res | Re<br>s | Re<br>s | Re<br>s | Re<br>s | COMP<br>2<br>EN | COMP<br>1<br>EN | AD<br>C<br>EN | Re<br>s | Re<br>s | Re<br>s | Res |
| | | | | | | | | | RW | RW | RW | | | | |
| 15 | 14 | 13 | 12 | 11 | 10 | 9 | 8 | 7 | 6 | 5 | 4 | 3 | 2 | 1 | 0 |
| TIM1<br>4<br>EN | USART<br>1<br>EN | Re<br>s | SPI<br>1<br>EN | TIM<br>1<br>EN | Re<br>s | Re<br>s | Re<br>s | Re<br>s | Res | Res | Res | Re<br>s | Re<br>s | Re<br>s | SYS<br>CF<br>G<br>EN |
| RW | RW | | RW | RW | | | | | | | | | | | RW |
#### **Reset value:**0x0000 0000
| Bit | Name | R/W | Reset Value | Function |
|-------|----------|-----|-------------|-----------------------------|
| 31:23 | Reserved | - | - | Reserved |
| | | | | COMP2 module clock enable. |
| 22 | COMP2EN | RW | 0 | 0: Disable |
| | | | | 1: Enable |
| | | | | COMP1 module clock enable. |
| 21 | COMP1EN | RW | 0 | 0: Disable |
| | | | | 1: Enable |
| | | | | ADC module clock enable. |
| 20 | ADCEN | RW | 0 | 0: Disable |
| | | | | 1: Enable |
| 19:16 | Reserved | - | - | Reserved |
| | | | | TIM14 module clock enable. |
| 15 | TIM14EN | RW | 0 | 0: Disable |
| | | | | 1: Enable |
| | | | | USART1 module clock enable. |
| 14 | USART1EN | RW | 0 | 0: Disable |
| | | | | 1: Enable |
| 13 | Reserved | - | - | Reserved |
| | | | | SPI1 module clock enable. |
| 12 | SPI1EN | RW | 0 | 0: Disable |
| | | | | 1: Enable |
| | | | | TIM1 module clock enable. |
| 11 | TIM1EN | RW | 0 | 0: Disable |
| | | | | 1: Enable |
| 10:1 | Reserved | - | - | Reserved |
| | | | | SYSCFG module clock enable. |
| 0 | SYSCFGEN | RW | 0 | 0: Disable |
| | | | | 1: Enable |
## <span id="page-70-0"></span>**8.6.16. Peripheral independent clock configuration register (RCC\_CCIPR)**
#### **Address offset:**0x54
| 3<br>1 | 3<br>0 | 29 | 28 | 27 | 26 | 25 | 24 | 23 | 22 | 21 | 20 | 19 | 18 | 17 | 16 |
|--------|--------|-----|-----|------------------|----------------------|-----|-----|-----|-----|-----|-----|-----|--------------------|-----|-----|
| Res | | Res | Res | Res | Res | Res | Res | Res | Res | Res | Res | | LPTIM1SEL[1:0<br>] | Res | Res |
| | | | | | | | | | | | | RW | RW | | |
| 1<br>5 | 1<br>4 | 13 | 12 | 11 | 10 | 9 | 8 | 7 | 6 | 5 | 4 | 3 | 2 | 1 | 0 |
| Res | | Res | | COMP<br>2<br>SEL | CO<br>MP<br>1<br>SEL | Res | Res | Res | Res | Res | Res | Res | Res | Res | Res |
| | | | | RW | RW | | | | | | | | | | |
| Bit | Name | R/W | Reset Value | Function |
|-------|---------------|-----|-------------|----------------------------------------------------------------|
| 31:20 | Reserved | - | - | Reserved |
| 19:18 | LPTIMSEL[1:0] | RW | 2'b00 | LPTIM1 internal clock source selection.<br>00: PCLK<br>01: LSI |
| Bit | Name | R/W | Reset Value | Function |
|-------|----------|-----|-------------|----------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------|
| | | | | 10: No clock<br>11: LSE |
| 17:12 | Reserved | - | - | Reserved |
| 11 | COMP2SEL | RW | 0 | COMP2 module clock source selection.<br>0: PCLK<br>1: LSC (Clock selected by RCC_BDCR.LSCOSEL)<br>Note: Configure the selected LSC clock before enabling<br>FLTEN. |
| 10 | COMP1SEL | RW | 0 | COMP1 module clock source selection.<br>0: PCLK<br>1: LSC (Clock selected by RCC_BDCR.LSCOSEL)<br>Note:Configure this register to select the clock before<br>enabling COMP2_FR2.FLTEN. |
| 9:0 | Reserved | - | - | Reserved |
## <span id="page-71-0"></span>**8.6.17. RTC domain control register (RCC\_BDCR)**
#### **Address offset:**0x5C
**Reset value:**0x0000 0000,reset by POR/BOR
When PWR\_CR1.DBP is 1, it is allowed to write to this register.
| 31 | 30 | 29 | 28 | 27 | 26 | 25 | 24 | 23 | 22 | 21 | 20 | 19 | 18 | 17 | 16 |
|---------|---------|---------|---------|---------|---------|-----------------|----------------|---------|-------------|--------------|---------|---------|----------------|----------------|---------------|
| Re<br>s | Re<br>s | Re<br>s | Re<br>s | Re<br>s | Re<br>s | LSC<br>O<br>SEL | LSC<br>O<br>EN | Re<br>s | Res | Res | Re<br>s | Re<br>s | Res | Res | Res |
| | | | | | | RW | RW | | | | | | | | |
| 15 | 14 | 13 | 12 | 11 | 10 | 9 | 8 | 7 | 6 | 5 | 4 | 3 | 2 | 1 | 0 |
| Re<br>s | Re<br>s | Re<br>s | Re<br>s | Re<br>s | Re<br>s | Res | | Re<br>s | LSECSS<br>D | LSECS<br>SON | Res | | LSE<br>BY<br>P | LSE<br>RD<br>Y | LS<br>E<br>ON |
| | | | | | | | | | RW | RW | | | RW | R | RW |
| Bit | Name | R/W | Reset Value | Function | | | | | |
|-------|----------|-----|-------------|-----------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------|--|--|--|--|--|
| 31:26 | Reserved | - | - | Reserved | | | | | |
| 25 | LSCOSEL | RW | 0 | Low-speed clock selection.<br>0: LSI<br>1: LSE | | | | | |
| 24 | LSCOEN | RW | 0 | Low-speed clock enable.<br>0: Disable<br>1: Enable | | | | | |
| 23:7 | Reserved | - | - | Reserved | | | | | |
| 6 | LSECSSD | R | 0 | LSE CSS (clock security system) detection failed.<br>This bit is set by hardware to indicate that CSS detects<br>32.768 kHz OSC (LSE) failed.<br>0: No LSE detected failure<br>1: Failed to detect ISE | | | | | |
| 5 | LSECSSON | RW | 0 | LSE CSS 使能<br>0:禁止<br>1:使能<br>必须 LSEON=1 并且 LSERDY=1 后才能使能<br>LSECSSON。<br>一旦使能该位,不能再把该位禁止,除非 LSECSSD=1。 | | | | | |
| 4:3 | Reserved | - | - | - | | | | | |
| 2 | LSEBYP | RW | 0 | LSE OSC bypass<br>0: Not bypassed, the low-speed external clock selects the<br>crystal oscillator<br>1: Bypassed, the low-speed external clock selects the ex<br>ternal interface input clock<br>Note: This bit can only be written when the external 32.768<br>kHz OSC is disabled (LSEON = 0 and LSERDY = 0). | | | | | |
| 1 | LSERDY | R | 0 | LSE OSC ready bit.<br>Set by hardware, cleared by hardware, indicating when<br>LSE is stable | | | | | |
| Bit | Name | R/W | Reset Value | Function |
|-----|-------|-----|-------------|---------------------------------------------|
| | | | | 0: Not ready |
| | | | | 1: Ready |
| 0 | LSEON | RW | 0 | LSE OSC enabled.<br>0: Disable<br>1: Enable |
## <span id="page-72-0"></span>**8.6.18. Control/status register (RCC\_CSR)**
#### **Address offset:**0x60
#### **Reset value:**0x0000 0000
Reset sources: 1) [30:25]: POR reset, 2) LSION: system reset, 3) NRST\_FLTIDS will not be reset
| | | by system | | | | | | | | | | | | | |
|---------|---------|----------------------|-----------------|---------------------|-----------------|-----------------|-------------------|-----|---------|---------|---------|---------|---------|----------------|-----------|
| 31 | 30 | 29 | 28 | 27 | 26 | 25 | 24 | 23 | 22 | 21 | 20 | 19 | 18 | 17 | 16 |
| Re<br>s | Re<br>s | IWD<br>G<br>RST<br>F | SFT<br>RST<br>F | PW<br>R<br>RST<br>F | PIN<br>RST<br>F | OBL<br>RST<br>F | Res | | Re<br>s | Re<br>s | Re<br>s | Re<br>s | Re<br>s | Res | Res |
| | | R | R | R | R | R | | RW | | | | | | | |
| 15 | 14 | 13 | 12 | 11 | 10 | 9 | 8 | 7 | 6 | 5 | 4 | 3 | 2 | 1 | 0 |
| Re<br>s | Re<br>s | Res | Res | Res | Res | Res | PINRST_FL<br>TDIS | Res | Re<br>s | Re<br>s | Re<br>s | Re<br>s | Re<br>s | LSI<br>RD<br>Y | LSIO<br>N |
| | | | | | | | RW | | | | | | | R | RW |
| Bit | Name | R/W | Reset Value | Function |
|-----|---------------|---------|-------------|--------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------|
| 31 | Reserved | | | |
| 29 | IWDGRSTF | R | 0 | IWDG reset flag.<br>Setting RMVF to 1 clears this bit. |
| 28 | SFTRSTF | R | 0 | Soft reset flag.<br>Setting RMVF to 1 clears this bit. |
| 27 | PWRRSTF | R | 0 | BOR/POR/PDR reset flag.<br>Setting RMVF to 1 clears this bit. |
| 26 | PINRSTF | R | 0 | External NRST pin reset flag.<br>Setting RMVF to 1 clears this bit. |
| 25 | OBLRSTF | R | 0 | Option byte loader reset flag.<br>Setting RMVF to 1 clears this bit. |
| 24 | Reserved | | | - |
| 23 | RMVF | RW | 0 | Reset flags [30:25] need to be cleared by setting software<br>to 1. |
| 8 | PINRST_FLTDIS | RW<br>0 | | NRST filter disabled<br>0: HSI_10M is enabled, and the filter 20 us width function is<br>enabled<br>1: The filtering function is disabled, and HSI_10M remains<br>off |
| 7:2 | Reserved | - | - | Reserved |
| 1 | LSIRDY | R | 0 | LSI OSC stable flag.<br>0: LSI is not stable<br>1: LSI has stabilized |
| 0 | LSION | RW | 0 | LSI OSC enabled.<br>0: Disable<br>1: Enable<br>Set by software, cleared by software. This bit is set by<br>hardware when IWDG is enabled by hardware (via option<br>byte) and LSECSS is enabled by software. |
## <span id="page-72-1"></span>**8.6.19. RCC register address map**
| Of<br>fs<br>et | Reg<br>ister | 31 | 30 | 29 | 28 | 27 | 26 | 25 | 24 | 23 | 22 | 21 | 20 | 19 | 18 | 17 | 16 | 15 | 14 | 13 | 12 | 11 | 10 | 9 | 8 | 7 | 6 | 5 | 4 | 3 | 2 | 1 | 0 |
|----------------|--------------|------|------|------|------|------|------|------|------|------|------|------|------|------|-------|------|------|------|------|----|-----------------|----|--------|------|-------|------|------|------|------|------|------|------|------|
| 0x<br>00 | RCC_<br>CR | Res. | Res. | Res. | Res. | Res. | Res. | Res. | Res. | Res. | Res. | Res. | Res. | Res. | HSEON | Res. | Res. | Res. | Res. | | HSIDIV<br>[2:0] | | HSIRDY | Res. | HSION | Res. | Res. | Res. | Res. | Res. | Res. | Res. | Res. |
| 74<br>/302 |
|------------|
| Of<br>fs<br>et | Reg<br>ister | 31 | 30 | 29 | 28 | 27 | 26 | 25 | 24 | 23 | 22 | 21 | 20 | 19 | 18 | 17 | 16 | 15 | 14 | 13 | 12 | 11 | 10 | 9 | 8 | 7 | 6 | 5 | 4 | 3 | 2 | 1 | 0 |
|----------------|------------------------------|----------|------|-----------------|--------|------------------|------|-----------------|------|------|----------|---------------|--------|------|------|-----------------|------|----------|-------------|---------------|---------|---------|-----------|---------|---------|----------------|------|------|----------|---------------|----------|----------|-----------|
| | Reset<br>value | | | | | | | | | | | | | | 0 | | | | | 0 | 0 | 0 | 0 | 0 | 1 | | | | | | | | |
| 0x<br>04 | RCC_<br>ICSCR | Res. | Res. | Res. | Res. | LSI_STARTUP[1:0] | | Res. | | | | LSI_TRIM[8:0] | | | | | | | HSI_FS[2:0] | | | | | | | HSI_TRIM[12:0] | | | | | | | |
| | Reset<br>value | | | | | 0 | 0 | | 0 | 1 | 1 | 1 | 1 | 1 | 1 | 1 | 1 | 0 | 0 | 0 | 1 | 0 | 0 | 0 | 0 | 1 | 1 | 1 | 1 | 1 | 1 | 1 | 1 |
| 0x | RCC_<br>CFGR | Res. | | MCO<br>PRE[2:0] | | Res. | | MCO<br>SEL[2:0] | | Res. | Res. | Res. | Res. | Res. | Res. | Res. | Res. | Res. | | PPRE<br>[2:0] | | | HPRE[3:0] | | | Res. | Res. | | SWS[2:0] | | | SW[2:0] | |
| 08 | Reset<br>value | | 0 | 0 | 0 | | 0 | 0 | 0 | | | | | | | | | | 0 | 0 | 0 | 0 | 0 | 0 | 0 | | | 0 | 0 | 0 | 0 | 0 | 0 |
| 0x<br>10 | RCC_<br>ECSC<br>R | Res. | Res. | Res. | Res. | Res. | Res. | Res. | Res. | Res. | Res. | Res. | Res. | Res. | Res. | LSE_DRIVER[1:0] | | Res. | Res. | Res. | Res. | Res. | Res. | Res. | Res. | Res. | Res. | Res. | Res. | HSE_FREQ[1:0] | | Res. | Res. |
| | Reset<br>value | | | | | | | | | | | | | | | 1 | 0 | | | | | | | | | | | | | 0 | 0 | | |
| 0x<br>14 | Re<br>serve<br>d | Res. | Res. | Res. | Res. | Res. | Res. | Res. | Res. | Res. | Res. | Res. | Res. | Res. | Res. | Res. | Res. | Res. | Res. | Res. | Res. | Res. | Res. | Res. | Res. | Res. | Res. | Res. | Res. | Res. | Res. | Res. | Res. |
| 0x<br>18 | RCC_<br>CIER | Res. | Res. | Res. | Res. | Res. | Res. | Res. | Res. | Res. | Res. | Res. | Res. | Res. | Res. | Res. | Res. | Res. | Res. | Res. | Res. | Res. | Res. | Res. | Res. | Res. | Res. | Res. | Res. | HSIRDYIE | Res. | LSERDYIE | LSIRDYIE |
| | Reset<br>value | | | | | | | | | | | | | | | | | | | | | | | | | | | | | 0 | | 0 | 0 |
| 0x1 | RCC_<br>CIFR | Res. | Res. | Res. | Res. | Res. | Res. | Res. | Res. | Res. | Res. | Res. | Res. | Res. | Res. | Res. | Res. | Res. | Res. | Res. | Res. | Res. | Res. | LSECSSF | Res. | Res. | Res. | Res. | Res. | HSIRDYIF | Res. | LSERDYIF | LSIRDYIF |
| C | Reset | | | | | | | | | | | | | | | | | | | | | | | 0 | | | | | | 0 | | 0 | 0 |
| | value<br>RCC_ | Res. | Res. | Res. | Res. | Res. | Res. | Res. | Res. | Res. | Res. | Res. | Res. | Res. | Res. | Res. | Res. | Res. | Res. | Res. | Res. | Res. | Res. | LSECSSC | Res. | Res. | Res. | Res. | Res. | HSIRDYIC | Res. | LSERDYIC | LSIRDYIC |
| 0x<br>20 | CICR<br>Reset | | | | | | | | | | | | | | | | | | | | | | | 0 | | | | | | 0 | | 0 | 0 |
| 0x<br>24 | value<br>RCC_<br>IOPR<br>STR | Res. | Res. | Res. | Res. | Res. | Res. | Res. | Res. | Res. | Res. | Res. | Res. | Res. | Res. | Res. | Res. | Res. | Res. | Res. | Res. | Res. | Res. | Res. | Res. | Res. | Res. | Res. | Res. | Res. | GPIOCRST | GPIOBRST | GPIOARST |
| | Reset<br>value | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | 0 | 0 | 0 |
| 0x<br>28 | RCC_<br>AHBR<br>STR | Res. | Res. | Res. | Res. | Res. | Res. | Res. | Res. | Res. | Res. | Res. | Res. | Res. | Res. | Res. | Res. | Res. | Res. | Res. | CRCRST | Res. | Res. | Res. | Res. | Res. | Res. | Res. | Res. | Res. | Res. | Res. | Res. |
| | Reset<br>value | | | | | | | | | | | | | | | | | | | | 0 | | | | | | | | | | | | |
| 0x2<br>C | RCC_<br>AP<br>BRST<br>R1 | LPTIMRST | Res. | Res. | PWRRST | DBGRST | Res. | Res. | Res. | Res. | Res. | I2CRST | Res. | Res. | Res. | Res. | Res. | Res. | SPI2RST | Res. | Res. | Res. | Res. | Res. | Res. | Res. | Res. | Res. | RST | Res. | Res. | Res. | Res. |
| | Reset<br>value | | | | 0 | 0 | | | | | | 0 | | | | | | | 0 | | | | | | | | | | 0 | | | 0 | |
| 0x<br>30 | RCC_<br>AP<br>BRST<br>R2 | Res. | Res. | Res. | Res. | Res. | Res. | Res. | Res. | Res. | COMP2RST | COMP1RST | ADCRST | Res. | Res. | Res. | Res. | TIM14RST | USART1RST | Res. | SPI1RST | TIM1RST | Res. | Res. | Res. | Res. | Res. | Res. | Res. | Res. | Res. | Res. | SYSCFGRST |
| | Reset<br>value | | | | | | | | | | 0 | 0 | | | | | | 0 | 0 | | 0 | 0 | | | | | | | | | | | 0 |
| 0x<br>34 | RCC_<br>IOPE<br>NR | Res. | Res. | Res. | Res. | Res. | Res. | Res. | Res. | Res. | Res. | Res. | Res. | Res. | Res. | Res. | Res. | Res. | Res. | Res. | Res. | Res. | Res. | Res. | Res. | Res. | Res. | Res. | Res. | Res. | GPIOCEN | GPIOBEN | GPIOAEN |
| | Reset<br>value | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | 0 | 0 | 0 |
| 0x<br>38 | RCC_<br>AHBE<br>NR | Res. | Res. | Res. | Res. | Res. | Res. | Res. | Res. | Res. | Res. | Res. | Res. | Res. | Res. | Res. | Res. | Res. | Res. | Res. | CRCEN | Res. | Res. | SRAMEN | FLASHEN | Res. | Res. | Res. | Res. | Res. | Res. | Res. | Res. |
| PY32F002B | Reference | Manual |
|-----------|-----------|--------|
|-----------|-----------|--------|
| 0x<br>5<br>C<br>0x<br>60 | | 0x<br>58 | 0x<br>54 | 0x<br>44<br>-<br>0x<br>50 | | 0x<br>40 | | 0x<br>3<br>C | | Of<br>fs<br>et |
|-------------------------------------------------------------------------------------|--|----------|-------------------|---------------------------|----------------|-------------------------|----------------|-------------------------|----------------|----------------|
| Reset<br>value<br>Re<br>serve<br>d<br>RCC_<br>BDCR<br>Reset<br>value<br>RCC_<br>CSR | | | RCC_<br>CCIP<br>R | Re<br>serve<br>d | Reset<br>value | RCC_<br>AP<br>BENR<br>2 | Reset<br>value | RCC_<br>AP<br>BENR<br>1 | Reset<br>value | Reg<br>ister |
| Res.<br>Res.<br>Res. | | | Res. | Res. | | Res. | 0 | LPTIMEN | | 31 |
| Res.<br>Res.<br>Res. | | | Res. | Res. | | Res. | | Res. | | 30 |
| Res.<br>Res.<br>IWDGRSTF | | | Res. | Res. | | Res. | | Res. | | 29 |
| Res.<br>Res.<br>SFTRSTF | | | Res. | Res. | | Res. | 0 | PWREN | | 28 |
| Res.<br>Res.<br>PWRRSTF | | | Res. | Res. | | Res. | 0 | DBGEN | | 27 |
| Res.<br>Res.<br>PINRSTF | | | Res. | Res. | | Res. | | Res. | | 26 |
| Res.<br>LSCOSEL<br>0<br>OBLRSTF | | | Res. | Res. | | Res. | | Res. | | 25 |
| Res.<br>LSCOEN<br>0<br>Res. | | | Res. | Res. | | Res. | | Res. | | 24 |
| Res.<br>Res.<br>RMVF | | | Res. | Res. | | Res. | | Res. | | 23 |
| Res.<br>Res.<br>Res. | | | Res. | Res. | 0 | COMP2EN | | Res. | | 22 |
| Res.<br>Res.<br>Res. | | | Res. | Res. | 0 | COMP1EN | 0 | I2CEN | | 21 |
| Res.<br>Res.<br>Res. | | | Res. | Res. | 0 | ADCEN | | Res. | | 20 |
| 0<br>Res.<br>Res.<br>Res. | | | LPTIMSEL[1:0] | Res. | | Res. | | Res. | | 19 |
| 0<br>Res.<br>Res.<br>Res. | | | | Res. | | Res. | | Res. | | 18 |
| Res.<br>Res.<br>Res. | | | Res. | Res. | | Res. | | Res. | | 17 |
| Res.<br>BDRST<br>0<br>Res. | | | Res. | Res. | | Res. | | Res. | | 16 |
| Res.<br>Res.<br>Res. | | | Res. | Res. | 0 | TIM14EN | | Res. | | 15 |
| Res.<br>Res.<br>Res. | | | Res. | Res. | 0 | USART1EN | 0 | SPI2EN | | 14 |
| Res.<br>Res.<br>Res. | | | Res. | Res. | | Res. | | Res. | | 13 |
| Res.<br>Res.<br>Res. | | | Res. | Res. | 0 | SPI1EN | | Res. | 0 | 12 |
| 0<br>Res.<br>Res.<br>Res. | | | COMP2SEL | Res. | 0 | TIM1EN | | Res. | | 11 |
| 0<br>Res.<br>Res.<br>Res. | | | COMP1SEL | Res. | | Res. | | Res. | | 10 |
| Res.<br>Res.<br>Res. | | | Res. | Res. | | Res. | | Res. | 1 | 9 |
| Res.<br>NRST_FLTDIS | | | Res. | Res. | | Res. | | Res. | 1 | 8 |
| Res.<br>Res.<br>Res. | | | Res. | Res. | | Res. | | Res. | | 7 |
| Res.<br>LSECSSD<br>0<br>Res. | | | Res. | Res. | | Res. | | Res. | | 6 |
| Res.<br>LSECSSON<br>0<br>Res. | | | Res. | Res. | | Res. | | Res. | | 5 |
| Res.<br>Res.<br>Res. | | | Res. | Res. | | Res. | | Res. | | 4 |
| Res.<br>Res.<br>Res. | | | Res. | Res. | | Res. | | Res. | | 3 |
| Res.<br>LSEBYP<br>0<br>Res. | | | Res. | Res. | | Res. | | Res. | | 2 |
| Res.<br>LSERDY<br>0<br>LSIRDY | | | Res. | Res. | | Res. | | Res. | | 1 |
| Res.<br>LSEON<br>0<br>LSION | | | Res. | Res. | 0 | SYSCFGEN | | Res. | | 0 |
# <span id="page-75-0"></span>**9. General-purpose I/Os (GPIO)**
## <span id="page-75-1"></span>**9.1. GPIO introduction**
Each GPIO port has:
- Four 32-bit configuration registers (GPIOx\_MODER, GPIOx\_OTYPER, GPIOx\_OSPEEDR, GPIOx\_PUPDR)
- Two 32-bit data registers (GPIOx\_IDR and GPIOx\_ODR)
- One 32-bit set/reset register (GPIOx\_BSRR)
- One 32-bit lock register (GPIOx\_LCKR)
- One alternate function selection register (GPIOx\_AFRL).
## <span id="page-75-2"></span>**9.2. GPIO main features**
- Output status: push-pull or open drain + pull-up/down
- Output data from output data register (GPIOx\_ODR) or peripheral (alternate function output)
- Speed selection for each I/O
- Input states:floating,pull-up/down,analog
- Input data to input data register (GPIOx\_IDR) or peripheral (alternate function input)
- Bit set and reset register (GPIOx\_ BSRR) for bitwise write access to GPIOx\_ODR
- Locking mechanism (GPIOx\_LCKR) provided to freeze the I/O port configurations
- Analog function
- Alternate function selection registers(at most 8 alternate functions per I/O port)
- Fast toggle capable of changing every single cycle
- Highly flexible pin multiplexing allows the use of I/O pins as GPIOs or as one of several peripheral function
## <span id="page-75-3"></span>**9.3. GPIO functional description**
Each port bit of the GPIO ports can be individually configured by software in several modes:
- ─ Input floating
- ─ Input pull-up
- ─ Input pull-down
- ─ Analog input
- ─ Output open-drain with pull-up or pull-down capability
- ─ Output puss-pull with pull-up or pull -down capability
- ─ Alternate function push-pull with pull-up or pull–down capability
- ─ Alternate function open-drain with pull-up or pull-down capability
Each I/O port bit is freely programmable, however the I/O port registers have to be accessed as 32 bit words,half-words or bytes. The purpose of the GPIOx\_BSRR and GPIOx\_BRR registers is to allow read/modify Independent accesses to any of the GPIOx\_ODR registers. In this way, there is no risk of an IRQ occurring between read and modify access.
The figure of an I/O port(1 bit) basic structure as follows:
![](_page_76_Figure_1.jpeg)
Figure 9-1 IO Basic structure of an I/O port bit
## <span id="page-76-0"></span>**9.3.1. General-purpose I/O (GPIO)**
During and after reset, the alternate functions are not active and most of the IOs are configured in analog mode.
The debug pins are in alternate function pull-up or pull-down after reset:
─PA2-SWCLK:in pull-down mode
─PB6-SWDIO:in pull-up mode
When the pin is configured as output, the value written to the output data register (GPIOx\_ODR) is output on the I/O pin. It is possible to use the output drive in push-pull mode or open-drain mode (only the low level is driven, high level is HI-Z).
The input data register (GPIOx\_IDR) captures the data present on the I/O pin at every AHB clock cycle.
All GPIO pins have weak internal pull-up and pull-down resistors, which can be activated or not depending on the value in the GPIOx\_PUPDR register.
## <span id="page-76-1"></span>**9.3.2. I/O pin alternate function multiplexer and mapping**
The device I/O pins are connected to on-board peripherals/modules through a multiplexer that allows only one peripheral alternate function (AF) connected to an I/O pin at a time. In this way, there can be no conflict between peripherals available on the same I/O pin.
Each I/O pin has a multiplexer with up to eight alternate function inputs (AF0 to AF7) that can be configured through the GPIOx\_AFRL (for pin 0 to 7) registers:
- After reset the multiplexer selection is alternate function 0 (AF0). The I/Os are configured in alternate function mode through GPIOx\_MODER register.
- The specific alternate function assignments for each pin are detailed in the device datasheet.
In addition to this flexible I/O multiplexing architecture, each peripheral has alternate functions mapped onto different I/O pins to optimize the number of peripherals available in smaller packages. The user configures IO as follows:
- Debug function: After each reset, these pins are assigned as alternate function pins immediately usable by the debugger host.
- GPIO: Configure the corresponding I/O port as output, input or analog mode in GPIOx\_MODER register
- Peripheral multiplexing function:
- The I/O corresponding to the register GPIOx\_AFRL configuration is the alternate function x (x = 0…7).
- Registers GPIOx\_OTYPER, GPIOx\_PUPDR and GPIOX\_OSPEEDER configure the type, pullup/pull-down and output speed respectively.
- Configure the corresponding I/O as an alternate function in the GPIOx\_MODER register.
- Additional functions:
- ADC and COMP functions are enabled in the registers of the ADC and COMP modules, in every I/O configuration. When the I/O is used as ADC or COMP, it is recommended to configure the port as analog mode through the register GPIOx\_MODER.
- For additional functions of the crystal oscillator, configure the respective functions in the corresponding PWR and RCC module registers. These configurations have higher priority than standard GPIO configurations.
## <span id="page-77-0"></span>**9.3.3. I/O port control registers**
Each of the GPIO ports has four 32-bit memory-mapped control registers (GPIOx\_MODER, GPIOx\_OTYPER, GPIOx\_OSPEEDR and GPIOx\_PUPDR) to configure up to 16 I/Os. The register GPIOx\_MODER is used to select the I/O mode (input, output, AF, analog). The GPIOx\_OTYPER and GPIOx\_OSPEEDR registers are used to select the output type (push-pull or open-drain) and speed. The GPIOx\_PUPDR register is used to select the pull-up/pull-down whateverr the I/O direction.
#### <span id="page-77-1"></span>**9.3.4. I/O port data registers**
Each GPIO has two 16-bit memory-mapped data registers: input and output data registers (GPIOx\_IDR and GPIOx\_ODR). GPIOx\_ODR stores the data to be output, it is read/written accessible. The data input through the I/O are stored into the input data register (GPIOx\_IDR), a readonly register.
#### <span id="page-77-2"></span>**9.3.5. I/O data bitwise handling**
The bit set reset register (GPIOx\_BSRR) is a 32-bit register that allows the application to set and reset each individual bits in the output data register (GPIOx\_ODR). The bit set reset register has twice the size of GPIOx\_ODR.
To each bit in GPIOx\_ODR, correspond two control bits of GPIOx\_BSRR: BS(i) and BR(i). When written bit BS(i) to 1 can set the corresponding bit of GPIOx\_ODR to 1, and setting bit BR(i) to 1 can clear the corresponding bit of GPIOx\_ODR to 0.
Write any bit to 0 in GPIOx\_BSRR does not have any effect on the corresponding bit in GPIOx\_ODR. If there is an attempt to both set and reset a bit in GPIOx\_BSRR, the set operation has priority. Using the GPIOx\_BSRR register to change the values of individual bit in GPIOx\_ODR is a "oneshot" effect that does not lock the GPIOx\_ODR bits. The GPIOx\_ODR bits can always be accessed directly. The GPIOx\_BSRR register provides a way of performing atomic bitwise handling. There is no need for the software to disable interrupts when programming the GPIOx\_ODR at bit level: it is possible to modify one or more bits in a sinle atomic AHB write access.
#### <span id="page-78-0"></span>**9.3.6. GPIO locking mechanism**
It is possible to freeze the IO control with GPIOx\_LCKR registers through a series of special write timings, including GPIOx\_MODER, GPIOx\_OTYPER, GPIOx\_OSPEEDR, GPIOx\_PUPDR, and GPIOx\_AFRL.
A special write/read sequence can manipulate the register GPIOx\_LCKR. When the right lock sequence is applied to bit 16 in this register, the value of LCKR[15:0] can LOCK the I/O (during the write sequence, the value of LCKR[15:0] remains unchanged). When the LOCK sequence has been applied to a port bit, the value of the port bit cannot be modify until the next MCU reset or peripheral reset. Each GPIOx\_LCKR bit freezes the corresponding bit in the control registers (GPIOx\_MODER, GPIOx\_OTYPER, GPIOx\_OSPEEDR, GPIOx\_PUPDR and GPIOx\_AFRL).
The GPIOx\_LCKR register with a word (32 bits) because the [15:0] bits are also set when the GPIOx\_LCKR bit 16 is set.
#### <span id="page-78-1"></span>**9.3.7. I/O alternate function input/output**
Two registers are provided to select one of the alternate function input/outputs available for each I/O. The user can connect an alternate function to the IO port according as required by the application.
This means that a number of possible peripheral functions are multiplexed on each GPIO using the GPIOx\_AFRL alternate function registers. The application can thus select any one of the possible functions for each I/O. The AF selection signal being common to the alternate function input and alternate function output, a single channel is selected for the alternate function input/output of a given I/O.
#### <span id="page-78-2"></span>**9.3.8. External interrupt/wakeup lines**
All ports have external interrupt capability. To use the external interrupt lines, the given pin must be disabled in analog mode or as oscillator pin, so the input trigger is kepy enabled.
#### <span id="page-78-3"></span>**9.3.9. I/O input configuration**
When the I/O port is configured as input:
- The output buffer is disabled.
- The Schmitt trigger input is enable.
- The pull-up and pull-down resistors can be enabled/disabled according to the configuration of the GPIOx\_PUPDR register.
- The data present on the I/O pins are sampled into the input data register on every AHB clock
#### cycle.
A read access to the input data register provides the I/O status.
![](_page_79_Figure_3.jpeg)
Figure 9-2 input floating/pull up/pull down configurations
## <span id="page-79-0"></span>**9.3.10. I/O output configuration**
When the I/O port is configured as output:
- The output buffer is enabled:
- Open-drain mode: A '0' in the output register activates the N-MOS whereas a '1' in the output registe leaves the port in a high-impedance state (the PMOS is never activated).
- Push-pull mode: A '0' in the output register activates the N-MOS whereas a '1' in the output register activates the P-MOS.
- The Schmitt trigger input is activated
- The pull-up and pull-down resistors can be enabled/disabled according to the configuration of the GPIOx\_PUPDR register
- The data present on the I/O pins are sampled into the input data register every AHB clock cycle
- A read access to the input data register gets the I/O state
- A read access to the output data register gets the value of the last write
![](_page_80_Figure_1.jpeg)
Figure 9-3 Output configuration
## <span id="page-80-0"></span>**9.3.11. Alternate function configuration**
When an I/O port is configured as alternate function:
- In an open-drain or push-pull configuration, the output buffer is turned on.
- Built-in peripheral signal-driven output buffer (multiplexed function output).
- The Schmitt trigger input is activated.
- The pull-up and pull-down resistors can be enabled/disabled according to the configuration of the GPIOx\_PUPDR register.
- The data present on the I/O pins are sampled into the input data register every AHB clock cycle.
- A read access to the input data register gets the I/O state.
![](_page_81_Figure_1.jpeg)
Figure 9-4 Alternate function configuration
## <span id="page-81-0"></span>**9.3.12. Analog configuration**
When an I/O port is configured as analog configuration:
- The output buffer is disabled.
- The Schmitt trigger input is deactivated, providing zero consumption for every analog value of the I/O pin. The output of Schmitt trigger is forced to '0'.
- The weak pull-up and pull-down resistors are disabled (Requires software to set GPIOx\_PUPDR to 00).
- Read access to the input data register gets the value is '0.
![](_page_81_Figure_9.jpeg)
Figure 9-5 High impedance-analog configuration
## <span id="page-82-0"></span>**9.3.13. Use the LSE oscillator pins as GPIOs**
When the LSE oscillator is switch off (default state after reset), the related oscillator pins can be used as normal GPIOs.
When the LSE oscillator is switch on (by setting the LSEON bit in the RCC\_CSR register) the corresponding port needs to be configured as an analog port by software.
When the crystal oscillator is configured in a user external clock mode, only the pin is reserved for clock input and the OSC\_IN or OSC32\_IN pin can still be used as normal GPIO.
## <span id="page-82-1"></span>**9.4. GPIO registers**
The GPIO related registers can be written in word, half word and byte mode.
## <span id="page-82-2"></span>**9.4.1. GPIO port mode register (GPIOx\_MODER) (x = A, B, C)**
#### **Address offset:** 0x00
#### **Reset value:**
- 0x0000 FFEF for GPIOA
- GPIOB reset value
- a) Flash option byte configured with SWD:0x0000 FFFF
- b) Flash option byte not configured with SWD:0x0000 EFFF
- GPIOC reset value
- a) Flash option byte not configured with SWD :0x0000 000F
- b) Flash option byte configured with SWD:0x0000 000E
| 31 | 30 | 29 | 28 | 27 | 26 | 25 | 24 | 23 | 22 | 21 | 20 | 19 | 18 | 17 | 16 | |
|-----------|------------|----------|------------|-----------|------------|------------|----|------------|----|------------|----|------------|----|------------|----|--|
| MODE15[1: | | | MODE14[1: | MODE13[1: | | MODE12[1: | | MODE11[1: | | MODE10[1: | | MODE9[1:0] | | MODE8[1:0] | | |
| 0] | | | 0] | 0] | | 0] | | 0] | | 0] | | | | | | |
| rw | rw | rw | rw | rw | rw | rw | rw | rw | rw | rw | rw | rw | rw | rw | rw | |
| 15 | 14 | 13<br>12 | | 11 | 10 | 9 | 8 | 7<br>6 | | 5<br>4 | | 3 | 2 | | 0 | |
| | MODE7[1:0] | | MODE6[1:0] | | MODE5[1:0] | MODE4[1:0] | | MODE3[1:0] | | MODE2[1:0] | | MODE1[1:0] | | MODE0[1:0] | | |
| rw | rw | | rw | rw<br>rw | | rw | rw | rw | rw | rw | rw | rw | rw | rw | rw | |
| Bit | Name | R/W | Reset Value | Function |
|------|------------|-----|-------------|-------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------|
| 15:0 | MODEy[1:0] | RW | | y = 150<br>These bits are written by software to configure the I/O<br>mode<br>00: Input mode<br>01: General purpose output mode<br>10: Alternate function mode<br>11: Analog mode (reset state) |
## <span id="page-82-3"></span>**9.4.2. GPIO port output type register (GPIOx\_OTYPER) (x = A, B, C)**
#### **Address offset:** 0x04
**Reset value:** 0x0000 0000
| 31 | 30 | 29 | 28 | 27 | 26 | 25 | 24 | 23 | 22 | 21 | 20 | 19 | 18 | 17 | 16 |
|------|------|------|------|------|------|-----|-----|-----|-----|-----|-----|-----|-----|-----|-----|
| Res | Res | Res | Res | Res | Res | Res | Res | Res | Res | Res | Res | Res | Res | Res | Res |
| | | | | | | | | | | | | | | | |
| 15 | 14 | 13 | 12 | 11 | 10 | 9 | 8 | 7 | 6 | 5 | 4 | 3 | 2 | 1 | 0 |
| OT15 | OT14 | OT13 | OT12 | OT11 | OT10 | OT9 | OT8 | OT7 | OT6 | OT5 | OT4 | OT3 | OT2 | OT1 | OT0 |
| rw | rw | rw | rw | rw | rw | rw | rw | rw | rw | rw | rw | rw | rw | rw | rw |
| Bit | Name | R/W | Reset Value | Function |
|-------|------------|-----|-------------|-------------------------------------------------------------------------------------------------------------|
| 31:16 | Reserved | | | |
| 15: 0 | MODE[15:0] | RW | | These bits are written by software to configure the I/O<br>output type<br>0: Output push-pull (reset state) |
1: Output open-drain
## <span id="page-83-0"></span>**9.4.3. GPIO port output speed register (GPIOx\_OSPEEDR) (x = A, B, C)**
#### **Address offset:** 0x08
**Reset value:** 0x0000 0000(for other ports)
GPIOB reset value
- a) Flash option byte configured with SWD:0x0000 0000
- b) Flash ooption byte not configured with SWD:0x0000 3000
- c) Reset value: 0x0000 0000(for other ports)
GPIOC reset value
- a) Flash option byte configured with SWD:0x0000 0003
- b) Flash ooption byte not configured with SWD:0x0000 0000
| 31 | 30 | 29 | 28 | 27 | 26 | 25 | 24 | 23 | 22 | 21 | 20 | 19 | 18 | 17 | 16 |
|----------|----|----------|---------|----------|----|----------|----|----------|----|---------|----------|---------|----|---------|----|
| OSPEED15 | | OSPEED14 | | OSPEED13 | | OSPEED12 | | OSPEED11 | | | OSPEED10 | OSPEED9 | | OSPEED8 | |
| rw | rw | rw | rw | rw | rw | rw | rw | rw | rw | rw | rw | rw | rw | rw | rw |
| 15 | 14 | 13 | 12 | 11 | 10 | 9 | 8 | 7 | 6 | 5 | 4 | 3 | 2 | 1 | 0 |
| OSPEED7 | | | OSPEED6 | OSPEED5 | | OSPEED4 | | OSPEED3 | | OSPEED2 | | OSPEED1 | | OSPEED0 | |
| rw | rw | rw | rw | rw | rw | rw | rw | rw | rw | rw | rw | rw | rw | rw | rw |
| Bit | Name | R/W | Reset Value | Function |
|------|--------------|-----|-------------|----------------------------------------------------------------------------------------------------------------------------------------------------------------|
| 31:0 | OSPEEDy[1:0] | RW | | Y = 150<br>These bits are written by software to configure the I/O<br>output speed<br>00:Very low speed<br>01:Low speed<br>10:High speed<br>11:Very high speed |
## <span id="page-83-1"></span>**9.4.4. GPIO port pull-up and pull-down register (GPIOx\_PUPDR) (x = A, B, C)**
#### **Address offset:** 0x0C
#### **Reset value:**
0x0000 0020(for port A) GPIOB reset value
- a) Flash option byte configured with SWD:0x0000 0000
- b) Flash ooption byte not configured with SWD:0x0000 1000
GPIOC reset value
- a) Flash option byte configured with SWD:0x0000 0001
- b) Flash ooption byte not configured with SWD:0x0000 0000
| 31 | 30 | 29 | 28 | 27 | 26 | 25 | 24 | 23 | 22 | 21 | 20 | 19 | 18 | 17 | 16 |
|-----------------|----|----|-----------------|-----------------|----|-----------------|----|-----------------|----|-----------------|----|------------|----|------------|----|
| PUPD15[1:0<br>] | | | PUPD14[1:0<br>] | PUPD13[1:0<br>] | | PUPD12[1:0<br>] | | PUPD11[1:0<br>] | | PUPD10[1:0<br>] | | PUPD9[1:0] | | PUPD8[1:0] | |
| rw | rw | rw | rw | rw | rw | rw | rw | rw | rw | rw | rw | rw | rw | rw | rw |
| 15 | 14 | 13 | 12 | 11 | 10 | 9 | 8 | 7 | 6 | 5 | 4 | 3 | 2 | 1 | 0 |
| PUPD7[1:0] | | | PUPD6[1:0] | PUPD5[1:0] | | PUPD4[1:0] | | PUPD3[1:0] | | PUPD2[1:0] | | PUPD1[1:0] | | PUPD0[1:0] | |
| rw | rw | rw | rw | rw | rw | rw | rw | rw | rw | rw | rw | rw | rw | rw | rw |
| Bit | Name | R/W | Reset Value | Function |
|------|-------------|-----|-------------|---------------------------------------------------------------------------------------------------------------------------------------------------------------------------|
| 31:0 | PUPDy [1:0] | RW | | Y = 150<br>These bits are written by software to configure the I/O<br>pull-up or pull-down<br>00: No pull-up or pull-down<br>01: Pull-up<br>10: Pull-down<br>11: Reserved |
## <span id="page-84-0"></span>**9.4.5. GPIO port input data register (GPIOx\_IDR) (x = A, B, C)**
#### **Address offset:** 0x10
**Reset value:** 0x0000 XXXX
| 31 | 30 | 29 | 28 | 27 | 26 | 25 | 24 | 23 | 22 | 21 | 20 | 19 | 18 | 17 | 16 |
|----------|------|------|------|------|------|-----|-----|-----|-----|-----|-----|-----|-----|-----|-----|
| Reserved | | | | | | | | | | | | | | | |
| 15 | 14 | 13 | 12 | 11 | 10 | 9 | 8 | 7 | 6 | 5 | 4 | 3 | 2 | 1 | 0 |
| ID15 | ID14 | ID13 | ID12 | ID11 | ID10 | ID9 | ID8 | ID7 | ID6 | ID5 | ID4 | ID3 | ID2 | ID1 | ID0 |
| r | r | r | r | r | r | r | r | r | r | r | r | r | r | r | r |
| Bit | Name | R/W | Reset Value | Function |
|-------|----------|-----|-------------|------------------------------------------------------------------------------------------|
| 31:16 | Reserved | | | |
| 15:0 | Idy | R | | y = 150<br>This is read-only, it contain the input value of the corre<br>sponds I/O port |
## <span id="page-84-1"></span>**9.4.6. GPIO port output data register (GPIOx\_ODR) (x = A, B, C)**
#### **Address offset:** 0x14
#### **Reset value:** 0x0000 0000
| 31 | 30 | 29 | 28 | 27 | 26 | 25 | 24 | 23 | 22 | 21 | 20 | 19 | 18 | 17 | 16 |
|----------|-----|-----|-----|-----|-----|----|----|----|----|----|----|----|----|----|----|
| Reserved | | | | | | | | | | | | | | | |
| 15 | 14 | 13 | 12 | 11 | 10 | 9 | 8 | 7 | 6 | 5 | 4 | 3 | 2 | 1 | 0 |
| OD1 | OD1 | OD1 | OD1 | OD1 | OD1 | OD | OD | OD | OD | OD | OD | OD | OD | OD | OD |
| 5 | 4 | 3 | 2 | 1 | 0 | 9 | 8 | 7 | 6 | 5 | 4 | 3 | 2 | 1 | 0 |
| rw | rw | rw | rw | rw | rw | rw | rw | rw | rw | rw | rw | rw | rw | rw | rw |
| Bit | Name | R/W | Reset Value | Function | | | | | | |
|--------|----------|-----|-------------|-------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------|--|--|--|--|--|--|
| 31: 16 | Reserved | | | | | | | | | |
| 15: 0 | Ody[1:0] | RW | | y = 150<br>These bits are readable and writable by software.<br>Note: For GPIOx_BSRR or GPIOx_BRR registers. (x=<br>A,B,F),<br>each<br>ODR<br>bit<br>can<br>be<br>independently<br>set/cleared. | | | | | | |
## <span id="page-84-2"></span>**9.4.7. GPIO port bit set/reset register (GPIOx\_BSRR) (x = A, B, C)**
#### **Address offset:** 0x18
| 31 | 30 | 29 | 28 | 27 | 26 | 25 | 24 | 23 | 22 | 21 | 20 | 19 | 18 | 17 | 16 |
|------|------|------|------|------|------|-----|-----|-----|-----|-----|-----|-----|-----|-----|-----|
| BR15 | BR14 | BR13 | BR12 | BR11 | BR10 | BR9 | BR8 | BR7 | BR6 | BR5 | BR4 | BR3 | BR2 | BR1 | BR0 |
| w | w | w | w | w | w | w | w | w | w | w | w | w | w | w | w |
| 15 | 14 | 13 | 12 | 11 | 10 | 9 | 8 | 7 | 6 | 5 | 4 | 3 | 2 | 1 | 0 |
| BS15 | BS14 | BS13 | BS12 | BS11 | BS10 | BS9 | BS8 | BS7 | BS6 | BS5 | BS4 | BS3 | BS2 | BS1 | BS0 |
| w | w | w | w | w | w | w | w | w | w | w | w | w | w | w | w |
| Bit | Name | R/W | Reset Value | Function |
|-------|------|-----|-------------|-------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------|
| 31:16 | BRy | W | | y = 150<br>These bits are write-only. A read to these bits returns<br>the value of 0.<br>0: No action on the corresponding ODRy bit<br>1: Clear the corresponding ODRy bit<br>Note: If the corresponding bits of Bsy and Bry are set<br>at the same time, the Bsy bit has priority. |
| 15: 0 | BSy | W | | y = 150<br>These bits are write-only. A read to these bits returns<br>the value of 0.<br>0: No action on the corresponding ODRy bit<br>1: Set the corresponding ODRy bit |
## <span id="page-85-0"></span>**9.4.8. GPIO port configuration lock register (GPIOx\_LCKR) (x = A, B, C)**
This register is used to lock the configuration of the port bits when the correct write sequence is applied to bit 16 (LCKK) set. The value of bits [15:0] is used to lock the configuration of the GPIO, the value of LCKR [15:0] must not change. When the LOCK sequence has been applied on the a port bit, the configuration of the port bits cannot be changed until the next system reset.
Note: A special write sequence is used to write the GPIOx\_LCKR register. Only word accesses can be performed during the lock sequence.
Each lock bit freezes a specific configuration register (control and alternate function registers)
#### **Address offset:** 0x1C
| 31 | 30 | 29 | 28 | 27 | 26 | 25 | 24 | 23 | 22 | 21 | 20 | 19 | 18 | 17 | 16 |
|-----|-----|-----|-----|-----|-----|-----|-----|-----|-----|-----|-----|-----|-----|-----|----------|
| Res | Res | Res | Res | Res | Res | Res | Res | Res | Res | Res | Res | Res | Res | Res | LCK<br>K |
| | | | | | | | | | | | | | | | rw |
| 15 | 14 | 13 | 12 | 11 | 10 | 9 | 8 | 7 | 6 | 5 | 4 | 3 | 2 | 1 | 0 |
| LCK | LCK | LCK | LCK | LCK | LCK | LCK | LCK | LCK | LCK | LCK | LCK | LCK | LCK | LCK | LCK |
| 15 | 14 | 13 | 12 | 11 | 10 | 9 | 8 | 7 | 6 | 5 | 4 | 3 | 2 | 1 | 0 |
| rw | rw | rw | rw | rw | rw | rw | rw | rw | rw | rw | rw | rw | rw | rw | rw |
#### **Reset value:** 0x0000 0000
| Bit | Name | R/W | Reset Value | Function |
|-------|----------|-----|-------------|-------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------|
| 31:17 | Reserved | | | |
| 16 | LCKK | RW | | This bit can be read any time, it can only be modified by<br>the lock key write sequence<br>0: The port configuration lock key not active<br>1: The port configuration lock key activated, and the<br>GPIOx_LCKR register is locked until the next system re<br>set<br>LOCK key write sequence:<br>The write sequence of the lock key: write 1- > write 0- ><br>write 1- > read 0- > read 1. The last read can be ignored,<br>but it can be used to confirm that the lock key has been<br>activated.<br>Note: During the LOCK key write sequence, the value of<br>LCK[15:0] must not change. Any error in the lock se<br>quence will stop the lock key from being activated. After<br>the first lock sequence on any bit of the port, any read<br>access on the LCKK will return 1 until the next MCU reset<br>or peripheral reset. |
| 15: 0 | LCKy | RW | | y = 150<br>These bits are readable and writable but can only be writ<br>ten when the LCKK bit is 0.<br>0: Port configuration not locked<br>1: Port configuration locked |
## <span id="page-85-1"></span>**9.4.9. GPIO alternate function register (low) (GPIOx\_AFRL) (x = A, B, C)**
#### **Address offset:** 0x20
| 31 | 30 | 29 | 28 | 27 | 26 | 25 | 24 | 23 | 22 | 21 | 20 | 19 | 18 | 17 | 16 |
|------|----|-------------|----|------|----|-------------|----|------|----|----|-------------|------|--------------|----|----|
| Res. | | AFSEL7[2:0] | | Res. | | AFSEL6[2:0] | | Res. | | | AFSEL5[2:0] | Res. | AF-SEL4[2:0] | | |
| | rw | rw | rw | | rw | rw | rw | | rw | rw | rw | | rw | rw | rw |
| 15 | 14 | 13 | 12 | 11 | 10 | 9 | 8 | 7 | 6 | 5 | 4 | 3 | 2 | 1 | 0 |
| Res. | | AFSEL3[2:0] | | Res. | | AFSEL2[2:0] | | Res. | | | AFSEL1[2:0] | Res. | AFSEL0[2:0] | | |
| | rw | rw | rw | | rw | rw | rw | | rw | rw | rw | | rw | rw | rw |
| Bit | Name | R/W | Reset Value | Function |
|-----|----------|-----|-------------|----------|
| 31 | Reserved | | | |
| Bit | Name | R/W | Reset Value | Function<br>These bits are written by software to configure |
|-------|-------------------------|-----|-------------|-------------------------------------------------------------|
| | | | | alternate function I/O. |
| | | | | AFSELy selection: |
| | | | | 000:AF0 |
| | | | | |
| | | | | 001:AF1 |
| 30:28 | AFSELy[2:0]((y= 7 to 0) | RW | | 010:AF2 |
| | | | | 011:AF3 |
| | | | | 100:AF4 |
| | | | | 101:AF5 |
| | | | | 110:AF6 |
| | | | | 111:AF7 |
| 27 | Reserved | | | |
| | | | | These bits are written by software to configure |
| | | | | alternate function I/O. |
| | | | | AFSELy selection: |
| | | | | 000:AF0 |
| | | | | 001:AF1 |
| | | | | |
| 26:24 | AFSELy[2:0]((y= 7 to 0) | RW | | 010:AF2 |
| | | | | 011:AF3 |
| | | | | 100:AF4 |
| | | | | 101:AF5 |
| | | | | 110:AF6 |
| | | | | 111:AF7 |
| 23 | Reserved | | | |
| | | | | These bits are written by software to configure |
| | | | | alternate function I/O. |
| | AFSELy[2:0]((y= 7 to 0) | | | AFSELy selection: |
| | | | | 000:AF0 |
| | | | | 001:AF1 |
| | | | | |
| 22:20 | | RW | | 010:AF2 |
| | | | | 011:AF3 |
| | | | | 100:AF4 |
| | | | | 101:AF5 |
| | | | | 110:AF6 |
| | | | | 111:AF7 |
| 19 | Reserved | | | |
| | | | | These bits are written by software to configure |
| | | | | alternate function I/O. |
| | | | | AFSELy selection: |
| | | | | 000:AF0 |
| | | | | 001:AF1 |
| | | | | |
| 18:16 | AFSELy[2:0]((y= 7 to 0) | RW | | 010:AF2 |
| | | | | 011:AF3 |
| | | | | 100:AF4 |
| | | | | 101:AF5 |
| | | | | 110:AF6 |
| | | | | 111:AF7 |
| 15 | Reserved | | | |
| | | | | These bits are written by software to configure |
| | | | | alternate function I/O. |
| | | | | AFSELy selection: |
| | | | | 000:AF0 |
| | | | | 001:AF1 |
| 14:12 | AFSELy[2:0]((y= 7 to 0) | RW | | 010:AF2 |
| | | | | |
| | | | | 011:AF3 |
| | | | | 100:AF4 |
| | | | | 101:AF5 |
| | | | | 110:AF6 |
| Bit | Name | R/W | Reset Value | Function |
|------|-------------------------|-----|-------------|-----------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------|
| | | | | 111:AF7 |
| 11 | Reserved | | | |
| 10:8 | AFSELy[2:0]((y= 7 to 0) | RW | | These bits are written by software to configure<br>alternate function I/O.<br>AFSELy selection:<br>000:AF0<br>001:AF1<br>010:AF2<br>011:AF3<br>100:AF4<br>101:AF5<br>110:AF6<br>111:AF7 |
| 11 | Reserved | | | |
| 10:8 | AFSELy[2:0]((y= 7 to 0) | RW | | These bits are written by software to configure<br>alternate function I/O.<br>AFSELy selection:<br>000:AF0<br>001:AF1<br>010:AF2<br>011:AF3<br>100:AF4<br>101:AF5<br>110:AF6<br>111:AF7 |
| 7 | Reserved | | | |
| 6:4 | AFSELy[2:0]((y= 7 to 0) | RW | | These bits are written by software to configure<br>alternate function I/O.<br>AFSELy selection:<br>000:AF0<br>001:AF1<br>010:AF2<br>011:AF3<br>100:AF4<br>101:AF5<br>110:AF6<br>111:AF7 |
| 3 | Reserved | | | |
| 2:0 | AFSELy[2:0]((y= 7 to 0) | RW | | These bits are written by software to configure<br>alternate function I/O.<br>AFSELy selection:<br>000:AF0<br>001:AF1<br>010:AF2<br>011:AF3<br>100:AF4<br>101:AF5<br>110:AF6<br>111:AF7 |
## <span id="page-87-0"></span>**9.4.10. GPIO alternate function register(high)(GPIOx\_AFRH) (x = A, B, C)**
Address offset: 0x24
| 31 | 30 | 29 | 28 | 27 | 26 | 25 | 24 | 23 | 22 | 21 | 20 | 19 | 18 | 17 | 16 |
|------|----|--------------|----|------|----|--------------|----|------|----|----|--------------|------|----|--------------|----|
| Res. | | AFSEL15[2:0] | | Res. | | AFSEL14[2:0] | | Res. | | | AFSEL13[2:0] | Res. | | AFSEL12[2:0] | |
| | rw | rw | rw | | rw | rw | rw | | rw | rw | rw | | rw | rw | rw |
|------|----|----|--------------|------|----|--------------|----|------|----|----|-------------|------|----|-------------|----|
| 15 | 14 | 13 | 12 | 11 | 10 | 9 | 8 | 7 | 6 | 5 | 4 | 3 | 2 | 1 | 0 |
| Res. | | | AFSEL11[3:0] | Res. | | AFSEL10[2:0] | | Res. | | | AFSEL9[2:0] | Res. | | AFSEL8[2:0] | |
| | rw | rw | rw | | rw | rw | rw | | rw | rw | rw | | rw | rw | rw |
| Bit | Name | R/W | Reset Value | Function |
|-------|--------------------------|-----|-------------|-----------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------|
| 31 | Reserved | | | |
| 30:28 | AFSELy[2:0]((y= 8 to 15) | RW | | These bits are written by software to configure<br>alternate function I/O.<br>AFSELy selection:<br>000:AF0<br>001:AF1<br>010:AF2<br>011:AF3<br>100:AF4<br>101:AF5<br>110:AF6<br>111:AF7 |
| 27 | Reserved | | | |
| 26:24 | AFSELy[2:0]((y= 8 to 15) | RW | | These bits are written by software to configure<br>alternate function I/O.<br>AFSELy selection:<br>000:AF0<br>001:AF1<br>010:AF2<br>011:AF3<br>100:AF4<br>101:AF5<br>110:AF6<br>111:AF7 |
| 23 | Reserved | | | |
| 22:20 | AFSELy[2:0]((y= 8 to 15) | RW | | These bits are written by software to configure<br>alternate function I/O.<br>AFSELy selection:<br>000:AF0<br>001:AF1<br>010:AF2<br>011:AF3<br>100:AF4<br>101:AF5<br>110:AF6<br>111:AF7 |
| 19 | Reserved | | | |
| 18:16 | AFSELy[2:0]((y= 8 to 15) | RW | | These bits are written by software to configure<br>alternate function I/O.<br>AFSELy selection:<br>000:AF0<br>001:AF1<br>010:AF2<br>011:AF3<br>100:AF4<br>101:AF5<br>110:AF6<br>111:AF7 |
| 15 | Reserved | | | |
| 14:12 | AFSELy[2:0]((y= 8 to 15) | RW | | These bits are written by software to configure<br>alternate function I/O.<br>AFSELy selection: |
| Bit | Name | R/W | Reset Value | Function |
|------|--------------------------|-----|-------------|-------------------------------------------------|
| | | | | 000:AF0 |
| | | | | 001:AF1 |
| | | | | 010:AF2 |
| | | | | 011:AF3 |
| | | | | 100:AF4 |
| | | | | 101:AF5 |
| | | | | 110:AF6 |
| | | | | 111:AF7 |
| 11 | Reserved | | | |
| | | | | These bits are written by software to configure |
| | | | | alternate function I/O. |
| | | | | AFSELy selection: |
| | | | | 000:AF0 |
| | | | | 001:AF1 |
| 10:8 | AFSELy[2:0]((y= 8 to 15) | RW | | 010:AF2 |
| | | | | 011:AF3 |
| | | | | 100:AF4 |
| | | | | 101:AF5 |
| | | | | 110:AF6 |
| | | | | 111:AF7 |
| 11 | Reserved | | | |
| | | | | These bits are written by software to configure |
| | | | | alternate function I/O.<br>AFSELy selection: |
| | | | | 000:AF0 |
| | | | | |
| | | | | 001:AF1 |
| 10:8 | AFSELy[2:0]((y= 8 to 15) | RW | | 010:AF2 |
| | | | | 011:AF3 |
| | | | | 100:AF4 |
| | | | | 101:AF5 |
| | | | | 110:AF6 |
| | | | | 111:AF7 |
| 7 | Reserved | | | |
| | | | | These bits are written by software to configure |
| | | | | alternate function I/O.<br>AFSELy selection: |
| | | | | |
| | | | | 000:AF0 |
| | | | | 001:AF1 |
| 6:4 | AFSELy[2:0]((y= 8 to 15) | RW | | 010:AF2 |
| | | | | 011:AF3 |
| | | | | 100:AF4 |
| | | | | 101:AF5 |
| | | | | 110:AF6 |
| | | | | 111:AF7 |
| 3 | Reserved | | | |
| | | | | These bits are written by software to configure |
| | | | | alternate function I/O.<br>AFSELy selection: |
| | | | | |
| | | | | 000:AF0 |
| | | | | 001:AF1 |
| 2:0 | AFSELy[2:0]((y= 8 to 15) | RW | | 010:AF2 |
| | | | | 011:AF3 |
| | | | | 100:AF4 |
| | | | | 101:AF5 |
| | | | | 110:AF6 |
| | | | | 111:AF7 |
## <span id="page-90-0"></span>**9.4.11. GPIO port bit reset register (GPIOx\_BRR) (x = A, B, C)**
#### **Address offset:** 0x28
| Reset value: 0x0000 0000 |
|--------------------------|
|--------------------------|
| 31 | 30 | 29 | 28 | 27 | 26 | 25 | 24 | 23 | 22 | 21 | 20 | 19 | 18 | 17 | 16 |
|------|------|------|------|------|------|-----|-----|-----|-----|-----|-----|-----|-----|-----|-----|
| | | | | | | | Res | | | | | | | | |
| | | | | | | | | | | | | | | | |
| 15 | 14 | 13 | 2 | 11 | 10 | 9 | 8 | 7 | 6 | 5 | 4 | 3 | 2 | 1 | 0 |
| BR15 | BR14 | BR13 | BR12 | BR11 | BR10 | BR9 | BR8 | BR7 | BR6 | BR5 | BR4 | BR3 | BR2 | BR1 | BR0 |
| w | w | w | w | w | w | w | w | w | w | w | w | w | w | w | w |
| Bit | Name | R/W | Reset Value | Function |
|-------|----------|-----|-------------|--------------------------------------------------------------------------------------------------------------------------------------------------------------------------|
| 31:16 | Reserved | | | |
| 15:0 | Bry | RW | | y = 150<br>These bits are write-only. A read to these bots returns<br>the value of 0.<br>0: No action on the corresponding Ody bit<br>1: Clear the corresponding Ody bit |
#### <span id="page-90-1"></span>**9.4.12. GPIO register map**
| O<br>ff<br>s<br>e<br>t | Reg<br>ister | 31 | 30 | 29 | 28 | 27 | 26 | 25 | 24 | 23 | 22 | 21 | 20 | 19 | 18 | 17 | 16 | 15 | 14 | 13 | 12 | 11 | 10 | 9 | 8 | 7 | 6 | 5 | 4 | 3 | 2 | 1 | 0 |
|------------------------|--------------------------------------------|-------------|------|-------------|-------------|-------------|-------------|-------------|------|-------------|-------------|-------------|------|-------------|------|-------------|------|-------------|------|-------------|------|-------------|------|-------------|-----|-------------|-----|-------------|-----|-------------|-----|-------------|-----|
| | GPIO<br>A_M<br>ODE<br>R | MODE15[1:0] | | | MODE14[1:0] | | MODE13[1:0] | MODE12[1:0] | | | MODE11[1:0] | MODE10[1:0] | | MODE9[1:0] | | MODE8[1:0] | | MODE7[1:0] | | MODE6[1:0] | | MODE5[1:0] | | MODE4[1:0] | | MODE3[1:0] | | MODE2[1:0] | | MODE1[1:0] | | MODE0[1:0] | |
| | Re<br>set<br>value | 1 | 1 | 1 | 0 | 1 | 0 | 1 | 1 | 1 | 1 | 1 | 1 | 1 | 1 | 1 | 1 | 1 | 1 | 1 | 1 | 1 | 1 | 1 | 1 | 1 | 1 | 1 | 1 | 1 | 1 | 1 | 1 |
| 0<br>x<br>0 | GPIO<br>B_M<br>ODE<br>R | MODE15[1:0] | | | MODE14[1:0] | | MODE13[1:0] | MODE12[1:0] | | | MODE11[1:0] | MODE10[1:0] | | MODE9[1:0] | | MODE8[1:0] | | MODE7[1:0] | | MODE6[1:0] | | MODE5[1:0] | | MODE4[1:0] | | MODE3[1:0] | | MODE2[1:0] | | MODE1[1:0] | | MODE0[1:0] | |
| 0 | Re<br>set<br>value | 0 | 0 | 0 | 0 | 0 | 0 | 0 | 0 | 0 | 0 | 0 | 0 | 0 | 0 | 1 | 1 | 1 | 1 | 1 | 1 | 1 | 1 | 1 | 1 | 1 | 1 | 1 | 1 | 1 | 1 | 1 | 1 |
| | GPIO<br>C_M<br>ODE<br>R | MODE15[1:0 | ] | MODE14[1:0 | ] | MODE13[1:0 | ] | MODE12[1:0 | ] | MODE11[1:0 | ] | MODE10[1:0 | ] | MODE9[1:0] | | MODE8[1:0] | | MODE7[1:0] | | MODE6[1:0] | | MODE5[1:0] | | MODE4[1:0] | | MODE3[1:0] | | MODE2[1:0] | | MODE1[1:0] | | MODE0[1:0] | |
| | Re<br>set<br>value | 0 | 0 | 0 | 0 | 0 | 0 | 0 | 0 | 0 | 0 | 0 | 0 | 0 | 0 | 0 | 0 | 0 | 0 | 0 | 0 | 0 | 0 | 0 | 0 | 1 | 1 | 1 | 1 | 1 | 1 | 1 | 1 |
| 0<br>x<br>0 | GPIO<br>C_O<br>TYP<br>ER<br>(x=A,<br>B, C) | Res. | Res. | Res. | Res. | Res. | Res. | Res. | Res. | Res. | Res. | Res. | Res. | Res. | Res. | Res. | Res. | OT15 | OT14 | OT13 | OT12 | OT11 | OT10 | OT9 | OT8 | OT7 | OT6 | OT5 | OT4 | OT3 | OT2 | OT1 | OT0 |
| 4 | Re<br>set<br>value | | | | | | | | | | | | | | | | | 0 | 0 | 0 | 0 | 0 | 0 | 0 | 0 | 0 | 0 | 0 | 0 | 0 | 0 | 0 | 0 |
| 0<br>x<br>0 | GPIO<br>A_O<br>SPE<br>EDR | OSPEED15[1: | 0] | OSPEED14[1: | 0] | OSPEED13[1: | 0] | OSPEED12[1: | 0] | OSPEED11[1: | 0] | OSPEED10[1: | 0] | OSPEED9[1:0 | ] | OSPEED8[1:0 | ] | OSPEED7[1:0 | ] | OSPEED6[1:0 | ] | OSPEED5[1:0 | ] | OSPEED4[1:0 | ] | OSPEED3[1:0 | ] | OSPEED2[1:0 | ] | OSPEED1[1:0 | ] | OSPEED0[1:0 | ] |
| 8 | Re<br>set<br>value | 0 | 0 | 0 | 0 | 1 | 1 | 0 | 0 | 0 | 0 | 0 | 0 | 0 | 0 | 0 | 0 | 0 | 0 | 0 | 0 | 0 | 0 | 0 | 0 | 0 | 0 | 0 | 0 | 0 | 0 | 0 | 0 |
| 0<br>x<br>2<br>0 | C | 0<br>x<br>1 | 8 | 0<br>x<br>1 | 4 | 0<br>x<br>1 | 0 | 0<br>x<br>1 | C | 0<br>x<br>0 | C | 0<br>x<br>0 | C | 0<br>x<br>0 | 8 | 0<br>x<br>0 | O<br>ff<br>s<br>e<br>t |
|--------------------------------------|--------------------|--------------------------------------|-------------------------|-------------------------------------|--------------------|-------------------------------------|--------------------|-------------------------------------|--------------------|-------------------------|--------------------|-------------------------|--------------------|-------------------------|--------------------|------------------------------------------|------------------------|
| GPIO<br>x_AF<br>RL<br>(x=A,<br>B, C) | Re<br>set<br>value | GPIO<br>x_LC<br>KR<br>(x=A,<br>B, C) | )<br>Re<br>set<br>value | GPIO<br>x_BS<br>RR<br>(x=A,<br>B,CF | Re<br>set<br>value | GPIO<br>x_OD<br>R<br>(x=A,<br>B, C) | Re<br>set<br>value | GPIO<br>x_ID<br>R<br>(x=A,<br>B, C) | Re<br>set<br>value | GPIO<br>C_P<br>UPD<br>R | Re<br>set<br>value | GPIO<br>B_P<br>UPD<br>R | Re<br>set<br>value | GPIO<br>A_P<br>UPD<br>R | Re<br>set<br>value | GPIO<br>x_OS<br>PEE<br>DR<br>(x=B,<br>C) | Reg<br>ister |
| | | Res. | 0 | BR15 | | Res. | | Res. | 0 | PUPD15[1: | 0 | PUPD15[1:0 | 0 | PUPD15[1:0] | 0 | OSPEED15[1: | 31 |
| AFSEL7<br>[3:0] | | Res. | 0 | BR14 | | Res. | | Res. | 0 | 0] | 0 | ] | 0 | | 0 | 0] | 30 |
| | | Res. | 0 | BR13 | | Res. | | Res. | 0 | PUPD14[1: | 0 | PUPD14[1:0 | 1 | | 0 | OSPEED14[1: | 29 |
| | | Res. | 0 | BR12 | | Res. | | Res. | 0 | 0] | 0 | ] | 0 | PUPD14[1:0] | 0 | 0] | 28 |
| | | Res. | 0 | BR11 | | Res. | | Res. | 0 | PUPD13[1: | 0 | PUPD13[1:0 | 0 | PUPD13[1:0] | 0 | OSPEED13[1: | 27 |
| AFSEL6<br>[3:0] | | Res. | 0 | BR10 | | Res. | | Res. | 0 | 0] | 0 | ] | 1 | | 0 | 0] | 26 |
| | | Res. | 0 | BR9 | | Res. | | Res. | 0 | PUPD12[1: | 0 | PUPD12[1:0 | 0 | PUPD12[1:0] | 0 | OSPEED12[1: | 25 |
| | | Res. | 0 | BR8 | | Res. | | Res. | 0 | 0] | 0 | ] | 0 | | 0 | 0] | 24 |
| | | Res. | 0 | BR7 | | Res. | | Res. | 0 | PUPD11[1: | 0 | PUPD11[1:0 | 0 | PUPD11[1:0] | 0 | OSPEED11[1: | 23 |
| AFSEL5<br>[3:0] | | Res. | 0 | BR6 | | Res. | | Res. | 0 | 0] | 0 | ] | 0 | | 0 | 0] | 22 |
| | | Res. | 0 | BR5 | | Res. | | Res. | 0 | PUPD10[1: | 0 | PUPD10[1:0 | 0 | PUPD10[1:0] | 0 | OSPEED10[1: | 21 |
| | | Res. | 0 | BR4 | | Res. | | Res. | 0 | 0] | 0 | ] | 0 | | 0 | 0] | 20 |
| | | Res. | 0 | BR3 | | Res. | | Res. | 0 | PUPD9[1:0] | 0 | PUPD9[1:0] | 0 | PUPD9[1:0] | 0 | OSPEED9[1:0] | 19 |
| [3:0] | | Res. | 0 | BR2 | | Res. | | Res. | 0 | | 0 | | 0 | | 0 | | 18 |
| AFSEL4 | | Res. | 0 | BR1 | | Res. | | Res. | 0 | PUPD8[1:0] | 0 | PUPD8[1:0] | 0 | PUPD8[1:0] | 0 | OSPEED8[1:0] | 17 |
| | 0 | LCKK | 0 | BR0 | | Res. | | Res. | 0 | | 0 | | 0 | | 0 | | 16 |
| | 0 | LCK15 | 0 | BS15 | 0 | OD15 | X | ID15 | 0 | PUPD7[1:0] | 0 | PUPD7[1:0] | 0 | PUPD7[1:0] | 0 | OSPEED7[1:0] | 15 |
| AFSEL3<br>[3:0] | 0 | LCK14 | 0 | BS14 | 0 | OD14 | X | ID14 | 0 | | 0 | | 0 | | 0 | | 14 |
| | 0 | LCK13 | 0 | BS13 | 0 | OD13 | X | ID13 | 0 | PUPD6[1:0] | 0 | PUPD6[1:0] | 0 | PUPD6[1:0] | 0 | OSPEED6[1:0] | 13 |
| | 0 | LCK12 | 0 | BS12 | 0 | OD12 | X | ID12 | 0 | | 0 | | 0 | | 0 | | 12 |
| | 0 | LCK11 | 0 | BS11 | 0 | OD11 | X | ID11 | 0 | PUPD5[1:0] | 0 | PUPD5[1:0] | 0 | PUPD5[1:0] | 0 | OSPEED5[1:0] | 11 |
| AFSEL2<br>[3:0] | 0 | LCK10 | 0 | BS10 | 0 | OD10 | X | ID10 | 0 | | 0 | | 0 | | 0 | | 10 |
| | 0 | LCK9 | 0 | BS9 | 0 | OD9 | X | ID9 | 1 | PUPD4[1:0] | 0 | PUPD4[1:0] | 0 | PUPD4[1:0] | 0 | OSPEED4[1:0] | 9 |
| | 0 | LCK8 | 0 | BS8 | 0 | OD8 | X | ID8 | 0 | | 0 | | 0 | | 0 | | 8 |
| | 0 | LCK7 | 0 | BS7 | 0 | OD7 | X | ID7 | 0 | PUPD3[1:0] | 0 | PUPD3[1:0] | 0 | PUPD3[1:0] | 0 | OSPEED3[1:0] | 7 |
| AFSEL1<br>[3:0] | 0 | LCK6 | 0 | BS6 | 0 | OD6 | X | ID6 | 0 | | 0 | | 0 | | 0 | | 6 |
| | 0 | LCK5 | 0 | BS5 | 0 | OD5 | X | ID5 | 0 | PUPD2[1:0] | 0 | PUPD2[1:0] | 0 | PUPD2[1:0] | 0 | OSPEED2[1:0] | 5 |
| | 0 | LCK4 | 0 | BS4 | 0 | OD4 | X | ID4 | 0 | | 0 | | 0 | | 0 | | 4 |
| | 0 | LCK3 | 0 | BS3 | 0 | OD3 | X | ID3 | 0 | PUPD1[1:0] | 0 | PUPD1[1:0] | 0 | PUPD1[1:0] | 0 | OSPEED1[1:0] | 3 |
| [3:0] | 0 | LCK2 | 0 | BS2 | 0 | OD2 | X | ID2 | 0 | | 0 | | 0 | | 0 | | 2 |
| AFSEL0 | 0 | LCK1 | 0 | BS1 | 0 | OD1 | X | ID1 | 0 | PUPD0[1:0] | 0 | PUPD0[1:0] | 0 | PUPD0[1:0] | 0 | OSPEED0[1:0] | 1 |
| | 0 | LCK0 | 0 | BS0 | 0 | OD0 | X | ID0 | 0 | | 0 | | 0 | | 0 | | 0 |
| O<br>ff<br>s<br>e<br>t | Reg<br>ister | 31 | 30 | 29 | 28 | 27 | 26 | 25 | 24 | 23 | 22 | 21 | 20 | 19 | 18 | 17 | 16 | 15 | 14 | 13 | 12 | 11 | 10 | 9 | 8 | 7 | 6 | 5 | 4 | 3 | 2 | 1 | 0 |
|------------------------|--------------------------------------|------|-----------------|------|------|------|-----------------|------|------|------|-----------------|------|------|------|-------|--------|------|------|-------|--------|------|------|-----------------|-----|-----|-----|-------|--------|-----|-----|-------|--------|-----|
| | Re<br>set<br>value | 0 | 0 | 0 | 0 | 0 | 0 | 0 | 0 | 0 | 0 | 0 | 0 | 0 | 0 | 0 | 0 | 0 | 0 | 0 | 0 | 0 | 0 | 0 | 0 | 0 | 0 | 0 | 0 | 0 | 0 | 0 | 0 |
| 0<br>x<br>2 | GPIO<br>x_AF<br>RH<br>(x=A,<br>B, C) | | AFSEL7<br>[3:0] | | | | AFSEL6<br>[3:0] | | | | AFSEL5<br>[3:0] | | | | [3:0] | AFSEL4 | | | [3:0] | AFSEL3 | | | AFSEL2<br>[3:0] | | | | [3:0] | AFSEL1 | | | [3:0] | AFSEL0 | |
| 4 | Re<br>set<br>value | 0 | 0 | 0 | 0 | 0 | 0 | 0 | 0 | 0 | 0 | 0 | 0 | 0 | 0 | 0 | 0 | 0 | 0 | 0 | 0 | 0 | 0 | 0 | 0 | 0 | 0 | 0 | 0 | 0 | 0 | 0 | 0 |
| 0<br>x<br>2 | GPIO<br>x_BR<br>R<br>(x=A,<br>B, C) | Res. | Res. | Res. | Res. | Res. | Res. | Res. | Res. | Res. | Res. | Res. | Res. | Res. | Res. | Res. | Res. | BR15 | BR14 | BR13 | BR12 | BR11 | BR10 | BR9 | BR8 | BR7 | BR6 | BR5 | BR4 | BR3 | BR2 | BR1 | BR0 |
| 8 | Re<br>set<br>value | | | | | | | | | | | | | | | | | 0 | 0 | 0 | 0 | 0 | 0 | 0 | 0 | 0 | 0 | 0 | 0 | 0 | 0 | 0 | 0 |
## <span id="page-93-0"></span>**10. System configuration controller**
# **(SYSCFG)**
The devices feature a set of configuration registers. The main purpose of the system configuration controller are:
- Enable or disable I2C Fast Mode Plus on some IO pins
- Remap the memory located at the beginning of the code area
- Manage the external interrupts connected to GPIOs
- Manage robustness features
## <span id="page-93-1"></span>**10.1. System configuration register**
## <span id="page-93-2"></span>**10.1.1. SYSCFG configuration register 1 (SYSCFG\_CFGR1)**
This register is used for specific configuration of memory and control special I/O functions.
Two bits are used to configure the type of memory accessible at address 0x0000 0000. These two bits are used to select the physical remap by software, and bypass the hardware BOOT selection. After reset, these bits take the value configured by the actual boot mode.
#### **Address offset:**0x00
**Reset value:**0x0000 000x(x is the memory mode selected by the actual boot mode configuration)
| 31 | 30 | 29 | 28 | 27 | 26 | 25 | 24 | 23 | 22 | 21 | 20 | 19 | 18 | 17 | 16 |
|----|----|----|----|----|----|----|----|----|----|----|----|---------|---------|----------|---------|
| Re | Re | Re | Re | Re | Re | Re | Re | Re | Re | Re | Re | I2C_PB6 | I2C_PB4 | I2C_PB3 | I2C_PA2 |
| s | s | s | s | s | s | s | s | s | s | s | s | _ ANF | _ ANF | _ ANF | _ ANF |
| | | | | | | | | | | | | RW | RW | | |
| 15 | 14 | 13 | 12 | 11 | 10 | 9 | 8 | 7 | 6 | 5 | 4 | 3 | 2 | 1 | 0 |
| Re | Re | Re | Re | Re | Re | Re | Re | Re | Re | Re | Re | | | MEM_MODE | |
| s | s | s | s | s | s | s | s | s | s | s | s | Res | Res | [1:0] | |
| | | | | | | | | | | | | | | RW | |
| Bit | Name | R/W | Reset Value | Function |
|-------|-------------------|-----|-------------|--------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------|
| 31:20 | Reserved | RW | - | Read and write |
| | | | | I2C FM+ Mode drive capability activation bit. |
| 19 | I2C_PB6_FMP | RW | 0 | 0:The pin operates in standard mode. |
| | | | | 1:The pin enables in I2C FM+ mode |
| | | | | I2C FM+ Mode drive capability activation bit. |
| 18 | I2C_PB4_FMP | RW | 0 | 0:The pin operates in standard mode. |
| | | | | 1:The pin enables in I2C FM+ mode |
| | | | | I2C FM+ Mode drive capability activation bit. |
| 17 | I2C_PB3_FMP | RW | 0 | 0:The pin operates in standard mode. |
| | | | | 1:The pin enables in I2C FM+ mode |
| | I2C_PA2_FMP | RW | | I2C FM+ Mode drive capability activation bit. |
| 16 | | | 0 | 0:The pin operates in standard mode. |
| | | | | 1:The pin enables in I2C FM+ mode |
| 17:2 | Reserved | RW | 0 | Read and write |
| 1:0 | MEM_MODE<br>[1:0] | | | Memory mapping selection bit<br>Set and clear by software. They control the mapping of<br>memory at address 0x0000 0000. After reset, these bits<br>take on the actual boot mode configuration values. |
| | | | | X0:Main flash, mapped at 0x0000 0000 |
| | | | | 01:System flash , mapped at 0x0000 0000 |
| Bit | Name | R/W | Reset Value | Function |
|-----|------|-----|-------------|--------------------------------|
| | | | | 11:SRAM, mapped at 0x0000 0000 |
## <span id="page-94-0"></span>**10.1.2. SYSCFG configuration register 2 (SYSCFG\_CFGR2)**
#### **Address offset:**0x18
**Reset value:**0x0000
| 31 | 30 | 29 | 28 | 27 | 26 | 25 | 24 | 23 | 22 | 21 | 20 | 19 | 18 | 17 | 16 |
|----|----|----|----|----|----------|-----|----|----|----|----|-----------|-----------|----|----|------|
| Re | Re | Re | Re | Re | | | Re | Re | Re | Re | Res | Res | Re | Re | Res |
| s | s | s | s | s | Res | Res | s | s | s | s | | | s | s | |
| | | | | | | | | | | | | | | | |
| 15 | 14 | 13 | 12 | 11 | 10<br>9 | | 8 | 7 | 6 | 5 | 4 | 3 | 2 | 1 | 0 |
| | | | | | | | | | | | | | | | LOCK |
| Re | Re | Re | Re | Re | ETR_SRC_ | | Re | Re | Re | Re | COMP2_BRK | COMP1_BRK | Re | Re | UP |
| s | s | s | s | s | TIM1 | | s | s | s | s | _TIM1 | _TIM1 | s | s | _LOC |
| | | | | | | | | | | | | | | | K |
| | | | | | RW | | | | | | RW | RW | | | RW |
| Bit | Name | R/W | Reset Value | Function | | | | |
|-------|-----------------------|---------|-------------|-------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------|--|--|--|--|
| 31:11 | Reserved | - | - | - | | | | |
| 10:9 | ETR_SRC<br>_TIM1[1:0] | RW | 2'b00 | TIMER1 ETR input source selection<br>2'b00: ETR source from GPIO<br>2'b01: ETR source from COMP1<br>2'b10: ETR source from COMP2<br>2'b11: ETR source from ADC | | | | |
| 8:5 | Reserved | - | - | - | | | | |
| 4 | COMP2_BRK<br>_TIM1 | RW | 0 | COMP2 as TIMx break input enable。<br>0:COMP2 output is not used as TIM1 break input<br>1:COMP2 output as TIM1 break input | | | | |
| 3 | COMP1_BRK_<br>TIM1 | RW<br>0 | | COMP1 作为 TIMx break 输入使能。<br>0:COMP1 output is not used as TIM1 break input<br>1:COMP1 output as TIM1 break input | | | | |
| 2:1 | Reserved | - | - | - | | | | |
| 0 | LOCKUP_<br>LOCK | RW | | Cortex-M0+ LOCKUP enable bit<br>Set by software and cleared by system reset.it can enable<br>and lock the LOCKUP(hardfault) output of Cortex-M0+ to<br>the brake input of TIM1.<br>0:The LOCKUP output of Cortex-M0+ is not connected<br>to the brake input of TIM1.<br>1:The LOCKUP output of Cortex-M0+ is connected to<br>the brake input of TIM1. | | | | |
## <span id="page-94-1"></span>**10.1.3. GPIO filtering enable(GPIO\_ENS)**
#### **Address offset:**0x1C
| Reset value:0x0000_0000 | | | | |
|-------------------------|--|--|--|--|
| | | | | |
| 31 | 30 | 29 | 28 | 27 | 26 | 25 | 24 | 23 | 22 | 21 | 20 | 19 | 18 | 17 | 16 |
|--------|-----|-----|-----|-----|-----|-----|-----|-----|--------|-----|-----|-----|-----|----|--------|
| Res | Res | Res | Res | Res | Res | Res | Res | Res | Res | Res | Res | Res | Res | | PC_ENS |
| | | | | | | | | | | | | | | RW | RW |
| 15 | 14 | 13 | 12 | 11 | 10 | 9 | 8 | 7 | 6 | 5 | 4 | 3 | 2 | 1 | 0 |
| PB_ENS | | | | | | | | | PA_ENS | | | | | | |
| RW | RW | RW | RW | RW | RW | RW | RW | RW | RW | RW | RW | RW | RW | RW | RW |
| Bit | Name | R/W | Reset Value | Function |
|-------|-----------|-----|-------------|--------------------------------------------------------------|
| 31:18 | reserved | RES | - | reserved |
| 17:16 | PC_ENS[x] | RW | 0 | Noise filter enable, active high<br>0: noise filter bypassed |
| Bit | Name | R/W | Reset Value | Function |
|------|-----------|-----|-------------|-----------------------------------------------------------------------------------------|
| | | | | 1: noise filter enabled |
| 15:8 | PB_ENS[x] | RW | 0 | Noise filter enable, active high<br>0: noise filter bypassed<br>1: noise filter enabled |
| 7:0 | PA_ENS[x] | RW | 0 | Noise filter enable, active high<br>0: noise filter bypassed<br>1: noise filter enabled |
## <span id="page-95-0"></span>**10.1.4. SYSCFG register map**
| | 0x<br>1C | | 0x<br>18 | | 0x<br>00 | Of<br>fs<br>et |
|-------------------|------------------|------------------------|------------------------------|------------------------|------------------------------|----------------|
| Re<br>set<br>valu | GPI<br>O_E<br>NS | Re<br>set<br>valu<br>e | SYS<br>CFG<br>_<br>CFG<br>R2 | Re<br>set<br>valu<br>e | SYS<br>CFG<br>_<br>CFG<br>R1 | Reg<br>ister |
| | Res. | | Res. | | Res. | 31 |
| | Res. | | Res. | | Res. | 30 |
| | Res. | | Res. | | Res. | 29 |
| | Res. | | Res. | | Res. | 28 |
| | Res. | | Res. | | Res. | 27 |
| | Res. | | Res. | | Res. | 26 |
| | Res. | | Res. | | Res. | 25 |
| | Res. | | Res. | | Res. | 24 |
| | Res. | | Res. | | Res. | 23 |
| | Res. | | Res. | | Res. | 22 |
| | Res. | | Res. | | Res. | 21 |
| | Res. | | Res. | | Res. | 20 |
| | Res. | | Res. | | I2C_PB6_FMP | 19 |
| | Res. | | Res. | | I2C_PB4_FMP | 18 |
| 0 | PC_ENS | | Res. | | I2C_PB3_FMP | 17 |
| 0 | | | Res. | | I2C_PA2_FMP | 16 |
| | | | Res. | | Res. | 15 |
| | | | Res. | | Res. | 14 |
| 0 | | | Res. | | Res. | 13 |
| 0 | | | Res. | | Res. | 12 |
| 0 | PB_ENS | | Res. | | Res. | 11 |
| 0 | | 0 | ETR_SRC_TIM1[1:0] | | Res. | 10 |
| 0 | | 0 | | | Res. | 9 |
| 0 | | | Res. | | Res. | 8 |
| | | | Res. | | Res. | 7 |
| | | | Res. | | Res. | 6 |
| 0 | | | Res. | | Res. | 5 |
| 0 | PA_ENS | 0 | COMP2_BRK_TIM21 | | Res. | 4 |
| 0 | | 0 | COMP2_BRK_TIM22 | | Res. | 3 |
| 0 | | 0 | COMP2_BRK_TIM23 | | Res. | 2 |
| 0 | | | Res. | X | MEM_MODE[1:0] | 1 |
| 0 | | 0 | LOCKUP_LOCK | X | | 0 |
## <span id="page-96-0"></span>**11. Interrupts and events**
## <span id="page-96-1"></span>**11.1. Nested vectored interrupt controller (NVIC)**
## **11.1.1. NVIC main features**
- <span id="page-96-2"></span>32 maskable interrupt channels (not including the 16 CPUs interrupt lines)
- 4 programmable priority levels (2 bits of interrupt priority are used)
- Low-latency exception and interrupt handling
- Power management control
- Implementation of System Control Registers
The NVIC and the interface of CPU are closely coupled, which enables low latency interrupt processing and efficient processing of late arriving interrupts. All interrupts including the CPU exceptions are managed by the NVIC.
## <span id="page-96-3"></span>**11.1.2. SysTick calibration value register**
The SysTick calibration value is set to 6000, which gives a reference time base of 1 ms with the SysTick clock set to 6 MHz (max fHCLK/8).
| Posi<br>tion | Prior<br>ity | Type of<br>priority | Acronym | Description | Address |
|--------------|--------------|---------------------|-------------------------|------------------------------------------------------------------------------------------------|-------------|
| - | - | - | - | Reserved | 0x0000_0000 |
| - | -3 | fixed | Reset | Reset | 0x0000_0004 |
| - | -2 | fixed | NMI_Handler | Non maskable interrupt.<br>The RCC Clock Security System (CSS)<br>is linked to the NMI vector. | 0x0000_0008 |
| - | -1 | fixed | HardFualt_Handler | All class of fault | 0x0000_000C |
| - | 3 | settable | SVCall | System service call via SWI instruction | 0x0000_002C |
| - | 5 | settable | PendSV | Pendable request for system service | 0x0000_0038 |
| | 6 | | SysTick | System tick timer | 0x0000_003C |
| 0 | 7 | - | Reserved | Reserved | 0x0000_0040 |
| 1 | 8 | - | Reserved | Reserved | 0x0000_0044 |
| 2 | 9 | - | Reserved | Reserved | 0x0000_0048 |
| 3 | 10 | settable | Flash | Flash global interrupt | 0x0000_004C |
| 4 | 11 | settable | RCC | RCC global interrupt | 0x0000_0050 |
| 5 | 12 | settable | EXTI0_1 | EXTI line[1:0] interrupt | 0x0000_0054 |
| 6 | 13 | settable | EXTI2_3 | EXTI line[3:2] interrupt | 0x0000_0058 |
| 7 | 14 | settable | EXTI4_15 | EXTI line[15:4] interrupt | 0x0000_005C |
| 8 | 15 | - | Reserved | Reserved | 0x0000_0060 |
| 9 | 16 | - | Reserved | Reserved | 0x0000_0064 |
| 10 | 17 | - | Reserved | Reserved | 0x0000_0068 |
| 11 | 18 | - | Reserved | Reserved | 0x0000_006C |
| 12 | 19 | settable | ADC_COMP | ADC and COMP interrupts (COMP<br>combined with EXTI 17 & 18) | 0x0000_0070 |
| 13 | 20 | settable | TIM1_BRK_UP_TRG<br>_COM | TIM1 break、update、tigger and com<br>mutation interrupt | 0x0000_0074 |
| 14 | 21 | settable | TIM1_CC | TIM1 capture/compare interrupt | 0x0000_0078 |
| 15 | 22 | - | Reserved | Reserved | 0x0000_007C |
| 16 | 23 | - | Reserved | Reserved | 0x0000_0080 |
| 17 | 24 | settable | LPTIM1 | LPTIM interrupt | 0x0000_0084 |
| 18 | 25 | - | Reserved | Reserved | 0x0000_0088 |
| 19 | 26 | settable | TIM14 | TIM14 global interrupt | 0x0000_008C |
| 20 | 27 | - | Reserved | Reserved | 0x0000_0090 |
## <span id="page-96-4"></span>**11.1.3. Interrupt and exception vectors**
| Posi<br>tion | Prior<br>ity | Type of<br>priority | Acronym | Description | Address |
|--------------|--------------|---------------------|----------|-------------------------|-------------|
| 21 | 28 | - | Reserved | Reserved | 0x0000_0094 |
| 22 | 29 | - | Reserved | Reserved | 0x0000_0098 |
| 23 | 30 | settable | I2C1 | I2C1 global interrupt | 0x0000_009C |
| 24 | 31 | - | Reserved | Reserved | 0x0000_00A0 |
| 25 | 32 | settable | SPI1 | SPI1 global interrupt | 0x0000_00A4 |
| 26 | 33 | - | Reserved | Reserved | 0x0000_00A8 |
| 27 | 34 | settable | USART1 | USART1 global interrupt | 0x0000_00AC |
| 28 | 35 | settable | Reserved | Reserved | 0x0000_00B0 |
| 29 | 36 | - | Reserved | Reserved | 0x0000_00B4 |
| 30 | 37 | - | Reserved | Reserved | 0x0000_00B8 |
| 31 | 38 | - | Reserved | Reserved | 0x0000_00BC |
1. The grayed cells(the address less than 0x0000 0040) correspond to the Cortex®-M0+ interrupts.
## <span id="page-97-0"></span>**11.2. Extended interrupts and events controller (EXTI)**
The extended interrupt and event controller, through configurable (configurable) and direct (direct event) input (Lines), manages the CPU and system wake-up functions, and outputs the following request signals:
- Interrupt request, sent to the int\_ctrl module to generate the IRQ of the CPU
- Event request, event input to CPU (RXEV)
- Wake-up request, sent to power management control module
EXTI wakeup request allows the system to wake up from stop mode, interrupt request and event request can also be used in run mode.
EXTI allows to manage up to 21 configurable/direct event lines (19 configurable event lines and 2 direct event lines).
#### <span id="page-97-1"></span>**11.2.1. EXTI main features**
- The system can wake up through GPIO and specified module (COMP/LPTIM) input events
- Configurable events (from I/O, or peripherals with no state pending bits, peripherals that generate pulses)
- Optional valid trigger edge (rising edge/falling edge)
- Interrupt pending flag
- Independent interrupt and event generation mask bit
- Triggered by software
- Direct events (peripherals with associated flags and interrupt pending status bits)
- Fixed rising edge trigger
- No interrupt pending bit in EXTI module
- Independent interrupt and event generation mask bit
- No software trigger
- IO port selection
#### <span id="page-97-2"></span>**11.2.2. EXTI diagram**
![](_page_98_Figure_1.jpeg)
Figure 11-1 EXTI diagram
## <span id="page-98-0"></span>**11.2.3. EXTI connection between peripherals and CPU**
A peripheral that can generate a wake-up or interrupt event signal in stop mode is connected to the EXTI module.
- A wake-up signal that generates a pulse, or has no interrupt status bits inside the peripheral, is connected to the configurable line of the EXTI module. At this time, the EXTI module generates an interrupt pending bit (this bit needs to be cleared), and the EXTI interrupt will be used as the interrupt signal of the CPU.
- The interrupt and wake-up signal of the peripheral with the associated status bit (the bit is cleared in the peripheral) is connected to the wake-up trigger signal line of the EXTI module.
- All GPIO ports are input to the EXTI MUX module, and can be selected as a system wake-up signal through configurable configuration.
## <span id="page-98-1"></span>**11.2.4. EXTI configurable event trigger wake-up**
By configuring the EXTI\_SWIER1 register, software can trigger the wake-up function.
There is a corresponding register configuration that triggers a rising edge or falling edge or a double edge to trigger a configurable type event. The hardware detects the input signal of the configurable type event according to the configuration, and generates a corresponding wake-up event or interrupt signal.
The CPU has dedicated interrupt mask registers and event mask registers. The event generated to the CPU after the event is enabled. The only event input signal rxev that is output to the CPU after all events to the CPU are 'OR'ed.
Configurable type events have a unique interrupt pending request register, which is shared with the CPU. The pending register is only set when the CPU Interrupt Mask Register (EXTI\_IMR) is configured as unmasked. Each configurable type event corresponds to a CPU external interrupt signal (some will be multiplexed to the same CPU external interrupt signal). Configurable type event interrupt requires the CPU to confirm through the EXTI\_PR register (write 1 to clear).
Note: When a bit of the interrupt pending register (EXTI\_PR) remains valid (not cleared), the system cannot enter the low power consumption mode.
### <span id="page-99-0"></span>**11.2.5. EXTI direct type event input wakeup**
The direct type event will generate an interrupt in the EXTI module, and will generate an event signal to wake up the system and the CPU subsystem. When the CPU processes the interrupt generated by this type of trigger event, it needs to clear the interrupt status bit of the peripheral module.
#### <span id="page-99-1"></span>**11.2.6. EXTI selector**
The GPIOs are connected to the 8 external interrupt/event lines in the following manner:
![](_page_99_Figure_7.jpeg)
Figure 11-2 External interrupt/event GPIO mapping
The remaining lines are connected as follows:
| EXTI line | Line source | Line type |
|-----------|---------------|--------------|
| Line 0-15 | GPIO | configurable |
| Line 16 | Reserved | |
| Line 17 | COMP 1 output | Configurable |
| Line 18 | COMP 2 output | Configurable |
| Line 19 | Reserved | |
| EXTI line | Line source | Line type |
|-----------|-------------|-----------|
| Line 20 | Reserved | |
| Line 21 | Reserved | |
| Line 22 | Reserved | |
| Line 23 | Reserved | |
| Line 24 | Reserved | |
| Line 25 | Reserved | |
| Line 26 | Reserved | |
| Line 27 | Reserved | |
| Line 28 | Reserved | |
| Line 29 | LPTIM | Direct |
| | | |
## <span id="page-100-0"></span>**11.3. EXTI registers**
The registers of this peripheral can be accessed with word (32bit), half-word (16bit) and byte (8bit).
## <span id="page-100-1"></span>**11.3.1. Rising trigger selection register (EXTI\_RTSR)**
#### **Address offset:** 0x00
**Reset value:** 0x0000 0000
Contains only register control bits for configurable events.
| 31 | 30 | 29 | 28 | 27 | 26 | 25 | 24 | 23 | 22 | 21 | 20 | 19 | 18 | 17 | 16 |
|-----|-----|-----|-----|-----|-----|-----|-----|-----|-----|-----|-----|-----|------|------|-----|
| Res | Res | Res | Res | Res | Res | Res | Res | Res | Res | Res | Res | Res | RT18 | RT17 | Res |
| | | | | | | | | | | | | | RW | RW | |
| | | | | | | | | | | | | | | | |
| 15 | 14 | 13 | 12 | 11 | 10 | 9 | 8 | 7 | 6 | 5 | 4 | 3 | 2 | 1 | 0 |
| Res | Res | Res | Res | Res | Res | Res | Res | RT7 | RT6 | RT5 | RT4 | RT3 | RT2 | RT1 | RT0 |
| Bit | Name | R/W | Reset Value | Function |
|-------|----------|-----|-------------|------------------------------------------------------------------|
| 31:19 | Reserved | | | |
| | | | | Configurable type EXTI line18 rising edge trigger configuration. |
| 18 | RT18 | RW | 0 | 0:Disable |
| | | | | 1:Enable |
| | | | | Configurable type EXTI line17 rising edge trigger configuration. |
| 17 | RT17 | RW | 0 | 0:Disable |
| | | | | 1:Enable |
| 16:8 | Reserved | | | |
| | | | | Configurable type EXTI line7 rising edge trigger configuration. |
| 7 | RT7 | RW | 0 | 0:Disable |
| | | | | 1:Enable |
| | | | | Configurable type EXTI line6 rising edge trigger configuration. |
| 6 | RT6 | RW | 0 | 0:Disable |
| | | | | 1:Enable |
| | | | | Configurable type EXTI line5 rising edge trigger configuration. |
| 5 | RT5 | RW | 0 | 0:Disable |
| | | | | 1:Enable |
| | | | | Configurable type EXTI line4 rising edge trigger configuration. |
| 4 | RT4 | RW | 0 | 0:Disable |
| | | | | 1:Enable |
| | | | | Configurable type EXTI line3 rising edge trigger configuration. |
| | | | | 0:Disable |
| 3 | RT3 | RW | 0 | |
| | | | | 1:Enable |
| | | | | Configurable type EXTI line2 rising edge trigger configuration. |
| 2 | RT2 | RW | 0 | 0:Disable |
| | | | | 1:Enable |
| 1 | RT1 | RW | 0 | Configurable type EXTI line1 rising edge trigger configuration. |
| | | | | 0:Disable |
| Bit | Name | R/W | Reset Value | Function |
|-----|------|-----|-------------|------------------------------------------------------------------------------------------|
| | | | | 1:Enable |
| 0 | RT0 | RW | 0 | Configurable type EXTI line0 rising edge trigger configuration.<br>0:Disable<br>1:Enable |
Configurable lines are edge-triggered, and glitches cannot be generated on these lines. If a rising edge occurs on the configurable interrupt line during a write to the EXTI\_RTSR register, the associated Pending bit is not set.
Rising and falling edges can be set on the same line, in which case both edges will generate a trigger condition.
## <span id="page-101-0"></span>**11.3.2. Falling trigger selection register (EXTI\_FTSR)**
#### **Address offset:** 0x04
| | | Contains only register control bits for configurable | | |
|--|--|------------------------------------------------------|--|--|
| | | | | |
| 31 | 30 | 29 | 28 | 27 | 26 | 25 | 24 | 23 | 22 | 21 | 20 | 19 | 18 | 17 | 16 |
|-----|-----|-----|-----|-----|-----|-----|-----|-----|-----|-----|-----|-----|------|------|-----|
| Res | Res | Res | Res | Res | Res | Res | Res | Res | Res | Res | Res | Res | FT18 | FT17 | Res |
| | | | | | | | | | | | | | RW | RW | RW |
| | | | | | | | | | | | | | | | |
| 15 | 14 | 13 | 12 | 11 | 10 | 9 | 8 | 7 | 6 | 5 | 4 | 3 | 2 | 1 | 0 |
| Res | Res | Res | Res | Res | Res | Res | Res | FT7 | FT6 | FT5 | FT4 | FT3 | FT2 | FT1 | FT0 |
| Bit | Name | R/W | Reset Value | Function |
|-------|----------|-----|-------------|--------------------------------------------------------------------------------|
| 31:19 | Reserved | | - | |
| 18 | FT18 | RW | 0 | Configurable type EXTI line18 falling edge trigger configuration.<br>0:Disable |
| | | | | 1:Enable |
| | | | | Configurable type EXTI line17 falling edge trigger configuration. |
| 17 | FT17 | RW | 0 | 0:Disable |
| | | | | 1:Enable |
| 16:8 | Reserved | | | |
| | | | | Configurable type EXTI line7 falling edge trigger configuration. |
| 7 | FT7 | RW | 0 | 0:Disable |
| | | | | 1:Enable |
| | | | | Configurable type EXTI line6 falling edge trigger configuration. |
| 6 | FT6 | RW | 0 | 0:Disable |
| | | | | 1:Enable |
| | | | | Configurable type EXTI line5 falling edge trigger configuration. |
| 5 | FT5 | RW | 0 | 0:Disable |
| | | | | 1:Enable |
| | | | | Configurable type EXTI line4 falling edge trigger configuration. |
| 4 | FT4 | RW | 0 | 0:Disable |
| | | | | 1:Enable |
| | | | | Configurable type EXTI line3 falling edge trigger configuration. |
| 3 | FT3 | RW | 0 | 0:Disable |
| | | | | 1:Enable |
| | | | | Configurable type EXTI line2 falling edge trigger configuration. |
| 2 | FT2 | RW | 0 | 0:Disable |
| | | | | 1:Enable |
| Bit | Name | R/W | Reset Value | Function |
|-----|------|-----|-------------|------------------------------------------------------------------|
| | | | | Configurable type EXTI line1 falling edge trigger configuration. |
| 1 | FT1 | RW | 0 | 0:Disable |
| | | | | 1:Enable |
| | | | | Configurable type EXTI line0 falling edge trigger configuration. |
| 0 | FT0 | RW | 0 | 0:Disable |
| | | | | 1:Enable |
Note: The external wakeup lines are edge triggered. No glitches must be generated on these lines. If a falling edge on an external interrupt line occurs during a write operation to the EXTI\_FTSR register, the pending bit is not set.
Rising and falling edges can be set on the same line, in which case both edges will generate a trigger condition.
## <span id="page-102-0"></span>**11.3.3. Software interrupt event register (EXTI\_SWIER)**
#### **Address offset:** 0x08
| 31 | 30 | 29 | 28 | 27 | 26 | 25 | 24 | 23 | 22 | 21 | 20 | 19 | 18 | 17 | 16 |
|-----|-----|-----|-----|-----|-----|-----|-----|-----|-----|-----|-----|-----|------|------|-----|
| Res | Res | Res | Res | Res | Res | Res | Res | Res | Res | Res | Res | Res | SW18 | SW17 | Res |
| | | | | | | | | | | | | | RW | RW | |
| | | | | | | | | | | | | | | | |
| 15 | 14 | 13 | 12 | 11 | 10 | 9 | 8 | 7 | 6 | 5 | 4 | 3 | 2 | 1 | 0 |
| Res | Res | Res | Res | Res | Res | Res | Res | SW7 | SW6 | SW5 | SW4 | SW3 | SW2 | SW1 | SW0 |
| Bit | Name | R/W | Reset Value | Function |
|-------|----------|-----|-------------|-------------------------------------------------------------------------------------------------------------------------------------------------------|
| 31:19 | Reserved | | - | |
| | | | | Configurable type EXTI line18 software rising edge trigger con<br>figuration.<br>0:No effect |
| 18 | SWI18 | RW | 0 | 1:Generate a rising edge trigger event, which in turn generates<br>an interrupt |
| | | | | This bit is cleared by hardware, and a read returns 0 (after hard<br>ware clearing) or configuration value (before hardware clearing) |
| | | RW | 0 | Configurable type EXTI line17 software rising edge trigger con<br>figuration. |
| | | | | 0:No effect |
| 17 | SWI17 | | | 1:Generate a rising edge trigger event, which in turn generates |
| | | | | an interrupt |
| | | | | This bit is cleared by hardware, and a read returns 0 (after hard<br>ware clearing) or configuration value (before hardware clearing) |
| 16:8 | Reserved | | | |
| | | | | Configurable type EXTI line7 software rising edge trigger config<br>uration. |
| | SWI7 | RW | 0 | 0:No effect |
| 7 | | | | 1:Generate a rising edge trigger event, which in turn generates |
| | | | | an interrupt<br>This bit is cleared by hardware, and a read returns 0 (after hard<br>ware clearing) or configuration value (before hardware clearing) |
| | SWI6 | RW | 0 | Configurable type EXTI line6 software rising edge trigger config<br>uration. |
| 6 | | | | 0:No effect |
| | | | | 1:Generate a rising edge trigger event, which in turn generates<br>an interrupt |
| Bit | Name | R/W | Reset Value | Function |
|-----|------|-----|-------------|-----------------------------------------------------------------------------------------------------------------------------------------------------------------|
| | | | | This bit is cleared by hardware, and a read returns 0 (after hard |
| | SWI5 | RW | 0 | ware clearing) or configuration value (before hardware clearing)<br>Configurable type EXTI line5 software rising edge trigger config<br>uration.<br>0:No effect |
| 5 | | | | 1:Generate a rising edge trigger event, which in turn generates |
| | | | | an interrupt<br>This bit is cleared by hardware, and a read returns 0 (after hard<br>ware clearing) or configuration value (before hardware clearing) |
| | | | | Configurable type EXTI line4 software rising edge trigger config<br>uration. |
| | | | | 0:No effect |
| 4 | SWI4 | RW | 0 | 1:Generate a rising edge trigger event, which in turn generates |
| | | | | an interrupt<br>This bit is cleared by hardware, and a read returns 0 (after hard<br>ware clearing) or configuration value (before hardware clearing) |
| | | RW | 0 | Configurable type EXTI line3 software rising edge trigger config<br>uration. |
| | SWI3 | | | 0:No effect |
| 3 | | | | 1:Generate a rising edge trigger event, which in turn generates |
| | | | | an interrupt<br>This bit is cleared by hardware, and a read returns 0 (after hard<br>ware clearing) or configuration value (before hardware clearing) |
| | | | | Configurable type EXTI line2 software rising edge trigger config<br>uration. |
| | | | | 0:No effect |
| 2 | SWI2 | RW | 0 | 1:Generate a rising edge trigger event, which in turn generates |
| | | | | an interrupt<br>This bit is cleared by hardware, and a read returns 0 (after hard |
| | | | | ware clearing) or configuration value (before hardware clearing) |
| | | | | Configurable type EXTI line1 software rising edge trigger config<br>uration. |
| | SWI1 | RW | 0 | 0:No effect |
| 1 | | | | 1:Generate a rising edge trigger event, which in turn generates |
| | | | | an interrupt<br>This bit is cleared by hardware, and a read returns 0 (after hard<br>ware clearing) or configuration value (before hardware clearing) |
| | SWI0 | RW | 0 | Configurable type EXTI line0 software rising edge trigger config<br>uration. |
| | | | | 0:No effect |
| 0 | | | | 1:Generate a rising edge trigger event, which in turn generates |
| | | | | an interrupt<br>This bit is cleared by hardware, and a read returns 0 (after hard<br>ware clearing) or configuration value (before hardware clearing) |
## <span id="page-103-0"></span>**11.3.4. Pending register (EXTI\_PR)**
#### **Address offset:** 0x0C
**Reset value:** 0x0000 0000
Contains only register control bits for configurable events.
| 31 | 30 | 29 | 28 | 27 | 26 | 25 | 24 | 23 | 22 | 21 | 20 | 19 | 18 | 17 | 16 |
|----|----|----|----|----|----|----|----|------|------|------|------|------|------|------|------|
| Re | Re | Re | Re | Re | Re | Re | Re | Res | Res | Res | Res | Res | PR18 | PR17 | Res |
| s | s | s | s | s | s | s | s | | | | | | | | |
| | | | | | | | | | | | | | rc_w | rc_w | |
| | | | | | | | | | | | | | 1 | 1 | |
| 15 | 14 | 13 | 12 | 11 | 10 | 9 | | | | | | | | | |
| | | | | | | | 8 | 7 | 6 | 5 | 4 | 3 | 2 | 1 | 0 |
| Re | Re | Re | Re | Re | Re | Re | Re | | | | | | | | |
| s | s | s | s | s | s | s | s | PR7 | PR6 | PR5 | PR4 | PR3 | PR2 | PR1 | PR0 |
| | | | | | | | | rc_w | rc_w | rc_w | rc_w | rc_w | rc_w | rc_w | rc_w |
| Bit | Name | R/W | Reset Value | Function |
|-------|----------|----------|-------------|--------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------|
| 31:19 | Reserved | reserved | - | |
| 18 | PR18 | RC_W1 | 0 | Configurable type EXTI line18 event pending flag.<br>This bit is set when software or hardware gener<br>ates a rising/falling edge trigger event. Software<br>writes 1 to clear.<br>0:no event request is generated.<br>1:Generate rising edge/falling edge/software |
| 17 | PR17 | RC_W1 | 0 | trigger event request.<br>Configurable type EXTI line17 event pending flag.<br>This bit is set when software or hardware gener<br>ates a rising/falling edge trigger event. Software<br>writes 1 to clear.<br>0:no event request is generated.<br>1:Generate rising edge/falling edge/software<br>trigger event request. |
| 16:8 | Reserved | | | |
| 7 | PR7 | RC_W1 | 0 | Configurable type EXTI line7 event pending flag.<br>This bit is set when software or hardware gener<br>ates a rising/falling edge trigger event. Software<br>writes 1 to clear.<br>0:no event request is generated.<br>1:Generate rising edge/falling edge/software<br>trigger event request. |
| 6 | PR6 | RC_W1 | 0 | Configurable type EXTI line6 event pending flag.<br>This bit is set when software or hardware gener<br>ates a rising/falling edge trigger event. Software<br>writes 1 to clear.<br>0:no event request is generated.<br>1:Generate rising edge/falling edge/software<br>trigger event request. |
| 5 | PR5 | RC_W1 | 0 | Configurable type EXTI line5 event pending flag.<br>This bit is set when software or hardware gener<br>ates a rising/falling edge trigger event. Software<br>writes 1 to clear.<br>0:no event request is generated.<br>1:Generate rising edge/falling edge/software<br>trigger event request. |
| 4 | PR4 | RC_W1 | 0 | Configurable type EXTI line4 event pending flag.<br>This bit is set when software or hardware gener<br>ates a rising/falling edge trigger event. Software<br>writes 1 to clear.<br>0:no event request is generated.<br>1:Generate rising edge/falling edge/software<br>trigger event request. |
| 3 | PR3 | RC_W1 | 0 | Configurable type EXTI line3 event pending flag.<br>This bit is set when software or hardware gener<br>ates a rising/falling edge trigger event. Software<br>writes 1 to clear.<br>0:no event request is generated.<br>1:Generate rising edge/falling edge/software<br>trigger event request. |
| 2 | PR2 | RC_W1 | 0 | Configurable type EXTI line2 event pending flag.<br>This bit is set when software or hardware gener<br>ates a rising/falling edge trigger event. Software<br>writes 1 to clear.<br>0:no event request is generated.<br>1:Generate rising edge/falling edge/software<br>trigger event request. |
| Bit | Name | R/W | Reset Value | Function |
|-----|------|-------|-------------|---------------------------------------------------------------------------------------------------------------------------------------------------------------------------------|
| 1 | PR1 | RC_W1 | 0 | Configurable type EXTI line1 event pending flag.<br>This bit is set when software or hardware gener<br>ates a rising/falling edge trigger event. Software<br>writes 1 to clear. |
| | | | | 0:no event request is generated. |
| | | | | 1:Generate rising edge/falling edge/software |
| | | | | trigger event request. |
| | PR0 | RC_W1 | 0 | Configurable type EXTI line0 event pending flag.<br>This bit is set when software or hardware gener<br>ates a rising/falling edge trigger event. Software<br>writes 1 to clear. |
| 0 | | | | 0:no event request is generated. |
| | | | | 1:Generate rising edge/falling edge/software<br>trigger event request. |
## <span id="page-105-0"></span>**11.3.5. External interrupt select register 1 (EXTI\_EXTICR1)**
#### **Address offset:**0x60
**Reset value:**0x0000
| 31 | 30 | 29 | 28 | 27 | 26 | 25 | 24 | 23 | 22 | 21 | 20 | 19 | 18 | 17 | 16 |
|-----|-----|-----|-----|-----|-----|----|------------|-----|-----|-----|-----|-----|-----|----|------------|
| Res | Res | Res | Res | Res | Res | | EXTI3[1:0] | Res | Res | Res | Res | Res | Res | | EXTI2[1:0] |
| | | | | | | RW | RW | | | | | | | RW | RW |
| | | | | | | | | | | | | | | | |
| 15 | 14 | 13 | 12 | 11 | 10 | 9 | 8 | 7 | 6 | 5 | 4 | 3 | 2 | 1 | 0 |
| Res | Res | Res | Res | Res | Res | | EXTI1[1:0] | Res | Res | Res | Res | Res | Res | | EXTI0[1:0] |
| Bit | Name | R/W | Reset Value | Function |
|-------|------------|-----|-------------|--------------------------------------------------------------------------------------------------------------------------|
| 31:21 | Reserved | - | - | Reserved |
| 25:24 | EXTI3[1:0] | RW | 0 | EXTI3 corresponds to GPIO port selection.<br>2'b00: PA[3] pin<br>2'b01: PB[3] pin<br>2'b11: reserved |
| 23:18 | Reserved | - | - | Reserved |
| 17:16 | EXTI2[1:0] | RW | 0 | EXTI2 corresponds to GPIO port selection.<br>2'b00: PA[2] pin<br>2'b01: PB[2] pin<br>2'b11: reserved |
| 15:10 | Reserved | - | - | Reserved |
| 9:8 | EXTI1[1:0] | RW | 0 | EXTI1 corresponds to GPIO port selection.<br>2'b00: PA[1] pin<br>2'b01: PB[1] pin<br>2'b10: PC[1] pin<br>2'b11: reserved |
| 7:2 | Reserved | - | - | Reserved |
| 1:0 | EXTI0[1:0] | RW | 0 | EXTI0 corresponds to GPIO port selection.<br>2'b00: PA[0] pin<br>2'b01: PB[0] pin<br>2'b10: PC[0] pin<br>2'b11: reserved |
## <span id="page-105-1"></span>**11.3.6. External interrupt select register 2 (EXTI\_EXTICR2)**
#### **Address offset:**0x64
| 31 | 30 | 29 | 28 | 27 | 26 | 25 | 24 | 23 | 22 | 21 | 20 | 19 | 18 | 17 | 16 |
|-----|-----|-----|-----|-----|-----|-----|-------|-----|-----|-----|-----|-----|-----|-----|------------|
| Res | Res | Res | Res | Res | Res | Res | EXTI7 | Res | Res | Res | Res | Res | Res | Res | EXTI6 |
| | | | | | | | RW | | | | | | | | RW |
| 15 | 14 | 13 | 12 | 11 | 10 | 9 | 8 | 7 | 6 | 5 | 4 | 3 | 2 | 1 | 0 |
| Res | Res | Res | Res | Res | Res | RW | EXTI5 | Res | Res | Res | Res | Res | Res | | EXTI4[1:0] |
| | | | | | | | RW | | | | | | | RW | RW |
| Bit | Name | R/W | Reset Value | Function |
|-------|------------|-----|-------------|------------------------------------------------------------------------------------------------------|
| 31:25 | Reserved | - | - | Reserved |
| 24 | EXTI7 | RW | 0 | EXTI7 corresponds to GPIO port selection.<br>0: PA[7] pin<br>1: PB[7] pin |
| 23:18 | Reserved | - | - | Reserved |
| 17:16 | EXTI6 | RW | 0 | EXTI6 corresponds to GPIO port selection.<br>0: PA[6] pin<br>1: PB[6] pin |
| 15:9 | Reserved | - | - | Reserved |
| 8 | EXTI5 | RW | 0 | EXTI5 corresponds to GPIO port selection.<br>0: PA[5] pin<br>1: PB[5] pin |
| 7:2 | Reserved | - | - | Reserved |
| 1:0 | EXTI4[1:0] | RW | 0 | EXTI4 corresponds to GPIO port selection.<br>2'b00: PA[4] pin<br>2'b01: PB[4] pin<br>2'b11: reserved |
## <span id="page-106-0"></span>**11.3.7. Interrupt mask register (EXTI\_IMR)**
#### **Address offset:**0x80
#### **Reset value:**0x2000 0000
Note: The interrupt mask bit of the Direct type line is 1 by default, that is, the line is not masked,
the mask bit of the configurable line, the default is 0, that is, the line is masked.
| 31 | 30 | 29 | 28 | 27 | 26 | 25 | 24 | 23 | 22 | 21 | 20 | 19 | 18 | 17 | 16 |
|-----|-----|------|-----|-----|-----|-----|-----|-----|-----|-----|-----|-----|------|------|-----|
| Res | Res | IM29 | Res | Res | Res | Res | Res | Res | Res | Res | Res | Res | IM18 | IM17 | Res |
| | | RW | | | | | | | | | | | RW | RW | |
| 15 | 14 | 13 | 12 | 11 | 10 | 9 | 8 | 7 | 6 | 5 | 4 | 3 | 2 | 1 | 0 |
| | Res | Res | Res | Res | | | | | | | | | | | |
| Res | | | | | Res | Res | Res | IM7 | IM6 | IM5 | IM4 | IM3 | IM2 | IM1 | IM0 |
| Bit | Name | R/W | Reset Value | Function |
|-------|----------|-----|-------------|-------------------------------------------------------------------------|
| 31:30 | Reserved | | | |
| | | | | EXTI line29 is used as an interrupt to wake up the<br>CPU mask control. |
| 29 | IM29 | RW | 1 | 0:interrupt wake-up mask |
| | | | | 1:Interrupt wake-up is not masked |
| 28:19 | Reserved | | | |
| | | | | EXTI line18 is used as an interrupt to wake up<br>the CPU mask control. |
| 18 | IM18 | RW | 0 | 0:interrupt wake-up mask |
| | | | | 1:Interrupt wake-up is not masked |
| | | | | EXTI line17 is used as an interrupt to wake up<br>the CPU mask control. |
| 17 | IM17 | RW | 0 | 0:interrupt wake-up mask |
| | | | | 1:Interrupt wake-up is not masked |
| 16:8 | Reserved | | | |
| | | | | EXTI line7 is used as an interrupt to wake up the<br>CPU mask control. |
| 7 | IM7 | RW | 0 | 0:interrupt wake-up mask |
| | | | | 1:Interrupt wake-up is not masked |
| | | | | EXTI line6 is used as an interrupt to wake up the<br>CPU mask control. |
| 6 | IM6 | RW | 0 | 0:interrupt wake-up mask |
| | | | | 1:Interrupt wake-up is not masked |
| 5 | IM5 | RW | 0 | EXTI line5 is used as an interrupt to wake up the<br>CPU mask control. |
| | | | | 0:interrupt wake-up mask |
| Bit | Name | R/W | Reset Value | Function |
|-----|------|-----|-------------|------------------------------------------------------------------------|
| | | | | 1:Interrupt wake-up is not masked |
| | | | | EXTI line4 is used as an interrupt to wake up the<br>CPU mask control. |
| 4 | IM4 | RW | 0 | 0:interrupt wake-up mask |
| | | | | 1:Interrupt wake-up is not masked |
| | | | | EXTI line3 is used as an interrupt to wake up the<br>CPU mask control. |
| 3 | IM3 | RW | 0 | 0:interrupt wake-up mask |
| | | | | 1:Interrupt wake-up is not masked |
| | | | | EXTI line2 is used as an interrupt to wake up the<br>CPU mask control. |
| 2 | IM2 | RW | 0 | 0:interrupt wake-up mask |
| | | | | 1:Interrupt wake-up is not masked |
| | | | | EXTI line1 is used as an interrupt to wake up the<br>CPU mask control. |
| 1 | IM1 | RW | 0 | 0:interrupt wake-up mask |
| | | | | 1:Interrupt wake-up is not masked |
| | | | | EXTI line0 is used as an interrupt to wake up the<br>CPU mask control. |
| 0 | IM0 | RW | 0 | 0:interrupt wake-up mask |
| | | | | 1:Interrupt wake-up is not masked |
## <span id="page-107-0"></span>**11.3.8. Event mask register (EXTI\_EMR)**
#### **Address offset:** 0x84
| 31 | 30 | 29 | 28 | 27 | 26 | 25 | 24 | 23 | 22 | 21 | 20 | 19 | 18 | 17 | 16 |
|-----|-----|------|-----|-----|-----|-----|-----|-----|-----|-----|-----|-----|------|------|-----|
| Res | Res | EM29 | Res | Res | Res | Res | Res | Res | Res | Res | Res | Res | EM18 | EM17 | Res |
| | | RW | | | | | | | | | | | RW | RW | |
| | | | | | | | | | | | | | | | |
| 15 | 14 | 13 | 12 | 11 | 10 | 9 | 8 | 7 | 6 | 5 | 4 | 3 | 2 | 1 | 0 |
| Res | Res | Res | Res | Res | Res | Res | Res | EM7 | EM6 | EM5 | EM4 | EM3 | EM2 | EM1 | EM0 |
| Bit | Name | R/W | Reset Value | Function |
|-------|----------|-----|-------------|-----------------------------------------------------------------------------------|
| 31:30 | Reserved | | | |
| 29 | EM29 | RW | 0 | EXTI line29 wakes up the CPU mask control as<br>an event.<br>0:Event wake-up mask |
| | | | | 1:Event wakeup is not masked |
| 28:19 | Reserved | | | |
| | | | | EXTI line18 wakes up the CPU mask control as<br>an event. |
| 18 | EM18 | RW | 0 | 0:Event wake-up mask |
| | | | | 1:Event wakeup is not masked |
| | | | | EXTI line17 wakes up the CPU mask control as<br>an event. |
| 17 | EM17 | RW | 0 | 0:Event wake-up mask |
| | | | | 1:Event wakeup is not masked |
| 16:8 | Reserved | | | |
| | | | | EXTI line7 wakes up the CPU mask control as an<br>event. |
| 7 | EM7 | RW | 0 | 0:Event wake-up mask |
| | | | | 1:Event wakeup is not masked |
| | | | | EXTI line6 wakes up the CPU mask control as an |
| 6 | EM6 | RW | 0 | event. |
| | | | | 0:Event wake-up mask |
| Bit | Name | R/W | Reset Value | Function |
|-----|------|-----|-------------|----------------------------------------------------------|
| | | | | 1:Event wakeup is not masked |
| | | | | EXTI line5 wakes up the CPU mask control as an<br>event. |
| 5 | EM5 | RW | 0 | 0:Event wake-up mask |
| | | | | 1:Event wakeup is not masked |
| | | | | EXTI line4 wakes up the CPU mask control as an<br>event. |
| 4 | EM4 | RW | 0 | 0:Event wake-up mask |
| | | | | 1:Event wakeup is not masked |
| | | | | EXTI line3 wakes up the CPU mask control as an<br>event. |
| 3 | EM3 | RW | 0 | 0:Event wake-up mask |
| | | | | 1:Event wakeup is not masked |
| | | | | EXTI line2 wakes up the CPU mask control as an<br>event. |
| 2 | EM2 | RW | 0 | 0:Event wake-up mask |
| | | | | 1:Event wakeup is not masked |
| | | | | EXTI line1 wakes up the CPU mask control as an<br>event. |
| 1 | EM1 | RW | 0 | 0:Event wake-up mask |
| | | | | 1:Event wakeup is not masked |
| | | | | EXTI line0 wakes up the CPU mask control as an<br>event. |
| 0 | EM0 | RW | 0 | 0:Event wake-up mask |
| | | | | 1:Event wakeup is not masked |
## <span id="page-108-0"></span>**11.3.9. EXTI register map**
| O<br>ff<br>s<br>et | Reg<br>ister | 31 | 30 | 29 | 28 | 27 | 26 | 25 | 24 | 23 | 22 | 21 | 20 | 19 | 18 | 17 | 16 | 15 | 14 | 13 | 12 | 11 | 10 | 9 | 8 | 7 | 6 | 5 | 4 | 3 | 2 | 1 | 0 |
|-------------------------------|--------------------------|------|------|------|------|------|------|------|------------|------|------|------|------|------|-------|------------|-------|------|------|------|------|------|------|------------|-------|------|------|------|------|------|------|------------|------|
| 0x<br>0 | EXTI<br>_RTS<br>R | Res. | Res. | Res. | Res. | Res. | Res. | Res. | Res. | Res. | Res. | Res. | Res. | Res. | RT18 | RT17 | Res. | Res | Res | Res | Res | Res | Res | Res | Res | RT7 | RT6 | RT5 | RT4 | RT3 | RT2 | RT1 | RT0 |
| 0 | Reset<br>value | | | | | | | | | | | | | | 0 | 0 | | | | | | | | | | | | | | | | | |
| 0x<br>0 | EXTI<br>_FTS<br>R | Res. | Res. | Res. | Res. | Res. | Res. | Res. | Res. | Res. | Res. | Res. | Res. | Res. | FT18 | FT17 | Res | Res | Res | Res | Res | Res | Res | Res | Res | FT7 | FT6 | FT5 | FT4 | FT3 | FT2 | FT1 | FT0 |
| 4 | Reset<br>value | | | | | | | | | | | | | | 0 | 0 | | | | | | | | | | 0 | 0 | 0 | 0 | 0 | 0 | 0 | 0 |
| 0x<br>0 | EXTI<br>_SWI<br>ER | Res. | Res. | Res. | Res. | Res. | Res. | Res. | Res. | Res. | Res. | Res. | Res. | Res. | SWI18 | SWI17 | Res. | Res. | Res. | Res. | Res. | Res. | Res. | Res. | Res. | SWI7 | SWI6 | SWI5 | SWI4 | SWI3 | SWI2 | SWI1 | SWI0 |
| 8 | Reset<br>value | | | | | | | | | | | | | | 0 | 0 | | | | | | | | | | 0 | 0 | 0 | 0 | 0 | 0 | 0 | 0 |
| 0x<br>0 | EXTI<br>_PR | Res. | Res. | Res. | Res. | Res. | Res. | Res. | Res. | Res. | Res. | Res. | Res. | Res. | PR18 | PR17 | Res. | Res. | Res. | Res. | Res. | Res. | Res. | Res. | Res. | PR7 | PR6 | PR5 | PR4 | PR3 | PR2 | PR1 | PR0 |
| C | Reset<br>value | | | | | | | | | | | | | | 0 | 0 | | | | | | | | | | 0 | 0 | 0 | 0 | 0 | 0 | 0 | 0 |
| 0x<br>1<br>0-<br>0x<br>5<br>C | Re<br>serve<br>d | Res. | Res. | Res. | Res. | Res. | Res. | Res. | Res. | Res. | Res. | Res. | Res. | Res. | Res. | Res. | Res. | Res. | Res. | Res. | Res. | Res. | Res. | Res. | Res. | Res. | Res. | Res. | Res. | Res. | Res. | Res. | Res. |
| 0x<br>6<br>0 | EXTI<br>_EX<br>TICR<br>1 | Res. | Res. | Res. | Res. | Res. | Res. | | EXTI3[1:0] | Res. | Res. | Res. | Res. | Res. | Res. | EXTI2[1:0] | | Res. | Res. | Res. | Res. | Res. | Res. | EXTI1[1:0] | | Res. | Res. | Res. | Res. | Res. | Res. | EXTI0[1:0] | |
| | Reset<br>value | | | | | | | 0 | 0 | | | | | | | 0 | 0 | | | | | | | 0 | 0 | | | | | | | 0 | 0 |
| 0x<br>6<br>4 | EXTI<br>_EX<br>TICR<br>2 | Res. | Res. | Res. | Res. | Res. | Res. | Res. | EXTI7 | Res. | Res. | Res. | Res. | Res. | Res. | Res. | EXTI6 | Res. | Res. | Res. | Res. | Res. | Res. | Res. | EXTI5 | Res. | Res. | Res. | Res. | Res. | Res. | EXTI4[1:0] | |
| | Reset<br>value | | | | | | | | 0 | | | | | | | | 0 | | | | | | | | 0 | | | | | | | 0 | 0 |
| O<br>ff<br>s<br>et | Reg<br>ister | 31 | 30 | 29 | 28 | 27 | 26 | 25 | 24 | 23 | 22 | 21 | 20 | 19 | 18 | 17 | 16 | 15 | 14 | 13 | 12 | 11 | 10 | 9 | 8 | 7 | 6 | 5 | 4 | 3 | 2 | 1 | 0 |
|------------------------------|--------------------------|------|------|------|------|------|------|------|------|------|------|------|------|------|------|------|------|------|------|------|------|------|------|------|------|------|------|------|------|------|------|------|------|
| 0x<br>6<br>8 | EXTI<br>_EX<br>TICR<br>3 | Res. | Res. | Res. | Res. | Res. | Res. | Res. | Res. | Res. | Res. | Res. | Res. | Res. | Res. | Res. | Res. | Res. | Res. | Res. | Res. | Res. | Res. | Res. | Res. | Res. | Res. | Res. | Res. | Res. | Res. | Res. | Res |
| | Reset<br>value | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | |
| 0x<br>6<br>C<br>0x<br>7<br>C | Re<br>serve<br>d | Res. | Res. | Res. | Res. | Res. | Res. | Res. | Res. | Res. | Res. | Res. | Res. | Res. | Res. | Res. | Res. | Res. | Res. | Res. | Res. | Res. | Res. | Res. | Res. | Res. | Res. | Res. | Res. | Res. | Res. | Res. | Res. |
| 0x<br>8 | EXTI<br>_IMR | Res. | Res. | IM29 | Res. | Res. | Res. | Res. | Res. | Res. | Res. | Res. | Res. | Res | IM18 | IM17 | Res. | Res. | Res. | Res. | Res. | Res. | Res. | Res. | Res | IM7 | IM6 | IM5 | IM4 | IM3 | IM2 | IM1 | IM0 |
| 0 | Reset<br>value | | | 1 | | | | | | | | | | | 0 | 0 | | | | | | | | | | 0 | 0 | 0 | 0 | 0 | 0 | 0 | 0 |
| 0x<br>8 | EXTI<br>_EM<br>R | Res. | Res. | EM29 | Res. | Res. | Res. | Res. | Res. | Res. | Res. | Res. | Res. | Res | EM18 | EM17 | Res. | Res. | Res. | Res. | Res. | Res. | Res. | Res. | Res | EM7 | EM6 | EM5 | EM4 | EM3 | EM2 | EM1 | EM0 |
| 4 | Reset<br>value | | | 0 | | | | | | | | | | | 0 | 0 | | | | | | | | | | 0 | 0 | 0 | 0 | 0 | 0 | 0 | 0 |
# <span id="page-110-0"></span>**12. Cyclic redundancy check calculation unit (CRC)**
## **12.1. Introduction**
<span id="page-110-1"></span>According to the generator polynomial, the CRC calculation unit will operate the input 32-bit data to generate a CRC result.
## <span id="page-110-2"></span>**12.2. CRC main features**
- Uses CRC-32(ethernet)polynomial:0x4C11DB7 X<sup>32</sup> + X<sup>26</sup> + X<sup>23</sup> +X<sup>22</sup> +X<sup>16</sup> + X<sup>12</sup> + X<sup>11</sup> + X<sup>10</sup> +X<sup>8</sup> + X<sup>7</sup> + X<sup>5</sup> + X<sup>4</sup> + X<sup>2</sup> + X +1
- Support 32-bit data input
- A single input/output 32 data and result output share one register
- 8-bit register for general purpose(can be used as temporary storage)
- Computation time:4 AHB clocks for 32bits data
## <span id="page-110-3"></span>**12.3. CRC functional description**
#### <span id="page-110-4"></span>**12.3.1. CRC block diagram**
![](_page_110_Figure_12.jpeg)
Figure 12-1 CRC calculation unit block diagram
The CRC calculation unit contains a 32-bit data register:
When writing to this register, as an input register, new data to be calculated by CRC can be input.
When the register is read, the result of the last CRC calculation is returned.
Each time a data register is written, the result of the calculation is the combination of the previous CRC calculation and the new calculation (CRC is calculated on the entire 32-bit word, not byte by byte).
While the CRC is being calculated, writes are blocked until the end of the CRC calculation. The register CRC\_DR can be reset to 0xFFFF FFFF by setting the RESET bit of the register CRC\_CR. This operation does not affect the data in register CRC\_IDR.
## <span id="page-111-0"></span>**12.4. CRC registers**
## <span id="page-111-1"></span>**12.4.1. Data register (CRC\_DR)**
#### **Address offset:**0x00
#### **Reset value:**0xFFFF FFFF
| 31 | 30 | 29 | 28 | 27 | 26 | 25 | 24 | 23 | 22 | 21 | 20 | 19 | 18 | 17 | 16 |
|----|----|----|----|----|----|----|----|-----------|----|----|----|----|----|----|----|
| | | | | | | | | DR[31:16] | | | | | | | |
| | | | | | | | | RW | | | | | | | |
| 15 | 14 | 13 | 12 | 11 | 10 | 9 | 8 | 7 | 6 | 5 | 4 | 3 | 2 | 1 | 0 |
| | | | | | | | | DR[15:0] | | | | | | | |
| | | | | | | | | RW | | | | | | | |
| Bit | Name | R/W | Reset Value | Function |
|------|------|-----|--------------|---------------------------------------------------------------------------------------------------------------------------------------------|
| 31:0 | DR | RW | 32'hFFFFFFFF | Data register<br>When writing new data, it is used as an input register.<br>When read, the previous CRC calculation result is re<br>tained. |
## <span id="page-111-2"></span>**12.4.2. Independent data register (CRC\_IDR)**
#### **Address offset:**0x04
#### **Reset value:**0x0000 0000
| 31 | 30 | 29 | 28 | 27 | 26 | 25 | 24 | 23 | 22 | 21 | 20 | 19 | 18 | 17 | 16 |
|-----|-----|-----|-----|-----|-----|-----|-----|-----|-----|-----|----------|-----|-----|-----|-----|
| Res | Res | Res | Res | Res | Res | Res | Res | Res | Res | Res | Res | Res | Res | Res | Res |
| | | | | | | | | | | | | | | | |
| | | | | | | | | | | | | | | | |
| 15 | 14 | 13 | 12 | 11 | 10 | 9 | 8 | 7 | 6 | 5 | 4 | 3 | 2 | 1 | 0 |
| Res | Res | Res | Res | Res | Res | Res | Res | | | | IDR[7:0] | | | | |
| Bit | Name | R/W | Reset Value | Function |
|------|----------|-----|-------------|------------------------------------------------------------------------------------------------------------------------------------------------------------------------|
| 31:8 | Reserved | | - | |
| 7:0 | IDR[7:0] | RW | 0 | General purpose 8bit data register<br>These bits are used as temporary storage for one byte.<br>This register is not reset by the RESET bit of the CRC_CR<br>register. |
## <span id="page-111-3"></span>**12.4.3. Control register (CRC\_CR)**
#### **Address offset:**0x08
| 31 | 30 | 29 | 28 | 27 | 26 | 25 | 24 | 23 | 22 | 21 | 20 | 19 | 18 | 17 | 16 |
|-----|-----|-----|-----|-----|-----|-----|-----|-----|-----|-----|-----|-----|-----|-----|-----------|
| Res | Res | Res | Res | Res | Res | Res | Res | Res | Res | Res | Res | Res | Res | Res | Res |
| | | | | | | | | | | | | | | | |
| 15 | 14 | 13 | 12 | 11 | 10 | 9 | 8 | 7 | 6 | 5 | 4 | 3 | 2 | 1 | 0 |
| Res | Res | Res | Res | Res | Res | Res | Res | Res | Res | Res | Res | Res | Res | Res | RE<br>SET |
| | | | | | | | | | | | | | | | W |
| Bit | Name | R/W | Reset Value | Function |
|------|----------|-----|-------------|----------------------------------------------------------------------------------------------------------------------------------------|
| 31:1 | Reserved | | - | |
| 0 | RESET | | 0 | This bit is set by software to reset the CRC calculation<br>unit.This bit can only be set and is automatically cleared by<br>hardware. |
| Of<br>fs<br>et | Reg<br>iste<br>r | 31 | 30 | 29 | 28 | 27 | 26 | 25 | 24 | 23 | 22 | 21 | 20 | 19 | 18 | 17 | 16 | 15 | 14 | 13 | 12 | 11 | 10 | 9 | 8 | 7 | 6 | 5 | 4 | 3 | 2 | 1 | 0 |
|----------------|-----------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------|------|------|------|------|------|------|------|----------|------|------|------|------|------|------|------|------|------|------|------|------|------|------|------|------|------|------|------|------|------|------|------|-------|
| | CR<br>C_D<br>DR[31:0]<br>R | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | |
| 0x<br>00 | Re<br>set<br>valu<br>e | 1 | 1 | 1 | 1 | 1 | 1 | 1 | 1 | 1 | 1 | 1 | 1 | 1 | 1 | 1 | 1 | 1 | 1 | 1 | 1 | 1 | 1 | 1 | 1 | 1 | 1 | 1 | 1 | 1 | 1 | 1 | 1 |
| | CR<br>Res.<br>Res.<br>Res.<br>Res.<br>Res.<br>Res.<br>Res.<br>Res.<br>Res.<br>Res.<br>Res.<br>Res.<br>Res.<br>Res.<br>Res.<br>Res.<br>Res.<br>Res.<br>Res.<br>Res.<br>Res.<br>Res.<br>Res.<br>Res.<br>C_I<br>DR | | | | | | | | IDR[7:0] | | | | | | | | | | | | | | | | | | | | | | | | |
| 0x<br>04 | Re<br>set<br>valu<br>e | | | | | | | | | | | | | | | | | | | | | | | | | 0 | 0 | 0 | 0 | 0 | 0 | 0 | 0 |
| | CR<br>C_C<br>R | Res. | Res. | Res. | Res. | Res. | Res. | Res. | Res. | Res. | Res. | Res. | Res. | Res. | Res. | Res. | Res. | Res. | Res. | Res. | Res. | Res. | Res. | Res. | Res. | Res. | Res. | Res. | Res. | Res. | Res. | Res. | RESET |
| 0x<br>08 | Re<br>set<br>valu<br>e | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | 0 |
## <span id="page-112-0"></span>**12.4.4. CRC register map**
# <span id="page-113-0"></span>**13. Analog-to-digital converter (ADC)**
## <span id="page-113-1"></span>**13.1. Introduction**
The chip has a 12-bit SARADC (successive approximation analog-to-digital converter). The module has a total of 10 channels to be measured, including 8 external channels and 2 internal channels. The conversion mode of each channel can be set to single, continuous, discontinuous mode.Con-
version results are stored in left or right-aligned 16-bit data registers.
The analog watchdog feature allows the application to detect if the input voltage goes outside the user-defined higher or lower thresholds.
An efficient low-power mode is implemented to allow very low consumption at low frequency.
## <span id="page-113-2"></span>**13.2. ADC main features**
- High performance
- 12-bit, 10-bit, 8-bit or 6-bit configurable resolution
- ADC conversion time: 1µs@12bit (1 MHz)
- Self-calibration
- Programmable sampling time
- Programmable data alignment mode
- Low-power
- Application can reduce PCLK frequency for low-power operation while still keeping optimum ADC performance.
- Automatic delayed transition mode: prevents ADC overrun in applications with low frequency PCLK
- Analog input channels
- 8 external analog inputs
- 1 channel fo internal temperature sensor
- 1 channel for internal reference voltage channel(VREFINT)
- Start-of-conversion can be initiated:
- By software
- By hardware triggers with configurable polarity(TIM1)
- Conversion modes
- single mode: Can convert a single channel or can scan a sequence of channels
- continuous mode:Continuous mode converts selected inputs continuously
- discontinuous mode: Convert selected channel once per trigger
- Interrupt generation
- At the end of sampling
- At the end of conversion
- At the end of sequence conversion
- In case of analog watchdog
- Overrun events
Analog watchdog
## <span id="page-114-0"></span>**13.3. ADC functional description**
#### <span id="page-114-1"></span>**13.3.1. ADC diagram**
![](_page_114_Figure_4.jpeg)
Figure 13-1 ADC channel with analog switch
## <span id="page-114-2"></span>**13.3.2. Calibration (ADCAL)**
The ADC has a calibration function. During the procedure, the ADC calculates a calibration factor for internal use within the ADC. The application must not use the ADC during calibration and must wait until it is complete.
Before using ADC conveision,calibration operations should be carried out.Calibration is used to eliminate offset errors caused by process changes between chips.
Calibration operations include software calibration.
#### **ADC software calibration**
The software can set ADCAL = 1 to start the calibration. The calibration only the system clock can be selected as the ADC clock. ADCAL is cleared by hardware when calibration is complete,and Avaliable from ADC\_CALFACTOR register reads the calibration factor.The calibration factor will be maintained until system reset is generated.
When the working conditions of the ADC change (the change in VCC is the main factor for the offset of the ADC, followed by the change in temperature), it is recommended to perform a re-calibration operation.
Calibration software procedure:
- CKMODE selects the system clock
- Set ADCAL = 1
- Wait until ADCAL=0
### <span id="page-115-0"></span>**13.3.3. ADC on-off control (ADEN)**
At MCU power-up, the ADC is disabled and put in power-down mode (ADEN = 0).
The ADCEN bit is used to turn on or off ADC at control bit.
The following is the process to enable ADC:
The ADEN bit of the ADC\_CR register is set to 1
ADC conversions are also initiated by setting ADSRART or (if triggered) by an external trigger event.
The following is the procedure for disabling the ADC:
Check that ADSTART in the ADC\_CR register is 0 to ensure the ADC is not in the process of converting. If ADSTART=0 and ADEN=1,the ADC is disabled to set ADDIS in ADC\_CR register to 1. If necessary, set ADSTP in the ADC\_CR register to 1 to stop the ongoing ADC conversion, and wait for ADSTP to be cleared by hardware (cleared to 0 means the conversion is stopped).
Warning: ADEN bit cannot be set to 1 during 4 ADC clocks after ADCAL is cleared by hardware and ADCAL = 1.
![](_page_115_Figure_20.jpeg)
Figure 13-2 Enabling/disabling the ADC
## <span id="page-116-0"></span>**13.3.4. ADC Clock**
The ADC has a dual clock-domain architecture, so that the ADC can be fed with a clock (ADC\_CLK) independent from the APB clock (PCLK). ADC\_CLK can be generated by two possible clock sources.
![](_page_116_Figure_3.jpeg)
Figure 13-3 ADC clock scheme
| | | | Latency between the trigger event and the start of | | | | | | |
|------------------|-------------|------|----------------------------------------------------|--|--|--|--|--|--|
| ADC clock source | CKMODE[3:0] | 分频系数 | conversion(T is the clock period) | | | | | | |
| | 0000 | 1 | 0 | | | | | | |
| | 0001 | 2 | 0 | | | | | | |
| | 0010 | 4 | 0 | | | | | | |
| | 0011 | 8 | 0 | | | | | | |
| PCLK | 0100 | 16 | 0 | | | | | | |
| | 0101 | 32 | 0 | | | | | | |
| | 0110 | 64 | 0 | | | | | | |
| | 0111 | / | / | | | | | | |
| | 1000 | 1 | 0 | | | | | | |
| | 1001 | 2 | 0 | | | | | | |
| | 1010 | 4 | 0 | | | | | | |
| | 1011 | 8 | 0 | | | | | | |
| HSI | 1100 | 16 | 0 | | | | | | |
| | 1101 | 32 | 0 | | | | | | |
| | 1110 | 64 | 0 | | | | | | |
| | 1111 | / | / | | | | | | |
Table 13-1 Delay between trigger and conversion start
## <span id="page-116-1"></span>**13.3.5. Configuring the ADC**
Software must write to the ADCAL and ADEN bits in the ADC\_CR register if the ADC is disabled (ADEN must be 0).Software must rewrite to the ADSTART bit in the ADC\_CR register only if the ADC is enabled and there is no pending request to disable the ADC(ADEN=1).
For all the other control bits in the ADC\_IER, ADC\_CFGRi, ADC\_SMPR, ADC\_TR and ADC\_CCR registers, software must only write to the configuration control bits if the ADC is enabled (ADEN = 1) and if there is no conversion ongoing (ADSTART = 0). ADC\_CHSELR is writted with ADEN = 0 and ADSTART = 0.
Software must only write to the ADSTP bit in the ADC\_CR register if the ADC is enabled and there is no pending request to disable the ADC (ADSTART = 1).
## <span id="page-116-2"></span>**13.3.6. Channel selection (CHSEL, SCANDIR)**
There are up to 11 multiplexed channels:
● 8 analog inputs from GPIO pins (ADC\_IN0...ADC\_IN9)
● 2 internal analog inputs (Temperature Sensor, Internal Reference Voltage )
It is possible to convert a single channel or to automatically scan a sequence of channels.
The sequence of the channels to be converted must be programmed in the ADC\_CHSELR channel selection register: each analog input channel has a dedicated selection bit.
The order in which the channels will be scanned can be configured by programming the bit SCAN-DIR bit in the ADC\_CFGR1 register:
- SCANDIR = 0: forward scan Channel 0 to Channel 9
- SCANDIR = 1: backward scan Channel 9 to Channel 0
The temperature sensor is connected to channel ADC\_IN8(TS\_VIN). The internal voltage reference is connected to channel ADC\_IN9(VREFINT).
### <span id="page-117-0"></span>**13.3.7. Programmable sampling time (SMP)**
Before starting a conversion, the ADC needs to establish a direct connection between the voltage source to be measured and the embedded sampling capacitor of the ADC. This sampling time must be enough for the input voltage source to charge the sample and hold capacitor to the input voltage level.
Having a programmable sampling time allows to trim the conversion speed according to the input resistance of the input voltage source.
The ADC samples the input voltage for a number of ADC clock cycles that can be modified using the SMP[2:0] bits in the ADC\_SMPR register. This programmable sampling time is common to all channels. If required by the application, the software can change and adapt this sampling time between each conversions.
The total conversion time is calculated as follows:
tCONV = Sampling time + (Convert resolution +0.5) x ADC clock cycles
For example:
When ADC\_CLK = 16MHz, the resolution is 12 bits, and the sampling time is 3.5 ADC clock cycles:
tCONV = (3.5 + 12.5) x ADC clock period = 16 x ADC clock period = 1 µs
The ADC indicates the end of the sampling phase by setting the EOSMP flag.
#### <span id="page-117-1"></span>**13.3.8. Single conversion mode (CONT = 0, DISCEN = 0)**
In Single conversion mode, the ADC performs a single sequence of conversions, converting all the channels once. This mode is selected when CONT = 0, DISCEN = 0 in the ADC\_CFGR1 register. ADC conversions can be initiated in two ways:
- Set ADSTART bit in ADC\_CR register
- Hardware trigger events
Inside the sequence, after each conversion is complete:
- The converted data are stored in the 16-bit ADC\_DR register
- The EOC (end of conversion) flag is set
- An interrupt is generated if the EOCIE bit is set
After the sequence of conversions is complete:
- The EOSEQ (end of sequence) flag is set
- An interrupt is generated if the EOSIE bit is set
Then the ADC stops until a new external trigger event occurs or the ADSTART bit is set again. Note: To convert a single channel, program a sequence with a length of 1.
### <span id="page-118-0"></span>**13.3.9. Continuous conversion mode (CONT = 1)**
In continuous conversion mode, when a software or hardware trigger event occurs, the ADC performs a sequence of conversions, converting all the channels once and then automatically re-starts and continuously performs the same sequence of conversions. This mode is selected when CONT = 1 in the ADC\_CFGR1 register.
Conversion is started by either:
- Setting the ADSTART bit in the ADC\_CR register
- Hardware trigger event
Inside the sequence, after each conversion is complete:
- The converted data are stored in the 16-bit ADC\_DR register
- The EOC (end of conversion) flag is set
- An interrupt is generated if the EOCIE bit is set
After the sequence of conversions is complete:
- The EOSEQ (end of sequence) flag is set
- An interrupt is generated if the EOSEQIE bit is set
Then, a new sequence restarts immediately and the ADC continuously repeats the conversion sequence.
Note: To convert a single channel, program a sequence with a length of 1
It is not possible to have both discontinuous mode and continuous mode enabled: it is forbidden to set both bits DISCEN = 1 and CONT = 1.
#### <span id="page-118-1"></span>**13.3.10. Discontinuous conversion mode (DISCEN = 1)**
This mode is enabled by setting the DISCEN bit in the ADC\_CFGR1 register.
In this mode (DISCEN = 1), a hardware or software trigger event is required to initiate each conversion defined in a sequence.
Conversely, when DISCEN = 0, a hardware or software trigger event can initiate all conversions defined in a sequence.
For example:
#### **DISCEN = 1, the channels to be converted are: 0, 3, 7, 10**
- 1 st trigger: Channel 0 is converted and an EOC event occurs
- 2 nd trigger: Channel 3 is converted and an EOC event occurs
- 3 rd trigger: Channel 7 is converted and an EOC event occurs
- 4 th trigger: Channel 10 is converted and EOC and EOSEQ events are generated
- 5 th trigger: Channel 0 is converted and an EOC event occurs
- 6 th trigger: Channel 3 is converted and an EOC event occurs
- ...
#### **DISCEN=0, 需要转换的通道为:0, 3, 7, 10**
- 1 st Trigger: The entire complete sequence of conversions, in turn, channels 0, 3, 7, and 10.
Each conversion is completed, an EOC event is generated, and the conversion to the last channel generates an EOSEQ event in addition to the EOC.
- Any trigger event restarts the complete sequence conversion
Note: It is impossible to have the ADC in continuous mode and continuous conversion mode at the same time, in this case (DISCEN = 1, CONT = 1), it behaves as a single conversion mode.
#### <span id="page-119-0"></span>**13.3.11. Starting conversions (ADSTART)**
Software starts ADC conversion with setting ADSTART = 1.
When ADSTART is set, the conversion:
- When EXTEN = 0x0 (software trigger), start immediately
- When if EXTEN ≠ 0x0, start at the next selected hardware trigger valid edge
The ADSTART bit is also used to indicate whether an ADC conversion operation is currently in progress. When ADSTART = 0, the ADC can be reconfigured, indicating that the ADC is idle at this time.
ADSTART bit can be cleared by hardware.
- One-shot conversion mode is triggered by software (CONT = 0, EXTSEL = 0x0) - After sequence conversion is complete (EOSEQ = 1)
- Discontinuous conversion mode is triggered by software (CONT = 0, DISCEN = 1, EXTSEL = 0x0)
- After conversion is complete (EOC = 1)
- In all cases (CONT = X, EXTSEL = X)
- After the software calls and executes the ADSTP procedure
Note: In continuous mode (CONT = 1), the ADSTART bit cannot be cleared by hardware caused by EOSEQ because it automatically restarts the sequence conversion. When the hardware trigger is selected as single conversion mode (CONT = 0 and EXTSEL = 0x01), ADSTART will not be cleared by hardware after the EOSEQ flag is set. This avoids the need for software to reset the ADSTART bit and ensures that no hardware trigger event is missed.
#### <span id="page-119-1"></span>**13.3.12. 转换时间**
The time used for conversion consists of the start conversion time and the successive approximation time related to conversion resolution.
tADC = tSMPL + tSAR = [ 3.5|min + 12.5|12bit] \* tADC\_CLK tADC = tSMPL + tSAR = 218.75ns|min + 781.25 ns|12bit = 1 µs|min (for fADC\_CLK = 16 MHz)
![](_page_120_Figure_1.jpeg)
Figure 13-4 analog to digital conversion timing
## <span id="page-120-0"></span>**13.3.13. Stopping an ongoing conversion (ADSTP)**
The software can decide to stop any ongoing conversions by setting ADSTP = 1 in the ADC\_CR register.This will reset the ADC operation and the ADC will be idle, ready for a new operation. When the ADSTP bit is set by software, any ongoing conversion is aborted and the result is discarded (ADC\_DR register is not updated with the current conversion).
The scan sequence is also aborted and reset (meaning that restarting the ADC would restart a new sequence).
Once this procedure is complete, the ADSTP and ADSTART bits are both cleared by hardware.
![](_page_120_Figure_7.jpeg)
![](_page_120_Figure_8.jpeg)
## <span id="page-120-1"></span>**13.4. Conversion on external trigger and trigger polarity (EXTSEL, EXTEN)**
A conversion or a sequence of conversion can be triggered either by software or by an external event (for example timer capture、input pin). If the EXTEN[1:0] control bits are not equal to "00", then external events are able to trigger a conversion with the selected polarity. The trigger selection is effective once software has set bit ADSTART = 1.
Any hardware triggers which occur while a conversion is ongoing are ignored.
| Source | EXTEN[1:0] |
|-------------------------------------|------------|
| Trigger detection disabled | 00 |
| Detect on rising edge | 01 |
| Detect on falling edge | 10 |
| Detects on rising and falling edges | 11 |
If bit ADSTART = 0, any hardware triggers which occur are ignored.
Note: The polarity of the external trigger can be changed only when the ADC is not converting (AS-TART = 0).The EXTSEL[2:0] control bits are used to select events that can trigger conversions.
The following table shows possible external triggers for rule transitions. A software source trigger event can be generated by setting the ADSTART bit in the ADC\_CR register.
| Figure 13-2 External trigers | | | | | | | | |
|------------------------------|-----------|-------------|--|--|--|--|--|--|
| Name | source | EXTSEL[2:0] | | | | | | |
| EXT0 | TIM1_TRGO | 000 | | | | | | |
| EXT1 | TIM1_CC4 | 001 | | | | | | |
<span id="page-121-0"></span>Note: The trigger selection can be changed only when the ADC is not converting
#### **13.4.1. Fast conversion mode**
It is possible to obtain faster conversion times (tSAR) by reducing the ADC resolution.The resolution can be configured to be either 12, 10, 8, or 6 bits by programming the RES[1:0] bits in the ADC\_CFGR1 register. Lower resolution allows faster conversion times for applications where high data precision is not required.
Lower resolution mode reduces the conversion time of successive approximation as shown in the table below:
| RESSEL<br>[1:0] | tSAR<br>(ADC clock cy<br>cles) | tSAR(ns) @<br>fADC = 24MHz | tSMP<br>(ADC clock cy<br>cles) | tADC(tSMP = 3.5)<br>(ADC clock cycles) | tCONV(ns) @<br>fADC = 24MHz |
|-----------------|--------------------------------|----------------------------|--------------------------------|----------------------------------------|-----------------------------|
| 12 | 12.5 | 521ns | 3.5 | 16 | 667ns |
| 10 | 10.5 | 438ns | 3.5 | 14 | 583ns |
| 8 | 8.5 | 396ns | 3.5 | 12 | 500ns |
| 6 | 6.5 | 271ns | 3.5 | 10 | 417ns |
## <span id="page-121-1"></span>**13.4.2. End of conversion, end of sampling phase (EOC, EOSMP flags)**
The ADC indicates each end of conversion (EOC) event.
The ADC sets the EOC flag in the ADC\_ISR register as soon as a new conversion data result is available in the ADC\_DR register. An interrupt can be generated if the EOCIE bit in the ADC\_IER register is set to 1. The EOC flag is cleared by software either by writing 1 to it, or by reading the ADC\_DR register.
The ADC also indicates the end of sampling phase by setting the EOSMP flag in the ADC\_ISR register. The EOSMP flag is cleared by software by writing1 to it. An interrupt can be generated if the EOSMPIE bit in the ADC\_IER register is set to 1.
## <span id="page-121-2"></span>**13.4.3. End of conversion sequence (EOSEQ flag)**
The ADC notifies the application of each end of sequence (EOSEQ) event.
The ADC sets the EOSEQ flag in the ADC\_ISR register as soon as the last data result of a conversion sequence is available in the ADC\_DR register. An interrupt can be generated if the EOSEQIE bit in the ADC\_IER register is set to 1. The EOSEQ flag is cleared by software by writing 1.
![](_page_122_Figure_3.jpeg)
<span id="page-122-0"></span>![](_page_122_Figure_4.jpeg)
Figure 13-6 Single conversions of a sequence, software trigger
- 1. EXTEN=0x0, CONT=0
- 2. CHSEL=0x20601, WAIT=0
![](_page_123_Figure_1.jpeg)
Figure 13-7 Continuous conversion of a sequence, software trigger
- 1. EXTEN=0x0, CONT=1,
- 2. CHSEL=0x20601, WAIT=0
![](_page_123_Figure_5.jpeg)
Figure 13-8 Single conversions of a sequence, hardware trigger
- 1. EXTSEL=TRGx, EXTEN=0x1 ( rising edge ), CONT=0
- 2. CHSEL=0xF, SCANDIR=0
![](_page_124_Figure_1.jpeg)
Figure 13-9 Continuous conversion of a sequence, software trigger
- 1. EXTSEL=TRGx, EXTEN=0x2 ( falling edge ), CONT=1
- 2. CHSEL=0xF, SCANDIR=0, WAIT=0
## <span id="page-124-0"></span>**13.5. Data management**
## <span id="page-124-1"></span>**13.5.1. Data register and data alignment (ADC\_DR, ALIGN)**
At the end of each conversion (when an EOC event occurs), the result of the converted data is stored in the ADC\_DR data register which is 16-bit wide.
The format of the ADC\_DR depends on the configured data alignment and resolution. The ALIGN bit in the ADC\_CFGR1 register selects the alignment of the data stored after conversion. Data can be right-aligned (ALIGN = 0) or left-aligned (ALIGN = 1) .
| ALIGN | RESSEL | 15 | 14 | 13 | 12 | 11 | 10 | 9 | 8 | 7 | 6 | 5 | 4 | 3 | 2 | 1 | 0 |
|-------|--------|------------|-----------|-----------|-----------|------------|-----|-----|---|-----|-----|-----|-----|---|---|---|---|
| | 0X0 | | 0X0 | | | DATA[11:0] | | | | | | | | | | | |
| | 0X1 | | 0X0 | | | DATA[9:0] | | | | | | | 0X0 | | | | |
| 0 | 0X2 | | 0X0 | | | DATA[7:0] | | | | | | 0x0 | | | | | |
| | 0X3 | 0X0 | | | | DATA[6:0] | | | | | 0X0 | | | | | | |
| | 0X0 | DATA[11:0] | | | | | 0X0 | | | | | | | | | | |
| 0X1 | | | DATA[9:0] | | | | | 0X0 | | | 0X0 | | | | | | |
| 1 | 0X2 | | | | DATA[7:0] | | | | | 0x0 | | | 0X0 | | | | |
| | 0X3 | | | DATA[6:0] | | | | | | 0X0 | | | 0X0 | | | | |
## <span id="page-124-2"></span>**13.5.2. ADC overrun (OVR, OVRMOD)**
The overrun flag (OVR) indicates a data overrun event, when the converted data was not read in time by the CPU , before the data from a new conversion is available.
The OVR flag is set in the ADC\_ISR register if the EOC flag is still at '1' at the time when a new conversion completes. An interrupt can be generated if the OVRIE bit is set in the ADC\_IER register.
When an overrun event occurs, the ADC keeps operating and can continue to convert unless the software decides to stop and reset the sequence conversion. The software can be used to set the ADSTP bit to 1 in the ADC\_CR register to stop ADC converting,and the OVR flag can be cleared by software by writing 1 to it.
It is possible to configure if the data is preserved or overwritten when an overrun event occurs by programming the OVRMOD bit in the ADC\_CFGR1 register:
OVRMOD=0
- An overrun event preserves the data register from being overwritten: the old data is maintained and the new conversion is discarded. If OVR remains at 1, further conversions can be performed but the resulting data is discarded.
OVRMOD=1
- The data register is overwritten with the last conversion result and the previous unread data is lost. If OVR remains at 1, further conversions can be performed and the ADC\_DR register always contains the data from the latest conversion.
![](_page_125_Figure_7.jpeg)
Figure 13-10 Overrun
#### <span id="page-125-0"></span>**13.5.3. Managing conversion sequences without DMA**
If the ADC conversion is slow enough, then the conversion sequence can be controlled by software. In this case, software application of the EOC flag and its associated interrupts will go through each conversion data. At the end of each conversion, we can see that the EOC bit in the ADC\_ISR register is set and the conversion value in the ADC\_DR register can be read at this time. the OVRMOD bit in the ADC\_CFGR1 register can be configured to 0 to manage overshoot events.
#### <span id="page-125-1"></span>**13.5.4. Conversion without DMA and overflow detection**
There are often applications that convert one or more channels and do not require the results to be read every time they are converted. In this case, the OVRMOD bit must be set to 1 and the software should ignore the OVR flag. When OVRMOD=1, an overshoot event cannot prevent the ADC from continuing to convert and the data in the ADC\_DR register is always the last converted data.
## <span id="page-126-0"></span>**13.6. Low-power features**
#### <span id="page-126-1"></span>**13.6.1. Automatic latency conversion mode**
Automatic latency conveision mode can be used to simplify software as well as optimizing the performance of applications.It is not easy to generate ADC overrun in this mode.
When the WAIT bit is set to 1 in the ADC\_CFGR1 register, a new conversion can start only if the previous data has been treated(For example,once the ADC\_DR register has been read or if the EOC bit has been cleared).This is a way to automatically adapt the speed of the ADC to the speed of the system that reads the data.
Note: Any hardware triggers which occur while a conversion is ongoing or during the wait time preceding the read access are ignored.
![](_page_126_Figure_7.jpeg)
Figure 13-11 Automatic latency conversion mode
- 1. EXTEN=0x0, CONT=1
- 2. CHSEL=0x3, SCANDIR=0
## <span id="page-126-2"></span>**13.7. Analog window watchdog**
The AWD analog watchdog feature is enabled by setting the AWDEN bit in the ADC\_CFGR1 register. It is used to monitor that either one selected channel or all enabled channels remain within a configured voltage range (window).
The AWD analog watchdog status bit is set if the analog voltage converted by the ADC is below a lower threshold or above a higher threshold. These thresholds are programmed in the 12 least significant bits of the ADC\_HTR and ADC\_LTR 16-bit registers. An interrupt can be enabled by setting the AWDIE bit in the ADC\_IER register.The AWD flag is cleared by software by writing 1 to it. When converting a data with a resolution of less than 12-bit (according to bits DRES[1:0]), the programmed thresholds must be kept cleared because the internal comparison is always performed on the full 12-bit raw converted data (left aligned).
Note: ADC analog input channel 0 does not support a single channel analog watchdog function.
| Resolution bits | Analog Watchdog comparison between: | | | | | | | |
|-----------------|------------------------------------------------|-----------------------|----------------------------------------------------------|--|--|--|--|--|
| | Raw converted data, left aligned<br>thresholds | | comments | | | | | |
| 00: 12-bit | DATA[11:0] | LT[11:0] and HT[11:0] | - | | | | | |
| 01: 10-bit | DATA[11:2],00 | LT[11:0] and HT[11:0] | The user must configure LT[1:0]<br>and HT[1:0] to 00 | | | | | |
| 10: 8-bit | DATA[11:4],0000 | LT[11:0] and HT[11:0] | The user must configure LT[3:0]<br>and HT[3:0] to 0000 | | | | | |
| 11: 6-bit | DATA[11:6],000000 | LT[11:0] and HT[11:0] | The user must configure LT[5:0]<br>and HT[5:0] to 000000 | | | | | |
![](_page_127_Figure_4.jpeg)
![](_page_127_Figure_5.jpeg)
Figure 13-12 Analog watchdog guarded area
| | Table 13-4 Analog watchdog channel selection | |
|--|----------------------------------------------|--|
| | | |
| Channels guarded by the analog watchdog | AWDSGL bit | AWDEN bit |
|-----------------------------------------|------------|-----------|
| None | x | 0 |
| All channels | 0 | 1 |
| Single channel | 1 | 1 |
## <span id="page-127-0"></span>**13.7.1. ADC\_AWD\_OUT signal output generation**
The analog watchdog is associated with an internal hardware signal, ADC\_AWD\_OUT is directly connected to the ETR input (external trigger) of the on-chip timer TIM1.
When the analog watchdog is enabled, ADC\_AWD\_OUT is activated:
When the conversion of the channel selected by AWDCH exceeds the programmed threshold, ADC\_AWD\_OUT will be set.
After the conversion of the next channel selected by AWDCH, ADC\_AWD\_OUT is reset within the programmed threshold. It will remain at 1 if the next protected transition still exceeds the programmed threshold.
- ADC\_AWD\_OUT is also reset when ADC is disabled. Note that stopping conversion (ADSTP set to 1) may clear the ADC\_AWDx\_OUT state.
- Channels not selected as analog watchdog do not affect ADC\_AWD\_OUT status bits.
The AWD flag is set by hardware and reset by software: the AWD flag has no effect on the generation of ADC\_AWD\_OUT (eg, if the flag is not cleared by software, ADC\_AWDx\_OUT can toggle while the AWDx flag remains at 1).
The ADC\_AWD\_OUT signal is generated by the PCLK domain.
AWD comparison is performed at the end of each ADC conversion.
## <span id="page-128-0"></span>**13.8. Temperature sensor and internal reference voltage**
A temperature sensor can be used to measure the junction temperature (TJ) of the device.
The temperature sensor is internally connected to the ADC input channel, which can be used to convert the sensor's voltage value to a numerical value. The sampling time of the temperature sensor must be greater than the minimum value of Ts\_temp given in the datasheet. When the temperature sensor is not in use, the sensor can be placed in a power-down mode.
The output voltage of the temperature sensor varies linearly with temperature, but each chip has subtle differences related to process variables. In order to improve this accuracy, the calibration value of each chip will be individually given by the product test and saved in the system storage area.
The internal voltage reference (VREFINT) provides a regulated voltage output to the ADC and comparator.
Note: The TSVREF bit must be set to activate two internal channels: temperature sensor, VREFINT.
![](_page_128_Figure_10.jpeg)
How to use the temperature sensor to read the temperature:
1. Select ADC1\_IN11 input channel
2. Select an appropriate sampling time according to the device specification
3. Set the TSEN bit in the ADC\_CCR register to wake up the temperature sensor from power down mode
4. Start ADC conversion with ADSTART bit set in ADC\_CR register (external trigger is also available)
- 5. Read VSENSE conversion data from ADC\_DR register
- 6. Count the temperature using the following formula:
$$Temperature\,(in\,^\circ\text{C}) = \frac{85^\circ\text{C} - 30^\circ\text{C}}{TS\_{CAL2} - TS\_{CAL1}} \times \left(TS\_{DATA} - TS\_{CAL1}\right) + 30^\circ\text{C}$$
TSCAL2 represents the calibration value of the 85°C temperature sensor, the calibration value storage Address offset: 0x1FFF 0F18
TSCAL1 represents the calibration value of the 30°C temperature sensor, the calibration value storage Address offset: 0x1FFF 0F14
TSDATA is the actual output value converted by the ADC
Note: When the sensor wakes up from power-down mode, it needs a start-up time to correctly output
VSENSE, and the ADC also has a start-up time after power-on.
To reduce this delay, you need to set the ADEN and TSEN bits at the same time.
**Calculating the actual Vcc voltage using the internal reference voltage**
$$VREFINT = 1.2V = \frac{ADC\\_DATAx}{4095} \times VCC$$
**Calculating the Vchannnel voltage using the the actual Vcc**
$$V\mathcal{C}HANNEL = \frac{ADC\\_DATAx}{4095} \times VCC$$
VREFINT is fixed at 1.2V
VCHANNEL is the channel voltage,
ADC\_DATA is the conversion data in ADC\_DR,
4096 is represented as 12 bits.
Microcontrolled VDDA power supply is easily affected or the value is not very clear.The internal voltage reference(VREFINT)and calibration data obtained from Vdda=.3V ADC during production can be used to evaluate the true voltage level of Vdda.
## <span id="page-129-0"></span>**13.9. ADC interrputs**
ADC interrupts can be generated by any of the following events:
- End of any conversion (EOC flag)
- End of sequence conversion (EOS flag)
- When analog watchdog detection occurs (AWD flag)
- Occurs when the sampling phase ends (EOSMP flag)
- When data overshoot occurs (OVR flag)
Separate interrupt enable bit for flexible setting of ADC interrupts
| Interrput event | Event flag | Enable control bit | | |
|-----------------------------------|------------|--------------------|--|--|
| End of conversion | EOC | EOCIE | | |
| End of sequence of conversions | EOS | EOSIE | | |
| Analog watchdog status bit is set | AWD | AWDIE | | |
| End of sampling phase | EOSMP | EOSMPIE | | |
| Overrun | OVR | OVRIE | | |
#### Table 13-5 ADC interrput
## <span id="page-129-1"></span>**13.10. ADC regiseters**
## <span id="page-129-2"></span>**13.10.1. ADC interrupt and status register (ADC\_ISR)**
#### **Address offset:** 0x00
**Reset value:** 0x0000 0000
| 31 | 30 | 29 | 28 | 27 | 26 | 25 | 24 | 23 | 22 | 21 | 20 | 19 | 18 | 17 | 16 |
|-----|-----|-----|-----|-----|-----|-----|-----|-----|-----|-----|-----|-------|-----|-------|-----|
| Res | Res | Res | Res | Res | Res | Res | Res | Res | Res | Res | Res | Res | Res | Res | Res |
| | | | | | | | | | | | | | | | |
| 15 | 14 | 13 | 12 | 11 | 10 | 9 | 8 | 7 | 6 | 5 | 4 | 3 | 2 | 1 | 0 |
| | | | | | | | | | | | | | | | |
| Res | Res | Res | Res | Res | Res | Res | Res | AWD | Res | Res | OVR | EOSEQ | EOC | EOSMP | Res |
| Bit | Name | R/W | Reset<br>Value | Function |
|------|--------------|-------|----------------|-------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------|
| 31:8 | Re<br>served | | | |
| 7 | AWD | RC_W1 | 0 | Analog watchdog flag<br>This bit is set by hardware when the converted voltage crosses the values<br>programmed in the ADC_LTR and ADC_HTR registers. It is cleared by<br>software writing 1 to it.<br>0:No analog watchdog event occurred (or the flag event was already<br>acknowledged and cleared by software)<br>1: Analog watchdog event occurred |
| 6:5 | Re<br>served | | | |
| 4 | OVR | RC_W1 | 0 | ADC overrun<br>This bit is set by hardware when an overrun occurs, meaning that a new<br>conversion has complete while the EOC flag was already set. It is cleared<br>by software writing 1 to it.<br>0: No overrun occurred (or the flag event was already acknowledged and<br>cleared by software)<br>1: Overrun has occurred |
| 3 | EOSEQ | RC_W1 | 0 | End of sequence flag<br>This bit is set by hardware at the end of the conversion of a sequence of<br>channels selected by the CHSEL bits. It is cleared by software writing 1 to<br>it.<br>0: Conversion sequence not complete (or the flag event was already<br>acknowledged and cleared by software)<br>1: Conversion sequence complete |
| 2 | EOC | RC_W1 | 0 | End of conversion flag<br>This bit is set by hardware at the end of each conversion of a channel<br>when a new data result is available in the ADC_DR register. It is cleared<br>by software writing 1 to it or by reading the ADC_DR register.<br>0: Channel conversion not complete (or the flag event was already<br>acknowledged and cleared by software)<br>1: Channel conversion complete |
| 1 | EOSMP | RC_W1 | 0 | End of sampling flag<br>This bit is set by hardware during the conversion, at the end of the sam<br>pling phase.It is cleared by software by programming it to '1'.<br>0: Not at the end of the sampling phase (or the flag event was already<br>acknowledged and cleared by software)<br>1: End of sampling phase reached |
| 0 | Re<br>served | | | |
## <span id="page-130-0"></span>**13.10.2. ADC interrupt enable register (ADC\_IER)**
#### **Address offset:** 0x04
| 31 | 30 | 29 | 28 | 27 | 26 | 25 | 24 | 23 | 22 | 21 | 20 | 19 | 18 | 17 | 16 |
|----|----|----|----|----|----|----|-----|-----|----|----|-----|-----|----|-----|----|
| Re | Re | Re | Re | Re | Re | Re | Res | Res | Re | Re | Res | Res | Re | Res | Re |
| s | s | s | s | s | s | s | | | s | s | | | s | | s |
| | | | | | | | | | | | | | | | |
| 15 | 14 | 13 | 12 | 11 | 10 | 9 | 8 | 7 | 6 | 5 | 4 | 3 | 2 | 1 | 0 |
| Re | Re | Re | Re | Re | Re | Re | Re. | AWDI | Re | Re | OVRI | EOSE | EO | EOSMPI | Re |
|----|----|----|----|----|----|----|-----|------|----|----|------|------|-----|--------|----|
| s | s | s | s | s | s | s | s | E | s | s | E | QIE | CIE | E | s |
| | | | | | | | | rw | | | rw | rw | rw | rw | |
| Bit | Name | R/W | Reset Value | Function |
|------|----------|-----|-------------|-----------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------|
| 31:8 | Reserved | | | |
| 7 | AWDIE | RW | 0 | Analog watchdog interrupt enable<br>This bit is set and cleared by software to ena<br>ble/disable the analog watchdog interrupt.<br>0:Analog watchdog interrupt disabled<br>1:Analog watchdog interrupt enabled |
| 6:5 | Reserved | | | |
| 4 | OVRIE | RW | 0 | Overrun interrupt enable<br>This bit is set and cleared by software to ena<br>ble/disable the overrun interrupt.<br>0: Overrun interrupt disabled<br>1: Overrun interrupt enabled. |
| 3 | EOSEQIE | RW | 0 | End of conversion sequence interrupt enable<br>This bit is set and cleared by software to ena<br>ble/disable the end of sequence of conversions<br>interrupt.<br>0: EOSEQ interrupt disabled<br>1: EOSEQ interrupt enabled. |
| 2 | EOCIE | RW | 0 | End of conversion interrupt enable<br>This bit is set and cleared by software to ena<br>ble/disable the end of conversion interrupt.<br>0: EOC interrupt disabled<br>1: EOC interrupt enabled. |
| 1 | EOSMPIE | RW | 0 | End of sampling flag interrupt enable<br>This bit is set and cleared by software to ena<br>ble/disable the end of the sampling phase in<br>terrupt.<br>0: EOSMP interrupt disabled.<br>1: EOSMP interrupt enabled. |
| 0 | Reserved | | | |
Comments: Software can write these bits when ADSTART = 0 (to ensure that no conversion is in progress)
## <span id="page-131-0"></span>**13.10.3. ADC control register (ADC\_CR)**
#### **Address offset:** 0x08
| 31 | 30 | 29 | 28 | 27 | 26 | 25 | 24 | 23 | 22 | 21 | 20 | 19 | 18 | 17 | 16 |
|-----------|-----|-----|-----|-----|-----|-----|-----|-----|-----|-----|-----------|-----|-------------|-----|------|
| AD<br>CAL | Res | Res | Res | Res | Res | Res | Res | Res | Res | Res | Res | Res | Res | Res | Res |
| rs | | | | | | | | | | | | | | | |
| | | | | | | | | | | | | | | | |
| 15 | 14 | 13 | 12 | 11 | 10 | 9 | 8 | 7 | 6 | 5 | 4 | 3 | 2 | 1 | 0 |
| Res | Res | Res | Res | Res | Res | Res | Res | Res | Res | Res | AD<br>STP | Res | AD<br>START | Res | ADEN |
| Bit | Name | R/W | Reset Value | Function |
|-----|-------|-----|-------------|---------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------|
| 31 | ADCAL | RS | 0 | This bit is set by software to start the calibration<br>of the ADC.<br>It is cleared by hardware after calibration is<br>complete.<br>0: Calibration complete<br>1: Write 1 to calibrate the ADC. Read at 1<br>means that a calibration is in progress. |
| Bit | Name | R/W | Reset Value | Function |
|------|--------------|-----|-------------|---------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------|
| 30:8 | Reserved | | | |
| 7:6 | Verfbuff_sel | RW | 2'b0 | VREFBUF output voltage select<br>00: 1.5V<br>Other: reserved |
| 5 | Vref_buffere | RW | 1'b0 | VerfBuffer enable<br>Software write 0 to 0,write 1 to 1<br>0:disable VerfBuffer<br>1:enable VerfBuffer |
| 4 | ADSTP | RS | 0 | ADC stop conversion command<br>This bit is set by software to stop and discard an<br>ongoing conversion (ADSTP Command).<br>It is cleared by hardware when the conversion is<br>effectively discarded and the ADC is ready to<br>accept a new start conversion command.<br>0: No ADC stop conversion command ongoing<br>1: Write 1 to stop the ADC. Read 1 means that<br>an ADSTP command is in progress. |
| 3 | Reserved | | | |
| 2 | ADSTART | RS | 0 | ADC start conversion command<br>This bit is set by software to start ADC conver<br>sion. Depending on the EXTEN [1:0] configura<br>tion bits, a conversion either starts immediately<br>(software trigger configuration) or once a hard<br>ware trigger event occurs (hardware trigger con<br>figuration).<br>It is cleared by hardware:<br>–In single conversion mode (CONT = 0, DISCEN<br>= 0), when software trigger is selected (EXTEN =<br>00): at the assertion of the end of Conversion Se<br>quence (EOSEQ) flag.<br>–In discontinuous conversion mode(CONT = 0,<br>DISCEN = 1), when the software trigger is se<br>lected (EXTEN = 00): at the assertion of the end<br>of Conversion (EOC) flag.<br>–In all other cases: after the execution of the AD<br>STP command, at the same time as the ADSTP<br>bit is cleared by hardware.<br>0: No ADC conversion in progress<br>Write 1 to start ADC ,read 1 to indicate that ADC<br>is operating and may be transitioning. |
| 1 | ADDIS | RS | | ADEN Disable Enable<br>The ADC is disabled by a software bit and the<br>ADC goes into power-down. Hardware clears<br>this bit when the ADC is disabled (while ADEN<br>is cleared by hardware)<br>0: No ADDIS commond ongoing<br>1: Write 1 disables ADC, read 1 means ADDIS<br>command is being executed<br>Note: Setting ADDIS to 1 is only valid when<br>ADEN=1 and ADSTART=0 (to ensure that no<br>conversion is taking place) |
| 0 | ADEN | RS | 0 | ADC enable command<br>Software setting this bit enables the ADC and<br>the ADC will be ready to operate.<br>0: ADC disabled (OFF state)<br>1: Enable ADC |
## <span id="page-132-0"></span>**13.10.4. ADC configuration register 1 (ADC\_CFGR1)**
**Address offset:** 0x0C **Reset value:** 0x0000 0000
| 31 | 30 | 29 | 28 | 27 | 26 | 25 | 24 | 23 | 22 | 21 | 20 | 19 | 18 | 17 | 16 |
|-----|----------|----------|----------------|-------|----------------|-----|-----|-----------|------------|-----------|-----|---------|-------------|-----|------------|
| Res | Res | | | AWDCH | | Res | Res | AWD<br>EN | AWD<br>SGL | Res | Res | Res | Res | Res | DIS<br>CEN |
| | | RW | RW | RW | RW | | | RW | RW | | | | | | RW |
| 15 | 14 | 13 | 12 | 11 | 10 | 9 | 8 | 7 | 6 | 5 | 4 | 3 | 2 | 1 | 0 |
| Res | WAI<br>T | CO<br>NT | OV<br>RM<br>OD | | EX<br>TEN[1:0] | Res | | EXTSEL | | ALI<br>GN | | RES_SEL | SCA<br>NDIR | Res | Res |
| | RW | RW | RW | | RW | | RW | RW | RW | RW | RW | RW | RW | | |
| Bit | Name | R/W | Reset<br>Value | Function |
|-------|------------|-----|----------------|-------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------|
| 31:30 | Reserved | | | |
| | | | | Analog watchdog channel selection, software can clear and set this bit.<br>Analog Watchdog Monitors Selected Input Channels |
| | | | | 0000:ADC analog input channel 1 |
| | | | | 0001:ADC analog input channel 2 |
| | | | | 0010:ADC analog input channel 3 |
| | | | | …. |
| 29:26 | AWDCH[3:0] | RW | 0000 | 1001:ADC analog input channel 10<br>Other values: reserved bits |
| | | | | Note:<br>ADC analog input channel 0 does not support single channel analog<br>watchdog function.<br>The channel configured by the AWDCH[3:0] bits also needs to be set to |
| | | | | the CHSELR register<br>Software is allowed to write these bits only when ADSART = 0 (to ensure<br>no conversions are in progress) |
| 25:24 | Reserved | | | |
| | | | | Analog Watchdog Enable |
| | | | | Software can set and clear this bit |
| 23 | AWDEN | RW | 0 | 0:Disable analog watchdog |
| | | | | 1:Enable watchdog |
| | | | | Software is allowed to write these bits only when ADSART = 0 (to en<br>sure no conversions are in progress) |
| | | | | Enable analog watchdog on one channel or all channels<br>Software can set and clear this bit to enable the analog watchdog on the<br>channel or all channels set by the AWDCH[3:0] bits |
| 22 | AWDSGL | RW | 0 | 0:Enable analog watchdog on all channels |
| | | | | 1:Enable analog watchdog on one channel |
| | | | | Software is allowed to write these bits only when ADSART = 0 (to ensure<br>no conversions are in progress) |
| 21:17 | Reserved | | | |
| 16 | DISCEN | RW | 0 | Discontinuous mode<br>Software can set and clear this bit to enable/disable discontinuous mode<br>0: Disable discontinuous mode<br>1: Enable discontinuous mode<br>It is not possible to enable both discontinuous and continuous modes,<br>setting DISCEN = 1 and CONT = 1 is prohibited.<br>Software is allowed to write these bits only when ADSART = 0 (to en |
| | | | | sure no conversions are in progress) |
| 15 | Reserved | | | |
| | | | | wait for conversion mode<br>Software can set and clear this bit to enable/disable wait for conversion |
| 14 | WAIT | RW | 0 | mode<br>0: wait for conversion mode to close<br>1: Wait for conversion mode to open<br>Software is allowed to write these bits only when ADSART = 0 (to ensure<br>no conversions are in progress) |
| 13 | CONT | RW | 0 | Single/Continuous Conversion Mode<br>Software can set and clear this bit. If set to 1, the conversion will occur<br>consistently until the bit is cleared |
| | | | | It is not possible to enable both discontinuous and continuous modes, set<br>ting DISCEN = 1 and CONT = 1 is prohibited.<br>Software is allowed to write these bits only when ADSART = 0 (to ensure<br>no conversions are in progress) |
|-------|-------------|----|-----|--------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------|
| 12 | OVRMOD | RW | 0 | Overload Management Mode<br>Software can set and clear this bit to configure how data overload is man<br>aged<br>0: ADC_DR register retains old value when overload occurs<br>1: When an overload occurs, the ADC_DR register will be oveRWritten by<br>the last conversion result<br>Software is allowed to write these bits only when ADSART = 0 (to ensure<br>no conversions are in progress) |
| 11:10 | EXTEN[1:0] | RW | 00 | External trigger enable and polarity selection<br>Software can set and clear this bit, select drive polarity and enable drive<br>00: Hardware driver detection disabled (software boot transition)<br>01: Rising edge hardware drive detection<br>10: Falling edge hardware driver detection<br>11: Rising edge and falling edge hardware driver detection<br>Software is allowed to write these bits only when ADSART = 0 (to ensure<br>no conversions are in progress) |
| 9 | Reserved | | | |
| | | | | External trigger selection<br>This bit selects the external event that triggers the start of a conversion<br>000:TRG0(TIM1_TRG0)<br>001:TRG1(TIM1_CC4)<br>010:TRG2(Reserved) |
| 8:6 | EXTSEL[2:0] | RW | 000 | 011:TRG3(Reserved)<br>100:TRG4(Reserved)<br>101:TRG5(Reserved)<br>110:TRG6(Reserved)<br>111:TRG7(Reserved) |
| 5 | ALIGN | RW | 0 | Data alignment<br>Software sets and clears this bit to select right or left justification<br>0:Right-aligned<br>1:Left-aligned<br>Software is allowed to write these bits only when ADSART = 0 (to en<br>sure no conversions are in progress) |
| 4:3 | RESSEL[1:0] | RW | 00 | Data resolution<br>Software sets this bit to select the conversion resolution<br>00:12 bits<br>01:10 bits<br>10:8bits<br>11:6 bits<br>These bits are software operable only when ADEN = 0 |
| 2 | SCANDIR | RW | 0 | Scan sequence direction<br>Software can set and clear this bit to select the scan sequence direction<br>0: Up (from channel 0 to channel 11)<br>1: Down (from channel 11 to channel 0)<br>Software is allowed to write these bits only when ADSART = 0 (to ensure<br>no conversions are in progress) |
| 1:0 | Reserved | - | - | - |
## <span id="page-134-0"></span>**13.10.5. ADC configuration register 2 (ADC\_CFGR2)**
#### **Address offset:** 0x10
| 31 | 30 | 29 | 28 | 27 | 26 | 25 | 24 | 23 | 22 | 21 | 20 | 19 | 18 | 17 | 16 |
|--------|----|----|----|-----|-----|-----|-----|-----|-----|-----|-----|-----|-----|-----|-----|
| CKMODE | | | | Res | Res | Res | Res | Res | Res | Res | Res | Res | Res | Res | Res |
| RW | RW | RW | RW | | | | | | | | | | | | |
| 15 | 14 | 13 | 12 | 11 | 10 | 9 | 8 | 7 | 6 | 5 | 4 | 3 | 2 | 1 | 0 |
|-----|-----|-----|-----|-----|-----|-----|-----|-----|-----|-----|-----|-----|-----|-----|-----|
| Res | Res | Res | Res | Res | Res | Res | Res | Res | Res | Res | Res | Res | Res | Res | Res |
| | | | | | | | | | | | | | | | |
| Bit | Name | R/W | Reset<br>Value | Function | | | | |
|-------|------------------|-----|----------------|------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------|--|--|--|--|
| 31:28 | CKMODE<br>[3:0]: | RW | 0 | ADC clock mode, software can set and clear this bit to define the<br>clock source of the analog ADC<br>0000:PCLK<br>0001:PCLK/2<br>0010:PCLK/4<br>0011:PCLK/8<br>0100:PCLK/16<br>0101:PCLK/32<br>0110:PCLK/64<br>1000:HSI<br>1001:HSI/2<br>1010:HSI/4<br>1011:HSI/8<br>1100:HSI/16 | | | | |
| | | | | 1101:HSI/32 | | | | |
| | | | | 1110:HSI/64 | | | | |
| | | | | Note:<br>ADCAL = 0, ADSTART = 0, ADSTP = 0 and ADEN = 0 only when<br>ADC is not enabled. Software is allowed to manipulate these bits | | | | |
| 27:0 | Reserved | | | | | | | |
## <span id="page-135-0"></span>**13.10.6. ADC sampling time register (ADC\_SMPR)**
#### **Address offset:** 0x14
| 31 | 30 | 29 | 28 | 27 | 26 | 25 | 24 | 23 | 22 | 21 | 20 | 19 | 18 | 17 | 16 |
|-----|-----|-----|-----|-----|-----|-----|-----|-----|-----|-----|-----|-----|-----|-----|-----|
| Res | Res | Res | Res | Res | Res | Res | Res | Res | Res | Res | Res | Res | Res | Res | Res |
| | | | | | | | | | | | | | | | |
| | | | | | | | | | | | | | | | |
| 15 | 14 | 13 | 12 | 11 | 10 | 9 | 8 | 7 | 6 | 5 | 4 | 3 | 2 | 1 | 0 |
| Res | Res | Res | Res | Res | Res | Res | Res | Res | Res | Res | Res | Res | | SMP | |
| Bit | Name | R/W | Reset Value | Function | | | | | |
|------|----------|-----|-------------|-------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------|--|--|--|--|--|
| 31:3 | Reserved | | | | | | | | |
| 2:0 | SMP[2:0] | RW | 000 | Sampling time selection<br>Software configurable bit selects the sampling time for all<br>channels<br>000:3.5 ADC clock cycles<br>001:5.5 ADC clock cycles<br>010:7.5 ADC clock cycles<br>011:13.5 ADC clock cycles<br>100:28.5 ADC clock cycles<br>101:41.5 ADC clock cycles<br>110:71.5 ADC clock cycles<br>111:239.5 ADC clock cycles<br>Software is allowed to write these bits only when ADSART=<br>0 (to ensure no conversions are in progress) | | | | | |
## <span id="page-136-0"></span>**13.10.7. ADC watchdog threshold register (ADC\_TR)**
#### **Address offset:** 0x20
| | Reset value: 0x0FFF 0000 | | | | | | | | | | | | | | |
|-----|--------------------------|-----|-----|----|----|----|----|----|----|----|----|----|----|----|----|
| 31 | 30 | 29 | 28 | 27 | 26 | 25 | 24 | 23 | 22 | 21 | 20 | 19 | 18 | 17 | 16 |
| Res | Res | Res | Res | | | | | | | HT | | | | | |
| | | | | RW | RW | RW | RW | RW | RW | RW | RW | RW | RW | RW | RW |
| 15 | 14 | 13 | 12 | 11 | 10 | 9 | 8 | 7 | 6 | 5 | 4 | 3 | 2 | 1 | 0 |
| Res | Res | Res | Res | | | | | | | LT | | | | | |
| | | | | RW | RW | RW | RW | RW | RW | RW | RW | RW | RW | RW | RW |
| Bit | Name | R/W | Reset<br>Value | Function |
|-------|--------------|-----|----------------|----------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------|
| 31:28 | Re<br>served | | | |
| 27:16 | HT[11:0] | RW | 0xFFF | Analog Watchdog High Threshold<br>Software configurable to define analog watchdog high threshold<br>Software is allowed to write these bits only when ADSART = 0 (to ensure no<br>conversions are in progress) |
| 15:12 | Re<br>served | | | |
| 11:0 | LT[11:0] | RW | 0x000 | Analog Watchdog Low Threshold<br>Software configurable to define analog watchdog low threshold<br>Software is allowed to write these bits only when ADSART = 0 (to ensure no<br>conversions are in progress) |
## <span id="page-136-1"></span>**13.10.8. ADC channel selection register (ADC\_CHSELR)**
#### **Address offset:** 0x28
| 31 | 30 | 29 | 28 | 27 | 26 | 25 | 24 | 23 | 22 | 21 | 20 | 19 | 18 | 17 | 16 |
|----|----|----|----|----|----|------|------|------|------|------|------|------|------|------|------|
| Re | Re | Re | Re | Re | Re | Res | Res | Res | Res | Res | Res | Res | Res | Res | Res |
| s | s | s | s | s | s | | | | | | | | | | |
| | | | | | | | | | | | | | | | |
| | | | | | | | | | | | | | | | |
| 15 | 14 | 13 | 12 | 11 | 10 | 9 | 8 | 7 | 6 | 5 | 4 | 3 | 2 | 1 | 0 |
| Re | Re | Re | Re | Re | Re | CHS | CHS | CHS | CHS | CHS | CHS | CHS | CHS | CHS | CHS |
| s | s | s | s | s | s | EL 9 | EL 8 | EL 7 | EL 6 | EL 5 | EL 4 | EL 3 | EL 2 | EL 1 | EL 0 |
| Bit | Name | R/W | Reset Value | Function |
|-------|----------|-----|-------------|------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------|
| 31:14 | Reserved | | 0 | |
| 13:10 | Reserved | RW | 0 | This bit is writable and readable,and has no actual func<br>tion. |
| 9 | CHSEL9 | RW | 0 | Channel 9 (VREFINT) select enable<br>0: Channel 9 is not selected for conversion<br>1: Channel 9 is selected for conversion<br>Software is allowed to write this bit only if ADSART = 0<br>(to ensure no conversions are in progress) |
| 8 | CHSEL8 | RW | 0 | Channel 8 (TS) select enable<br>0: Channel 8 is not selected for conversion<br>1: Channel 8 is selected for conversion<br>Software is allowed to write this bit only if ADSART = 0<br>(to ensure no conversions are in progress) |
| 7:0 | CHSELx | RW | 0x0000 | Channel selection<br>These bits are software configurable to define the se<br>quence conversion channel<br>0: Input channel-x is not selected for conversion<br>1: Input channel-x is selected for conversion<br>Software is allowed to write these bits only when AD<br>SART = 0 (to ensure no conversions are in progress) |
## <span id="page-137-0"></span>**13.10.9. ADC data register (ADC\_DR)**
#### **Address offset:** 0x40
| Reset value: 0x0000 0000 | | | | | | | | | | | | | | | |
|--------------------------|------------|-----|-----|-----|-----|-----|-----|-----|-----|-----|-----|-----|-----|-----|-----|
| 31 | 30 | 29 | 28 | 27 | 26 | 25 | 24 | 23 | 22 | 21 | 20 | 19 | 18 | 17 | 16 |
| Res | Res | Res | Res | Res | Res | Res | Res | Res | Res | Res | Res | Res | Res | Res | Res |
| | | | | | | | | | | | | | | | |
| 15 | 14 | 13 | 12 | 11 | 10 | 9 | 8 | 7 | 6 | 5 | 4 | 3 | 2 | 1 | 0 |
| | DATA[15:0] | | | | | | | | | | | | | | |
| R | R | R | R | R | R | R | R | R | R | R | R | R | R | R | R |
| | | | | | | | | | | | | | | | |
| Bit | Name | R/W | Reset Value | Function |
|-------|------------|-----|-------------|------------------------------------------------------------------------------------------------------------------------------------------------------------------------|
| 31:16 | Reserved | | | |
| 15:0 | DATA[15:0] | R | 0x00 | Converted data<br>This bit is read-only. The conversion result of the last con<br>verted channel is placed in this register. Data is left-aligned<br>or right-aligned. |
### <span id="page-137-1"></span>**13.10.10. ADC calibration configuration and status registers (ADC\_CCSR)**
#### **Address offset:** 0x44
| 31 | 30 | 29 | 28 | 27 | 26 | 25 | 24 | 23 | 22 | 21 | 20 | 19 | 18 | 17 | 16 |
|-------|-------|-------------|----|-------|----|----|----|----|----|----|----|----|----|----|----|
| CALON | CALSU | OFFSU | Re | Res | Re | Re | Re | Re | Re | Re | Re | Re | Re | Re | Re |
| | C | C | s | | s | s | s | s | s | s | s | s | s | s | s |
| R | RC_W1 | RC_W1 | | | | | | | | | | | | | |
| 15 | 14 | 13 | 12 | 11 | 10 | 9 | 8 | 7 | 6 | 5 | 4 | 3 | 2 | 1 | 0 |
| CALSE | CAL | | | CALSE | Re | Re | Re | Re | Re | Re | Re | Re | Re | Re | Re |
| T | BYP | CALSMP[2:0] | | L | s | s | s | s | s | s | s | s | s | s | s |
| RW | | RW | | RW | | | | | | | | | | | |
| Bit | Name | R/W | Reset Value | Function |
|-----|--------|-------|-------------|-------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------|
| 31 | CALON | R | 0 | Calibration flag, indicating that ADC calibra<br>tion is in progress.<br>1: ADC calibration in progress<br>0: ADC calibration has ended or ADC cali<br>bration has not been started |
| 30 | CALSUC | RC_W1 | 0 | Capacitance calibration status bit.<br>Indicates whether ADC capacitance calibra<br>tion was successful. Hardware setting 1; Soft<br>ware write 1 set to 0;<br>CALON=0, CALSEL=0,CALSUC=1: invalid<br>state<br>CALON=0, CALSEL=0, CALSUC=0:CAPs<br>calibration not performed.<br>CALON=0, CALSEL=1, CALSUC =1: ADC<br>CAPs calibration successful<br>CALON=0, CALSEL=1, CALSUC =0: ADC<br>CAPs calibration failed |
| 29 | OFFSUC | RC_W1 | 1'b0 | Offset calibration status bit。<br>Indicates whether ADC capacitance calibra<br>tion was successful. Hardware setting 1; Soft<br>ware write 1 set to 0;<br>CALON=0, CALSEL=0,OFFSUC=0: ADC<br>OFFSET calibration failed<br>CALON=0, CALSEL=0, OFFSUC=1:ADC<br>OFFSET calibration successful |
| Bit | Name | R/W | Reset Value | Function |
|-------|-------------|------|-------------|------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------|
| | | | | CALON=0, CALSEL=1,OFFSUC=1: ADC<br>OFFSET calibration successful<br>CALON=0, CALSEL=1, OFFSUC=0:ADC<br>OFFSETcalibration failed |
| 29:16 | Reserved | - | 0 | - |
| | | | | Calibration factor selection<br>Software writers 1 and sets it to 1 when AD<br>CAL is 0.The hardware is set to 0 when AD<br>CAL is valid or ADSTART is valid. |
| 15 | CALSET | R_W1 | 1'h0 | 1:Set CAL_CXIN data as the final calibra<br>tion data |
| | | | | 0 : Close the channels of CAL_CXIN to<br>CAL_CXOUT ,Select the results that gener<br>ated internally by the calibration circuit. |
| 14 | CALBYP | R_W1 | 1'h0 | Calibration factor bypass.<br>When CAL is 0, the software writes 1 and<br>sets it to 1. When CAL is valid or injection/rule<br>channel SWSTART, JWSTART is valid, the<br>hardware is set to 0.<br>1:The calibration result is a reset value. |
| | | | | 0:The calibration result is either the self cal<br>ibration result or the input value of the calibra<br>tion factor |
| 13:12 | CALSMP[2:0] | RW | 0 | Calibration sample time seletion<br>Configure the number of clock cycles for the<br>sampling phase of calibration based on the<br>following information:<br>00: 2 ADC clock cycles<br>01: 4 ADC clock cycles<br>10: 8 ADC clock cycles<br>11: 1 ADC clock cycle<br>The longer the cycle of configuring SMP dur<br>ing calibration, the more accurate the calibra<br>tion result, but this configuration will bring<br>the problem of prolonged calibration cycle |
| 11 | CALSEL | RW | 0 | Calibration content selection bit, used to se<br>lect the content that needs to be calibrated<br>1: Calibrate OFFSET and linearity<br>0: Only calibrate OFFSET |
| 10:0 | Reserved | - | 0 | - |
## <span id="page-138-0"></span>**13.10.11. ADC common configuration register (ADC\_CCR)**
#### **Address offset:** 0x308
| 31 | 30 | 29 | 28 | 27 | 26 | 25 | 24 | 23 | 22 | 21 | 20 | 19 | 18 | 17 | 16 |
|-----|-----|-----|-----|-----|-----|-----|-----|------|--------|-----|-----|-----|-----|-----|-----|
| Res | Res | Res | Res | Res | Res | Res | Res | TSEN | VREFEN | Res | Res | Res | Res | Res | Res |
| | | | | | | | | RW | RW | | | | | | |
| | | | | | | | | | | | | | | | |
| 15 | 14 | 13 | 12 | 11 | 10 | 9 | 8 | 7 | 6 | 5 | 4 | 3 | 2 | 1 | 0 |
| Res | Res | Res | Res | Res | Res | Res | Res | Res | Res | Res | Res | Res | Res | Res | Res |
| Bit | Name | R/W | Reset Value | Function |
|-------|----------|-----|-------------|-------------------------------------------------------------------------------------------------------------------------------------|
| 31:24 | Reserved | | | |
| 23 | TSEN | RW | 0 | Temperature sensor enable bit, software can set and clear<br>this bit, enable/disable temperature sensor<br>0: Disable<br>1: enable |
| | | | | Software is allowed to write these bits only when ADSART=<br>0 (to ensure no conversions are in progress) |
|------|----------|----|---|-------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------|
| 22 | VREFEN | RW | 0 | Reference Vrefint enable bit, software can set and clear<br>this bit, enable/disable reference Vrefint<br>0: Disable<br>1: enable<br>Software is allowed to write these bits only when ADSART<br>= 0 (to ensure no conversions are in progress) |
| 21:0 | Reserved | | | |
## <span id="page-139-0"></span>**13.10.12. ADC register map**
| O<br>ff<br>s<br>et | Reg<br>ister | 31 | 30 | 29 | 28 | 27 | 26 | 25 | 24 | 23 | 22 | 21 | 20 | 19 | 18 | 17 | 16 | 15 | 14 | 13 | 12 | 11 | 10 | 9 | 8 | 7 | 6 | 5 | 4 | 3 | 2 | 1 | 0 |
|--------------------|------------------------|-------|--------|--------------|------|-------------|------|------|------|-------|----------|------|------|------|------|------|--------|---------|---------|--------------|--------|--------|---------|--------|------------|-----------------|----------|--------------|--------------|---------|---------|-----------|--------|
| 0x<br>0 | ADC<br>_ISR | Res. | Res. | Res. | Res. | Res. | Res. | Res. | Res. | Res. | Res. | Res. | Res. | Res. | Res. | Res. | Res. | Res. | Res. | Res. | Res. | Res. | Res. | Res. | Res. | AWD | Res. | Res. | OVR | EOSEQ | EOC | EOSMP | Res. |
| 0 | Re<br>set<br>value | | | | | | | | | | | | | | | | | | | | | | | | | 0 | | | 0 | 0 | 0 | 0 | |
| 0x<br>0 | ADC<br>_IER | Res. | Res. | Res. | Res. | Res. | Res. | Res. | Res. | Res. | Res. | Res. | Res. | Res. | Res. | Res. | Res. | Res. | Res. | Res. | Res. | Res. | Res. | Res. | Res. | AWDIE | Res. | Res. | OVRIE | EOSEQIE | EOCIE | EOSMPIE | Res. |
| 4 | Re<br>set<br>value | | | | | | | | | | | | | | | | | | | | | | | | | 0 | | | 0 | 0 | 0 | 0 | |
| 0x<br>0 | ADC<br>_CR | ADCAL | Res. | Res. | Res. | Res. | Res. | Res. | Res. | Res. | Res. | Res. | Res. | Res. | Res. | Res. | Res. | Res. | Res. | Res. | Res. | Res. | Res. | Res. | Res. | Verfbuff_sel | | Vref_buffere | ADSTP | MSBSEL | ADSTART | Res. | ADEN |
| 8 | Re<br>set<br>value | 0 | | | | | | | | | | | | | | | | | | | | | | | | 0 | 0 | 0 | 0 | 0 | 0 | | 0 |
| 0x<br>0<br>C | ADC<br>_CF<br>GR1 | Res. | Res. | | | AWDCH [3:0] | | Res. | Res. | AWDEN | AWDSGL | Res. | Res. | Res. | Res. | Res. | DISCEN | Res. | WAIT | CONT | OVRMOD | Res. | Res. | Res. | | EXTSEL<br>[2:0] | | ALIGN | RES_SEL[1:0] | | SCANDIR | Res | Res |
| | Re<br>set<br>value | | | 0 | 0 | 0 | 0 | | | 0 | 0 | | | | | | 0 | | 0 | 0 | 0 | | | | 0 | 0 | 0 | 0 | 0 | 0 | 0 | | |
| 0x<br>1 | ADC<br>_CF<br>GR2 | | | CKMODE [3:0] | | Res. | Res. | Res. | Res. | Res. | Res. | Res. | Res. | Res. | Res. | Res. | Res. | Res. | Res. | Res. | Res. | Res. | Res. | Res. | Res. | Res. | Res. | Res. | Res. | Res. | Res. | Res. | Res. |
| 0 | Re<br>set<br>value | 0 | 0 | 0 | 0 | | | | | | | | | | | | | | | | | | | | | | | | | | | | |
| 0x<br>1 | ADC<br>_SM<br>PR | Res. | Res. | Res. | Res. | Res. | Res. | Res. | Res. | Res. | Res. | Res. | Res. | Res. | Res. | Res. | Res. | Res. | Res. | Res. | Res. | Res. | Res. | Res. | Res. | Res. | Res. | Res. | Res. | Res. | | SMP [2:0] | |
| 4 | Re<br>set<br>value | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | 0 | |
| 0x<br>2 | ADC<br>_TR<br>Re | Res. | Res. | Res. | Res. | | | | | | HT[11:0] | | | | | | | Res. | Res. | Res. | Res. | | | | | | LT[11:0] | | | | | | |
| 0 | set<br>value | | | | | 1 | 1 | 1 | 1 | 1 | 1 | 1 | 1 | 1 | 1 | 1 | 1 | | | | | 0 | 0 | 0 | 0 | 0 | 0 | 0 | 0 | 0 | 0 | 0 | 0 |
| 0x<br>2 | ADC<br>_CH<br>SEL<br>R | Res. | Res. | Res. | Res. | Res. | Res. | Res. | Res. | Res. | Res. | Res. | Res. | Res. | Res. | Res. | Res. | Res. | Res. | Res. | Res | Res | CHSEL10 | CHSEL9 | CHSEL8 | CHSEL7 | CHSEL6 | CHSEL5 | CHSEL4 | CHSEL3 | CHSEL2 | CHSEL1 | CHSEL0 |
| 8 | Re<br>set<br>value | | | | | | | | | | | | | | | | | | | | | | 0 | 0 | 0 | 0 | 0 | 0 | 0 | 0 | 0 | 0 | 0 |
| 0x | ADC<br>_DR | Res. | Res. | Res. | Res. | Res. | Res. | Res. | Res. | Res. | Res. | Res. | Res. | Res. | Res. | Res. | Res. | | | | | | | | DATA[15:0] | | | | | | | | |
| 4<br>0 | Re<br>set<br>value | | | | | | | | | | | | | | | | | 0 | 0 | 0 | 0 | 0 | 0 | 0 | 0 | 0 | 0 | 0 | 0 | 0 | 0 | 0 | 0 |
| 0x<br>4<br>4 | ADC<br>_CC<br>SR | CALON | CAPSUC | OFFSUC | Res. | Res. | Res. | Res. | Res. | Res. | Res. | Res. | Res. | Res. | Res. | Res. | Res. | CALSET. | CALBYP. | CALSMP [1:0] | | CALSEL | Res. | Res. | Res. | Res. | Res. | Res. | Res. | Res. | Res. | Res. | Res. |
| O<br>ff<br>s<br>et | Reg<br>ister | 31 | 30 | 29 | 28 | 27 | 26 | 25 | 24 | 23 | 22 | 21 | 20 | 19 | 18 | 17 | 16 | 15 | 14 | 13 | 12 | 11 | 10 | 9 | 8 | 7 | 6 | 5 | 4 | 3 | 2 | 1 | 0 |
|--------------------|--------------------|------|------|------|------|------|------|------|------|------|--------|------|------|------|------|------|------|------|------|------|------|------|------|------|------|------|------|------|------|------|------|------|------|
| | Re<br>set<br>value | 0 | 0 | 0 | | | | | | | | | | | | | | 0 | 0 | 0 | 0 | 0 | | | | | | | | | | | |
| 0x<br>3 | ADC<br>_CC<br>R | Res. | Res. | Res. | Res. | Res. | Res. | Res. | Res. | TSEN | VREFEN | Res. | Res. | Res. | Res. | Res. | Res. | Res. | Res. | Res. | Res. | Res. | Res. | Res. | Res. | Res. | Res. | Res. | Res. | Res. | Res. | Res. | Res. |
| 0<br>8 | Re<br>set<br>value | | | | | | | | | 0 | 0 | | | | | | | | | | | | | | | | | | | | | | |
# <span id="page-141-0"></span>**14. Comparator (COMP)**
## <span id="page-141-1"></span>**14.1. Introduction**
Two general purpose comparators (general purpose comparators) COMP are integrated in the chip, namely COMP1 and COMP2. These two modules can be used as separate modules or combined with timer.
Comparators can be used as follows:
- Triggered by analog signal to generate low power mode wake-up function
- Analog signal conditioning
- Current control loop of Cycle by cycle when connected with PWM output from timer
## <span id="page-141-2"></span>**14.2. COMP main features**
- Each comparator has configurable positive or negative input for flexible voltage selection
- Multiple I/O pins
- VREFCMP:VREFBUF/16th order voltage division of power supply voltage
- Output can be connected to I/O or timer input as trigger
- OCREF\_CLR event (cycle by cycle current control)
- Brake for fast PWM shutdown
- COMP1 and COMP2 can be combined into window COMP
- Each COMP has interrupt generation capability, which is used as wake-up (via EXTI) from low-power modes (sleep and stop modes)
- Provide software to configure digital filtering time to enhance chip anti-interference ability
## <span id="page-142-0"></span>**14.3. COMP function description**
#### <span id="page-142-1"></span>**14.3.1. COMP diagram**
![](_page_142_Figure_3.jpeg)
Figure 14-1 Comparator architecture block diagram
## <span id="page-142-2"></span>**14.3.2. COMP pins and internal signals**
The I/O used as comparator input must be configured in analog mode in the GPIO register. The comparator output can be connected to the I/O pin through the alternate function channel (al-
ternate function) on the GPIO.
The outputs can also be internally connected to the inputs of various timers for the following purposes:
- When the brake input is connected, the emergency shutdown of the PWM signal
- Cycle-by-cycle current control using OCREF\_CLR input
- Input capture for timing measurements
## <span id="page-142-3"></span>**14.3.3. COMP reset and clock**
The COMP module has two clock sources:
1) PCLK(APB clock),used to provide the clock to the configuration register
2) COMP clock, used for the clock of the circuit after the analog comparator output (the latch circuit of the analog output, the glitch filter circuit, etc.), which can be selected as PCLK, LSE or LSI. When you need to work in stop mode, choose LSE or LSI.
The reset signal sources of the COMP module are:
- 1. The reset signal of the COMP module includes the APB reset source and the COMP module software reset source.
- 2. APB reset, used for resetting the COMP register.
- 3. COMP software reset, used for resetting the analog comparator output circuit (the latch circuit of the analog output, the glitch filter circuit, etc.).
#### <span id="page-143-0"></span>**14.3.4. Window comparator**
The role of the Window comparator is to monitor whether the analog voltage is within the low and high thresholds.
A window comparator can be created using two comparators. The monitored analog voltage is connected to the non-inverting (+) inputs of both comparators at the same time, and the high and low thresholds are connected to the inverting inputs (-) of the two comparators, respectively.
By enabling the WINMODE bit, the non-inverting (+ input) of the two comparators can be connected together to save one I/O pin.
![](_page_143_Figure_10.jpeg)
Figure 14-2 window comparator
#### <span id="page-143-1"></span>**14.3.5. Low-power mode**
| Mode | Discreption |
|-------|------------------------------------------------------------------------------------|
| Sleep | No impact on COMP.<br>Comparator interrupt can cause the device to exit Sleep mode |
| Stop | No impact on COMP<br>Comparator interrupt can cause the device to exit Sleep mode |
## <span id="page-143-2"></span>**14.3.6. Comparator filtering**
If the working environment of the chip is harsh, the output of the hysteresis comparator will produce noise signals. By enabling the digital filtering module, any noise signal with a pulse width less than the FRx. FLTCNT [15:0] set time in the output waveform of the hysteresis comparator can be filtered out. If the digital filtering module is prohibited, the input and output signals of the digital filtering module are the same.
Note that this setting should be done before COMP\_EN is enabled.
The filtering diagram is as follows:
![](_page_144_Figure_4.jpeg)
Figure 14-3 COMP filter
## <span id="page-144-0"></span>**14.3.7. COMP interrupt**
The comparator output is internally connected to the EXTI controller (extended interrupts and events). Each comparator has a separate EXTI line (17 and 18) and can generate interrupts or events. The same mechanism is used for wake-up from low power.
## <span id="page-144-1"></span>**14.4. COMP registers**
## <span id="page-144-2"></span>**14.4.1. COMP1 control and status registers (COMP1\_CSR)**
#### **Address offset:**0x00
| | | | | Reset value:0x0000 0000 | | | | | | | | | | | |
|----------------------|-------|---------|---------|-------------------------|-----------|---------|---------|-----------------|---------|------------|---------|---------|---------|---------|------------------|
| 31 | 30 | 29 | 28 | 27 | 26 | 25 | 24 | 23 | 22 | 21 | 20 | 19 | 18 | 17 | 16 |
| Re | COMP_ | Re | Re | COMP_VC | COMP_VCDI | | | COMP_VCDIV[3:0] | | Res | Re | Re | Re | Re | Res |
| s | OUT | s | s | SEL | V_EN | | | | | | s | s | s | s | |
| R | R | - | - | RW | RW | R | R | R | R | - | - | - | - | - | - |
| W | | | | | | W | W | W | W | | | | | | |
| 15 | 14 | 13 | 12 | 11 | 10 | 9 | 8 | 7 | 6 | 5 | 4 | 3 | 2 | 1 | 0 |
| PO<br>LA<br>RIT<br>Y | Res | Re<br>s | Re<br>s | WINMODE | Res | Re<br>s | Re<br>s | Re<br>s | Re<br>s | INMS<br>EL | Re<br>s | Re<br>s | Re<br>s | Re<br>s | COM<br>P1<br>_EN |
| R<br>W | - | - | - | RW | - | - | - | - | - | RW | - | - | - | - | RW |
| Bit | Name | R/W | Reset Value | Function |
|-------|------------|-----|-------------|------------------------------------------------------------------------------------------------------------|
| 31 | Reserved | | | |
| 30 | COMP_OUT | R | | COMP1 output status<br>This bit is read-only and reflects the polarity-selected out<br>put level of COMP1. |
| 29:28 | Reserved | | | |
| 27 | COMP_VCSEL | RW | 0 | VREFCMP reference source selection.<br>VREFCMP is enabled by VREFINT_EN. |
| Bit | Name | R/W | Reset Value | Function |
|-------|-----------------|-----|-------------|-----------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------|
| | | | | 0: VREFBUF<br>1: VCC, VREFINT and VREFBUF is not available at<br>COMP_VCSEL=1. |
| 26 | COMP_VCDIV_EN | RW | | VREFCMP enable, active high.<br>COMP_VCDIV_EN=1 will enable VREFINT at the same<br>time internally by PMU if COMP_VCSEL=0 |
| 25:22 | COMP_VCDIV[3:0] | RW | 0111 | VREFCMP voltage divider configuration, VREFCMP is<br>divided from reference source (VREFBUF or VCC set by<br>COMP_VCSEL)<br>0: 1/16<br>1: 2/16<br>2: 3/16<br>3: 4/16<br>4: 5/16<br>5: 6/16<br>6: 7/16<br>7: 8/16<br>8: 9/16<br>9: 10/16<br>10: 11/16<br>11: 12/16<br>12: 13/16<br>13: 14/16<br>14: 15/16<br>15: 16/16 |
| 21:16 | Reserved | | | |
| 15 | POLARITY | RW | 0 | COMP1 polarity selection<br>0:do not reverse<br>1:Reverse |
| 14:12 | Reserved | | | |
| 11 | WINMODE | RW | 0 | COMP1 window mode enable<br>0:Close WINDOW mode, The forward input of COMP1<br>is COMP1_ INP<br>1:Open WINDOW mode,The forward input of COMP1<br>is consistent with the forward input of COMP2 |
| 10:6 | Reserved | | | |
| 5 | INNSEL[1:0] | RW | 00 | Negative input selection for COMP1<br>0:PB0<br>1:PB1 |
| 4:1 | Reserved | | | |
| 0 | COMP1_EN | RW | 0 | COMP1 enable bit<br>0:Disable<br>1:Enable |
## <span id="page-145-0"></span>**14.4.2. COMP1 filter register (COMP1\_FR)**
#### **Address offset:**0x04
| 31 | 30 | 29 | 28 | 27 | 26 | 25 | 24 | 23 | 22 | 21 | 20 | 19 | 18 | 17 | 16 |
|---------------|-----|-----|-----|-----|-----|-----|-----|-----|-----|-----|-----|-----|-----|-----|--------|
| FLTCNT1[15:0] | | | | | | | | | | | | | | | |
| RW | RW | RW | RW | RW | RW | RW | RW | RW | RW | RW | RW | RW | RW | RW | RW |
| 15 | 14 | 13 | 12 | 11 | 10 | 9 | 8 | 7 | 6 | 5 | 4 | 3 | 2 | 1 | 0 |
| Res | Res | Res | Res | Res | Res | Res | Res | Res | Res | Res | Res | Res | Res | Res | FLTEN1 |
| | | | | | | | | | | | | | | | RW |
| Bit | Name | R/W | Reset Value | Function |
|-------|---------|-----|-------------|-------------------------------------------------------------------------------------------------------------------------------------------------------|
| 31:16 | FLTCNT1 | RW | 0x0 | Comparator 1 Sample Filter Counter<br>The sampling clock is APB or LSI or LSE. The filter count<br>value is configurable. When the number of sampling |
| Bit | Name | R/W | Reset Value | Function | | | | | | |
|------|----------|-----|-------------|--------------------------------------------------------------------------------------------------------------------------------------------------------------------------------|--|--|--|--|--|--|
| | | | | times reaches the filter count value, the results are output<br>consistently.<br>Sampling count period = FLTCNT[15:0] | | | | | | |
| 15:1 | Reserved | | 0x0 | | | | | | | |
| 0 | FLTEN1 | RW | 0x0 | Comparator 1 digital filter function configuration<br>0: Disable digital filter function<br>1: Enable digital filter function<br>Note: This bit must be set when COMP1_EN is 0 | | | | | | |
## <span id="page-146-0"></span>**14.4.3. COMP2 control and status registers (COMP2\_CSR)**
#### **Address offset:**0x10
**Reset value:**0x0000 0000
| 31 | 30 | 29 | 28 | 27 | 26 | 25 | 24 | 23 | 22 | 21 | 20 | 19 | 18 | 17 | 16 |
|-----|---------|----|----|----|----|-------|----|----|----|-------|----|----|----|----|------|
| Res | COMP_OU | Re | Re | Re | Re | Res | Re | Re | Re | Res | Re | Re | Re | Re | Res |
| | T | s | s | s | s | | s | s | s | | s | s | s | s | |
| | R | | | | | | | | | | | | | | |
| 15 | 14 | 13 | 12 | 11 | 10 | 9 | 8 | 7 | 6 | 5 | 4 | 3 | 2 | 1 | 0 |
| PO | | | | | | | | | | | | | | | COMP |
| LAR | Res | Re | Re | Re | Re | INPSE | Re | Re | Re | INMSE | Re | Re | Re | Re | 2 |
| ITY | | s | s | s | s | L | s | s | s | L | s | s | s | s | _EN |
| RW | | - | - | | - | RW | | | | RW | | | | | RW |
| Bit | Name | R/W | Reset<br>Value | Function |
|-------|----------|-----|----------------|-----------------------------------------------------------------------------------------------------------|
| 31 | Reserved | | | |
| 30 | COMP_OUT | R | | COMP2 output status<br>This bit is read-only and reflects the polarity-selected output level<br>of COMP2. |
| 29:16 | Reserved | | | |
| | | | | COMP2 polarity selection |
| 15 | POLARITY | RW | | 0:do not reverse |
| | | | | 1:Reverse |
| 14:10 | Reserved | | | |
| | | | | COMP2 Signal selection for forward input |
| 9 | INPSEL | RW | | 0:PA3 |
| | | | | 1:VREFCMP |
| | | | | COMP2 Signal selection for negative input |
| 5 | INMSEL | RW | | 0:PA4 |
| | | | | 1:PA3 |
| 4:1 | Reserved | | | |
| | | | | COMP2 enable bit<br>Software is readable and writable (if not locked) |
| 0 | COMP2_EN | RW | | 0:Disable |
| | | | | 1:Enable |
## <span id="page-146-1"></span>**14.4.4. COMP2 filter register (COMP2\_FR)**
#### **Address offset:**0x14
| 31 | 30 | 29 | 28 | 27 | 26 | 25 | 24 | 23 | 22 | 21 | 20 | 19 | 18 | 17 | 16 |
|---------------|-----|-----|-----|-----|-----|-----|-----|-----|-----|-----|-----|-----|-----|-----|--------|
| FLTCNT2[15:0] | | | | | | | | | | | | | | | |
| RW | RW | RW | RW | RW | RW | RW | RW | RW | RW | RW | RW | RW | RW | RW | RW |
| 15 | 14 | 13 | 12 | 11 | 10 | 9 | 8 | 7 | 6 | 5 | 4 | 3 | 2 | 1 | 0 |
| Res | Res | Res | Res | Res | Res | Res | Res | Res | Res | Res | Res | Res | Res | Res | FLTEN2 |
| | | | | | | | | | | | | | | | RW |
| Bit | Name | R/W | Reset Value | Function |
|-------|---------------|-----|-------------|--------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------|
| 31:16 | FLTCNT2[15:0] | RW | 0x0 | Comparator 2 Sample Filter Counter<br>The sampling clock is APB or LSI or LSE. The filter count<br>value is configurable. When the number of sampling<br>times reaches the filter count value, the results are output<br>consistently.<br>Sampling count period = FLTCNT[15:0] |
| 15:1 | Reserved | | 0x00 | |
| 0 | FLTEN2 | RW | 0x0 | Comparator 2 digital filter function configuration<br>0: Disable digital filter function<br>1: Enable digital filter function<br>Note: This bit must be set when COMP2_EN is 0 |
## <span id="page-147-0"></span>**14.4.5. COMP register map**
| O<br>ff<br>s<br>et | Reg<br>ister | 31 | 30 | 29 | 28 | 27 | 26 | 25 | 24 | 23 | 22 | 21 | 20 | 19 | 18 | 17 | 16 | 15 | 14 | 13 | 12 | 11 | 10 | 9 | 8 | 7 | 6 | 5 | 4 | 3 | 2 | 1 | 0 |
|--------------------|--------------------|------|----------|------|------|------------|------------|------|---------------|--------|------|------|------|------------------|------|------|------|----------|------|------|------|---------|------|-------------|------|------|------|--------|------|------------------|------|------|----------|
| 0x<br>0<br>0 | COM<br>P1_<br>CSR | Res | COMP_OUT | Res. | Res. | COMP_VCSEL | COMP_VCDIV | _EN. | COMP_VCDIV | [3:0]. | | Res. | Res. | Res. | Res. | Res. | Res | Res | Res. | Res. | Res. | WINMODE | Res. | INPSEL[1:0] | | Res. | Res. | Res. | Res. | Res. | Res. | Res | COMP1_EN |
| | Re<br>set<br>value | 0 | 0 | | | 0 | 0 | 0 | 0 | 0 | 0 | | | | | | | | | | | 0 | | 0 | 0 | | | | | | | | 0 |
| 0x<br>0 | COM<br>P1_F<br>R | | | | | | | | FLTCNT1[15:0] | | | | | | | | | Res. | Res. | Res. | Res. | Res. | Res. | Res. | Res. | Res. | Res. | Res. | Res. | Res. | Res. | Res. | FLTEN1 |
| 4 | Re<br>set<br>value | 0 | 0 | 0 | 0 | 0 | 0 | 0 | 0 | 0 | 0 | 0 | 0 | 0 | 0 | 0 | 0 | | | | | | | | | | | | | | | | 0 |
| 0x<br>1<br>0 | COM<br>P2_<br>CSR | Res. | COMP_OUT | Res. | Res. | Res. | Res. | Res. | Res. | Res. | Res. | Res. | Res. | MODE[1:0]<br>Res | Res | Res. | Res. | POLARITY | Res. | Res. | Res. | Res. | Res. | INPSEL | Res. | Res. | Res. | INNSEL | Res. | MODE[1:0]<br>Res | Res | Res. | COMP2_EN |
| | Re<br>set<br>value | | 0 | | | | | | | | | | | | | | | 0 | | | | | | 0 | | | | 0 | | | | | 0 |
| 0x<br>1 | COM<br>P2_F<br>R | | | | | | | | FLTCNT2[15:0] | | | | | | | | | Res. | Res. | Res. | Res. | Res. | Res. | Res. | Res. | Res. | Res. | Res. | Res. | Res. | Res. | Res. | FLTEN2 |
| 4 | Re<br>set<br>value | 0 | 0 | 0 | 0 | 0 | 0 | 0 | 0 | 0 | 0 | 0 | 0 | 0 | 0 | 0 | 0 | | | | | | | | | | | | | | | | 0 |
## <span id="page-148-0"></span>**15. Advanced-control timer (TIM1)**
## <span id="page-148-1"></span>**15.1. TIM1 introduction**
The advanced-control timers (TIM1) consist of a 16-bit auto-reload counter driven by a programmable prescaler.
It may be used for a variety of purposes, including measuring the pulse lengths of input signals (input capture) or generating output waveforms (output compare, PWM, complementary PWM with deadtime insertion).
Pulse lengths and waveform periods can be modulated from a few microseconds to several milliseconds using the timer prescaler and the RCC clock controller prescalers.
The advanced-control (TIM1) and general-purpose (TIMx) timers are completely independent, and do not share any resources. They can be synchronized together.
## <span id="page-148-2"></span>**15.2. TIM1 main features**
- 16-bit up, down, up/down auto-reload counter.
- 16bit programmable frequency divider, allowing for 1 to 65535 frequency division of the clock frequency of the counter.
- Up to 4 independent channels for:
- Input capture
- Output compare
- PWM generation (Edge and Center-aligned Mode)
- One-pulse mode output
- Complementary outputs with programmable dead-time
- Synchronization circuit to control the timer with external signals and to interconnect several timers together.
- Repetition counter to update the timer registers only after a given number of cycles of the counter.
- Break input to put the timer's output signals in reset state or in a known state.
- Interrupt generation on the following events:
- Update: counter overflow/underflow, counter initialization (by software or internal/external trigger)
- Trigger event (counter start, stop, initialization or count by internal/external trigger)
- Input capture
- Output compare
- Break input
- Supports incremental (quadrature) encoder and hall-sensor circuitry for positioning purposes
- Trigger input for external clock or cycle-by-cycle current management
![](_page_149_Figure_1.jpeg)
Figure 15-1 Advanced-control timer block diagram
## <span id="page-149-0"></span>**15.3. TIM1 functional description**
## <span id="page-149-1"></span>**15.3.1. Time-base unit**
The main block of the programmable advanced-control timer is a 16-bit counter with its related autoreload register. The counter can count up, down or both up and down. The counter clock can be divided by a prescaler.
The counter, the auto-reload register and the prescaler register can be written or read by software. This is true even when the counter is running.
The time-base unit includes:
- Counter register (TIM1\_CNT)
- Prescaler register (TIM1\_PSC)
- Auto-reload register (TIM1\_ARR)
- Repetition counter register (TIM1\_RCR)
The auto-reload register is preloaded. Writing to or reading from the auto-reload register accesses the preload register. The content of the preload register are transferred into the shadow register permanently or at each update event (UEV), depending on the auto-reload preload enable bit (ARPE) in TIMx\_CR1 register. The update event is sent when the counter reaches the overflow (or underflow
when downcounting) and if the UDIS bit equals 0 in the TIMx\_CR1 register. It can also be generated by software.
The counter is clocked by the prescaler output CK\_CNT, which is enabled only when the counter enable bit (CEN) in TIM1\_CR1 register is set.
Note that the counter starts counting 1 clock cycle after setting the CEN bit in the TIM1\_CR register. **Prescaler description**
The prescaler can divide the counter clock frequency by any factor between 1 and 65536. It is based on a 16-bit counter controlled through a 16-bit register (in the TIMx\_PSC register).It can be changed on the fly as this control register is buffered. The new prescaler parameter is taken into account at the next update event.
Figure 15-2 and Figure 15-3 give some examples of the counter behavior when the prescaler parameter is changed on the fly:
![](_page_150_Figure_6.jpeg)
Figure 15-2 Counter timing diagram with prescaler division change from 1 to 2
![](_page_150_Figure_8.jpeg)
Figure 15-3 Counter timing diagram with prescaler division change from 1 to 4
## <span id="page-151-0"></span>**15.3.2. Counter modes**
#### **Upcounting mode**
In upcounting mode, the counter counts from 0 to the auto-reload value, then restarts from 0 and generates a counter overflow event.
If the repetition counter is used, the update event (UEV) is generated after upcounting is repeated for the number of times programmed in the repetition counter register plus one. Else the update event is generated at each counter overflow.
Setting the UG bit in the TIMx\_EGR register (by software or by using the slave mode controller) also generates an update event.
Setting the UDIS bit in the TIMx\_CR1 register allows the software to disable update events; this is to avoid updating the shadow register when writing new values to the preload register. No update events will be generated until the UDIS bit is cleared to zero. However, the counter restarts from 0 and the prescaler restarts from 0 (but the value of the prescaler remains unchanged). In addition, if the URS bit in the TIMx\_CR1 register is set (select update request), setting the UG bit will generate an update event UEV, but the hardware does not set the UIF flag (i.e., no interrupt is generated). This is to avoid generating both update and capture interrupts when the counter is cleared in capture mode.
When an update event occurs, all the registers are updated and the update flag (UIF bit in TIMx\_SR register) is set (depending on the URS bit):
- The repetition counter is reloaded with the content of TIMx\_RCR register
- The auto-reload shadow register is updated with the preload value (TIMx\_ARR)
- The buffer of the prescaler is reloaded with the preload value (content of the TIMx\_PSC register)
The following figures show some examples of the counter behavior for different clock frequencies when TIMx\_ARR = 0x36.
| CK_PSC | |
|----------------------------|---------------------------------------------------------------------------------------------|
| CNT_EN | |
| Timer clock = CK_CNT | |
| Counter register | 3 1<br>3 2<br>3 3<br>3 5<br>3 6<br>0 0<br>0 1<br>0 2<br>0 4<br>0 5<br>0 6 0 7<br>3 4<br>0 3 |
| Counter overflow | |
| Update event(UEV) | |
| Update interrupt flag(UIF) | |
Figure 15-4 Counter timing diagram, internal clock divided by 1
| CK_PSC | |
|----------------------------|----------------------|
| CNT_EN | |
| Timer clock = CK_CNT | |
| | 0035<br>0036<br>0034 |
| Counter overflow | |
| Update event(UEV) | |
| Update interrupt flag(UIF) | |
Figure 15-5 Counter timing diagram, internal clock divided by 2
| CK_PSC | |
|----------------------------|------------------------------|
| CNT_EN | |
| Timer clock = CK_CNT | |
| Counter register | 0035<br>0036<br>0000<br>0001 |
| Counter overflow | |
| Update event(UEV) | |
| Update interrupt flag(UIF) | |
| Counter register | 0035<br>0036<br>0000<br>0001<br>0002<br>0003<br>0034 |
|----------------------------|-----------------------------------------------------------------|
| Counter overflow | |
| Update event(UEV) | |
| Update interrupt flag(UIF) | |
| | Figure 15-5 Counter timing diagram, internal clock divided by 2 |
| | |
| CK_PSC | |
| CNT_EN | |
| Timer clock = CK_CNT | |
| Counter register | 0035<br>0036<br>0000<br>0001 |
| Counter overflow | |
| Update event(UEV) | |
| Update interrupt flag(UIF) | |
| | Figure 15-6 Counter timing diagram, internal clock divided by 4 |
| | |
| CK_PSC | |
| CNT_EN | |
| Timer clock = CK_CNT | |
| Counter register | 1<br>F<br>2<br>0<br>0<br>0 |
| Counter overflow | |
| Update event(UEV) | |
| Update interrupt flag(UIF) | |
| | Figure 15-7 Counter timing diagram, internal clock divided by N |
| | |
| | |
| | |
| | |
| | |
| | |
| | |
| | |
| | |
Figure 15-7 Counter timing diagram, internal clock divided by N
| CK_PSC | | |
|-------------------------------|-------------------------------------------------------------|------------------------------|
| CNT_EN | | |
| Timer clock = CK_CNT | | |
| Counter register | 3 1<br>3 2<br>3 3<br>3 5<br>3 6<br>0 0<br>0 1<br>0 2<br>3 4 | 0 4<br>0 5<br>0 6 0 7<br>0 3 |
| Counter overflow | | |
| Update event(UEV) | | |
| Update interrupt flag(UIF) | | |
| Auto-reload preload register | FF | 3 6 |
| Write a new value in TIMx_ARR | | |
Figure 15-8 Counter timing diagram, update event when ARPE = 0 (TIMx\_ARR no preloaded)
| CK_PSC | | | | |
|------------------------------|-------------------------------|----------------|--------------------------------------|--------------------------------|
| CNT_EN | | | | |
| Timer clock = CK_CNT | | | | |
| Counter register | F0<br>F1<br>F2 | F4<br>F5<br>F3 | 0<br>0<br>0<br>1<br>0<br>2<br>0<br>3 | 0<br>4<br>0<br>5 0<br>6 0<br>7 |
| Counter overflow | | | | |
| Update event(UEV) | | | | |
| Update interrupt flag(UIF) | | | | |
| Auto-reload preload register | F5 | | 3<br>6 | |
| Auto-reload shadow register | | F5 | | 3<br>6 |
| | Write a new value in TIMx_ARR | | | |
Figure 15-9 Counter timing diagram, update event when ARPE = 1 (TIMx\_ARR preloaded)
#### **Downcounting mode**
In downcounting mode, the counter counts from the auto-reload value down to 0, then restarts from the auto-reload value and generates a counter underflow event.
If the repetition counter is used, the update event (UEV) is generated after downcounting is repeated for the number of times programmed in the repetition counter register (TIMx\_RCR). Else the update event is generated at each counter underflow.
Setting the UG bit in the TIMx\_EGR register (by software or by using the slave mode controller) also generates an update event.
The UEV update event can be disabled by software by setting the UDIS bit in TIMx\_CR1 register. This is to avoid updating the shadow registers while writing new values in the preload registers. Then no update event occurs until UDIS bit has been written to 0. However, the counter restarts from the current auto-reload value, whereas the counter of the prescaler restarts from 0 (but the prescale rate doesn't change).
In addition, if the URS bit (update request selection) in TIMx\_CR1 register is set, setting the UG bit generates an update event UEV but without setting the UIF flag (thus no interrupt or DMA request is sent). This is to avoid generating both update and capture interrupts when clearing the counter on the capture event.
When an update event occurs, all the registers are updated and the update flag (UIF bit in TIMx\_SR register) is set (depending on the URS bit):
- The repetition counter is reloaded with the content of TIMx\_RCR register
- The buffer of the prescaler is reloaded with the preload value (The TIMx\_PSC register value)
- The auto-reload active register is updated with the preload value (content of the TIMx\_ARR register)
Note: the auto-reload is updated before the counter is reloaded, so that the next period is the expected one.
The following figure shows some examples of the counter behavior at different clock frequencies.
| CNT_EN<br>Timer clock = CK_CNT<br>Counter register<br>0 5<br>0 4<br>0 3<br>0 2<br>0 1<br>0 0<br>3 6<br>3 5<br>3 3<br>3 2<br>3 1 3 0 2 F<br>3 4<br>Counter overflow | |
|--------------------------------------------------------------------------------------------------------------------------------------------------------------------|--|
| | |
| | |
| | |
| | |
| Update event(UEV) | |
| Update interrupt flag(UIF) | |
Figure 15-10 Counter timing diagram, internal clock divided by 1
| CNT_EN<br>Counter register | 0033<br>0002<br>0001<br>0000<br>0036<br>0035<br>0034 |
|----------------------------|------------------------------------------------------|
| | |
| Update interrupt flag(UIF) | |
Figure 15-11 Counter timing diagram, internal clock divided by 2
| CK_PSC | |
|----------------------------|------------------------------|
| CNT_EN | |
| Timer clock = CK_CNT | |
| Counter register | 0001<br>0000<br>0036<br>0035 |
| Counter overflow | |
| Update event(UEV) | |
| Update interrupt flag(UIF) | |
Figure 15-12 Counter timing diagram, internal clock divided by 4
| CK_PSC | | |
|----------------------------|------------------|------------------|
| CNT_EN | | |
| Timer clock = CK_CNT | | |
| Counter register | 2<br>0<br>1<br>F | 0<br>0<br>3<br>6 |
| Counter overflow | | |
| Update event(UEV) | | |
| Update interrupt flag(UIF) | | |
Figure 15-13 Counter timing diagram, internal clock divided by N
| Auto-reload preload register | FF | 3 6 |
|------------------------------|-----------------------------------------------|-----------------------------------------------|
| Update interrupt flag(UIF) | | |
| Update event(UEV) | | |
| Counter overflow | | |
| Counter register | 0 5<br>0 4<br>0 3<br>0 1<br>0 0<br>3 6<br>0 2 | 3 5<br>3 4<br>3 2<br>3 1<br>3 0<br>3 3<br>2 F |
| Timer clock = CK_CNT | | |
| CNT_EN | | |
| CK_PSC | | |
Figure 15-14 Counter timing diagram, update event when repetition counter is not used
#### **Center-aligned mode (up/down counting)**
In center-aligned mode, the counter counts from 0 to the auto-reload value (content of the TIMx\_ARR register) – 1, generates a counter overflow event, then counts from the autoreload value down to 1 and generates a counter underflow event. Then it restarts counting from 0.
Center-aligned mode is active when the CMS bits in TIMx\_CR1 register are not equal to 0. The Output compare interrupt flag of channels configured in output is set when: the counter counts down (Center aligned mode 1, CMS = "01"), the counter counts up (Center aligned mode 2, CMS = "10") the counter counts up and down(Center aligned mode 3, CMS = "11").
In this mode, the DIR direction bit in the TIMx\_CR1 register cannot be written. It is updated by hardware and gives the current direction of the counter.
The update event can be generated at each counter overflow and at each counter underflow or by setting the UG bit in the TIMx\_EGR register (by software or by using the slave mode controller) also generates an update event. In this case, the counter restarts counting from 0, as well as the counter of the prescaler. The UEV update event can be disabled by software by setting the UDIS bit in the TIMx\_CR1 register. This is to avoid updating the shadow registers while writing new values in the preload registers. Then no update event occurs until UDIS bit has been written to 0. However, the counter continues counting up and down, based on the current auto-reload value.
In addition, if the URS bit (update request selection) in TIMx\_CR1 register is set, setting the UG bit generates an UEV update event but without setting the UIF flag (thus no interrupt). This is to avoid generating both update and capture interrupts when clearing the counter on the capture event.
When an update event occurs, all the registers are updated and the update flag (UIF bit in TIMx\_SR register) is set (depending on the URS bit).
- The repetition counter is reloaded with the content of TIMx\_RCR register
- The buffer of the prescaler is reloaded with the preload value (content of the TIMx\_PSC register)
- The auto-reload active register is updated with the preload value (content of the TIMx\_ARR register) Note: if the update source is a counter overflow, the autoreload is updated before the counter is reloaded, so that the next period is the expected one (the counter is loaded with the new value).
| CK_PSC | |
|----------------------------|---------------------------------------------------------------------------------------------|
| CNT_EN | |
| Timer clock = CK_CNT | |
| Counter register | 0 4<br>0 3<br>0 2<br>0 0<br>0 1<br>0 2<br>0 3<br>0 4<br>0 6<br>0 5<br>0 4 0 3<br>0 1<br>0 5 |
| Counter underflow | |
| Counter overflow | |
| Update event(UEV) | |
| Update interrupt flag(UIF) | |
Figure 15-15 Counter timing diagram, internal clock divided by 1, TIMx\_ARR = 0x6
| CK_PSC | |
|----------------------------|----------------------|
| CNT_EN | |
| Timer clock = CK_CNT | |
| | 0001<br>0000<br>0002 |
| Counter overflow | |
| | |
| Update interrupt flag(UIF) | |
Figure 15-16 Counter timing diagram, internal clock divided by 2, TIMx\_ARR = 0x36
![](_page_157_Figure_3.jpeg)
Figure 15-17 TIMx\_ARR=0x36 Counter timing diagram, internal clock divided by 4, TIMx\_ARR = 0x36
![](_page_157_Figure_5.jpeg)
Figure 15-18 Counter timing diagram, internal clock divided by N
| CK_PSC | |
|------------------------------|---------------------------------------------------------------------------------------------------------------------------------|
| CNT_EN | |
| Timer clock = CK_CNT | |
| Counter register | 0<br>1 0<br>0<br>0<br>1<br>0<br>2<br>0<br>4<br>0<br>5 0<br>6 0<br>0<br>6<br>0<br>5<br>0<br>4<br>0<br>3<br>0<br>2<br>0<br>3<br>7 |
| Counter underflow | |
| Update event(UEV) | |
| Update interrupt flag(UIF) | |
| Auto-reload preload register | FD<br>3<br>6 |
| Auto-reload shadow register | FD<br>3<br>6 |
| | Write a new value in TIMx_ARR |
Figure 15-19 Counter timing diagram, update event with ARPE = 1 (counter underflow)
![](_page_158_Figure_3.jpeg)
Figure 15-20 Counter timing diagram, Update event with ARPE = 1 (counter overflow)
## <span id="page-158-0"></span>**15.3.3. Repetition counter**
Time-base unit describes how the update event (UEV) is generated with respect to the counter overflows/underflows. It is actually generated only when the repetition counter has reached zero. This can be useful when generating PWM signals.
This means that data are transferred from the preload registers to the shadow registers (TIMx\_ARR auto-reload register, TIMx\_PSC prescaler register, but also TIMx\_CCRx capture/compare registers in compare mode) ,N+1 is the value in the TIMx\_RCR repetition counter register.
The repetition counter is decremented when any of the following conditions are true:
- At each counter overflow in upcounting mode.
- At each counter underflow in downcounting mode.
At each counter overflow and at each counter underflow in center-aligned mode. Although this limits the maximum number of repetition to 128 PWM cycles, it makes it possible to update the duty cycle twice per PWM period. When refreshing compare registers only once per PWM period in center-aligned mode, maximum resolution is 2xTck, due to the symmetry of the pattern.
The repetition counter is an auto-reload type, the repetition rate is maintained as defined by the TIMx\_RCR register value. When the update event is generated by software (by setting the UG bit in TIMx\_EGR register) or by hardware through the slave mode controller, it occurs immediately whatever the value of the repetition counter is and the repetition counter is reloaded with the content of the TIMx\_RCR register.
In center-aligned mode, for odd values of RCR, the update event occurs either on the overflow or on the underflow depending on when the RCR register was written and when the counter was started. If the RCR was written before starting the counter, the UEV occurs on the overflow. If the RCR was written after starting the counter, the UEV occurs on the underflow. For example for RCR = 3, the UEV is generated on each 4th overflow or underflow event depending on when RCR was written.
![](_page_159_Figure_4.jpeg)
Figure 15-21 Update rate examples depending on mode and TIMx\_RCR register settings
#### <span id="page-159-0"></span>**15.3.4. Clock source**
The counter clock can be provided by the following clock sources:
- Internal clock(CK\_INT)
- External clock mode1: external input pin
- External clock mode2: external trigger input ETR
Internal trigger inputs (ITRx): using one timer as prescaler for another timer, for example, the user can configure Timer 1 to act as a prescaler for Timer3.
#### **Internal clock source (CK\_INT)**
If the slave mode controller is disabled (SMS=000), then the CEN, DIR (in the TIMx\_CR1 register) and UG bits (in the TIMx\_EGR register) are actual control bits and can be changed only by software. As soon as the CEN bit is written to 1, the prescaler is clocked by the internal clock CK\_INT.
| CK_PSC | |
|-----------------------------------------------------|---------------------------------------------------------------------------------------------|
| CEN=CNT_EN | |
| U G | |
| CNT_INIT | |
| Counter clock = CK_CNT = CK_PSC<br>Counter register | 3 1<br>3 2<br>3 3<br>3 5<br>3 6<br>0 0<br>0 1<br>0 2<br>0 4<br>0 5<br>0 6 0 7<br>3 4<br>0 3 |
| | |
Figure 15-22 Control circuit in normal mode, internal clock divided by 1
#### **External clock source mode 1**
This mode is selected when SMS = 111 in the TIMx\_SMCR register. The counter can count at each rising or falling edge on a selected input.
![](_page_160_Figure_8.jpeg)
Figure 15-23 TI2 external clock connection example
![](_page_161_Figure_1.jpeg)
Figure 15-24 Control circuit in external clock mode 1
#### **External clock source mode 2**
This mode is selected by writing ECE = 1 in the TIMx\_SMCR register. The counter can count at each rising or falling edge on the external trigger input ETR.
![](_page_161_Figure_5.jpeg)
Figure 15-25 TI2 External trigger input block
![](_page_161_Figure_7.jpeg)
Figure 15-26 Control circuit in external clock mode 2
## <span id="page-161-0"></span>**15.3.5. Capture/compare channel**
Each Capture/Compare channel is built around a capture/compare register (including a shadow register), a input stage for capture (with digital filter, multiplexing and prescaler) and an output stage (with comparator and output control).
The input stage samples the corresponding TIx input to generate a filtered signal TIxF. Then, an edge detector with polarity selection generates a signal (TIxFPx) which can be used as trigger input by the slave mode controller or as the capture command. It is prescaled before the capture register (IcxPS).
![](_page_162_Figure_3.jpeg)
Figure 15-27 Capture/compare channel (example: channel 1 input stage)
The output stage generates an intermediate waveform that is then used for reference: OCxRef (active high). The polarity acts at the end of the chain.
![](_page_162_Figure_6.jpeg)
Figure 15-28 Capture/compare channel 1 main circuit
![](_page_163_Figure_1.jpeg)
Figure 15-29 Output stage of capture/compare channel (channel 1 to 3)
![](_page_163_Figure_3.jpeg)
Figure 15-30 Output stage of capture/compare channel (channel 4)
The capture/compare block is made of one preload register and one shadow register. Write and read always access the preload register.
In capture mode, captures are actually done in the shadow register, which is copied into the preload register.
In compare mode, the content of the preload register is copied into the shadow register which is compared to the counter.
## <span id="page-163-0"></span>**15.3.6. Input capture mode**
In Input capture mode, the Capture/Compare registers (TIMx\_CCRx) are used to latch the value of the counter after a transition detected by the corresponding ICx signal. When a capture occurs, the corresponding CCXIF flag (TIMx\_SR register) is set to 1 and an interrupt request can be sent if they are enabled. If a capture occurs while the CCxIF flag was already high, then the over-capture flag CCxOF (TIMx\_SR register) is set to 1. CCxIF can be cleared by software by writing it to '0' or by reading the captured data stored in the TIMx\_CCRx register. CCxOF is cleared when written to '0'. The following examples show how to capture the counter value in TIMx\_CCR1 when TI1 input rises. To do this, use the following procedure:
Select the active input: TIMx\_CCMR1 must be linked to the TI1 input, so write the CC1S bits to 01 in the TIMx\_CCMR1 register. As soon as CC1S becomes different from 00, the channel is configured in input and the TIMx\_CCR1 register becomes read-only.
Program the needed input filter duration with respect to the signal connected to the timer (by programming ICxF bits in the TIMx\_CCMRx register if the input is a TIx input). Let's imagine that, when toggling, the input signal is not stable during at must five internal clock cycles. We must program a filter duration longer than these five clockcycles. We can validate a transition on TI1 when 8 consecutive samples with the new level have been detected (sampled at Fck\_int frequency). Then write IC1F bits to 0011 in the TIMx\_CCMR1 register.
Select the edge of the active transition on the TI1 channel by writing CC1P bit to 0 in the TIMx\_CCER register (rising edge in this case).
Program the input prescaler. In our example, we wish the capture to be performed at each valid transition, so the prescaler is disabled (write IC1PS bits to '00' in the TIMx\_CCMR1 register).
Enable capture from the counter into the capture register by setting the CC1E bit to 1 in the TIMx\_CCER register
If needed, enable the related interrupt request by setting the CC1IE bit in the TIMx\_DIER register
When an input capture occurs:
When generating effective level conversion, the counter value is transmitted to TIMx\_ CCR1 register.
CC1IF flag is set (interrupt flag). CC1OF is also set if at least two consecutive captures occurred whereas the flag was not cleared.
An interrupt is generated depending on the CC1IE bit.
In order to handle the overcapture, it is recommended to read the data before the overcapture flag. This is to avoid missing an overcapture which could happen after reading the flag and before reading the data.
Note: Capture interrupt requests can be generated by software by setting the corresponding CCxG bit in the TIMx\_EGR register.
#### <span id="page-164-0"></span>**15.3.7. PWM input mode**
This mode is a particular case of input capture mode. The procedure is the same except:
- Two Icx signals are mapped on the same Tix input.
- The 2 Icx signals are active on edges with opposite polarity.
- One of the two TixFP signals is selected as trigger input and the slave mode controller is configured in reset mode.
For example, user can measure the period (in TIMx\_CCR1 register) and the duty cycle (in TIMx\_CCR2 register) of the PWM applied on TI1 using the following procedure (depending on CK\_INT frequency and prescaler value):
Select the active input for TIMx\_CCR1: write the CC1S bits to 01 in the TIMx\_CCMR1 register (TI1 selected).
Select the active polarity for TI1FP1 (used both for capture in TIMx\_CCR1 and counter clear): write the CC1P bit to '0' (active on rising edge).
Select the active input for TIMx\_CCR2: write the CC2S bits to 10 in the TIMx\_CCMR1 register (TI1 selected).
Select the active polarity for TI1FP2 (used for capture in TIMx\_CCR2): write the CC2P bit to '1' (active on falling edge).
Select the valid trigger input: write the TS bits to 101 in the TIMx\_SMCR register (TI1FP1 selected).
Configure the slave mode controller in reset mode: write the SMS bits to 100 in the TIMx\_SMCR register.
![](_page_165_Figure_3.jpeg)
Enable the captures: write the CC1E and CC2E bits to '1' in the TIMx\_CCER register.
Figure 15-31 PWM input mode timing
#### <span id="page-165-0"></span>**15.3.8. Forced output mode**
In output mode (CCxS bits = 00 in the TIMx\_CCMRx register), each output compare signal (OCxREF and then OCx/OCxN) can be forced to active or inactive level directly by software, independently of any comparison between the output compare register and the counter. To force an output compare signal (OCXREF/OCx) to its active level, the user just needs to write 101 in the OCxM bits in the corresponding TIMx\_CCMRx register. Thus OCXREF is forced high (OCxREF is always active high) and OCx get opposite value to CCxP polarity bit.
For example: CCxP = 0 (OCx active high) = > OCx is forced to high level. The OCxREF signal can be forced low by writing the OCxM bits to 100 in the TIMx\_CCMRx register.
The comparison between the TIMx\_CCRx shadow register and the counter is still performed and allows the flag to be set. Interrupt requests can be sent accordingly. This is described in the output compare mode section below.
#### <span id="page-165-1"></span>**15.3.9. Output compare mode**
This function is used to control an output waveform or indicating when a period of time has elapsed. When a match is found between the capture/compare register and the counter, the output compare function:
- Assigns the corresponding output pin to a programmable value defined by the output compare mode (OCxM bits in the TIMx\_CCMRx register) and the output polarity (CCxP bit in the TIMx\_CCER register). The output pin can keep its level (OCXM = 000), be set active (OCxM = 001), be set inactive (OCxM = 010) or can toggle (OCxM = 011) on match.
- Sets a flag in the interrupt status register (CCxIF bit in the TIMx\_SR register)
Generates an interrupt if the corresponding interrupt mask is set (CCXIE bit in the TIMx\_DIER register).
The TIMx\_CCRx registers can be programmed with or without preload registers using the OCxPE bit in the TIMx\_CCMRx register. In output compare mode, the update event UEV has no effect on OCxREF and OCx output.
The timing resolution is one count of the counter. Output compare mode can also be used to out-
put a single pulse (in One Pulse mode).
Configuration steps for output comparison mode:
- 1. Select the counter clock (internal, external, prescaler).
- 2. Write the desired data in the TIMx\_ARR and TIMx\_CCRx registers.
- 3. Set the CCxIE bit if an interrupt request is to be generated.
- 4. Select the output mode. For example:
- ─ Write OCxM = 011 to toggle OCx output pin when Counter matches CCRx
- ─ Write OCxPE = 0 to disable preload register
- ─ Write CCxP = 0 to select active high polarity
- ─ Write CCxE = 1 to enable the output
- ─ Enable the counter by setting the CEN bit in the TIMx\_CR1 register
The TIMx\_CCRx register can be updated at any time by software to control the output waveform, provided that the preload register is not enabled (OCxPE = '0', else TIMx\_CCRxshadow register is updated only at the next update event). An example is given in Figure 15-32.
![](_page_166_Figure_16.jpeg)
Figure 15-32 Output compare mode, toggle on OC1
#### <span id="page-166-0"></span>**15.3.10. PWM mode**
Pulse Width Modulation mode allows generating a signal with a frequency determined by the value of the TIMx\_ARR register and a duty cycle determined by the value of the TIMx\_CCRx register.
The PWM mode can be selected independently on each channel (one PWM per OCx output) by writing '110' (PWM mode 1) or '111' (PWM mode 2) in the OCxM bits in the TIMx\_CCMRx register. The corresponding preload register must be enabled by setting the OCxPE bit in the TIMx\_CCMRx register, and eventually the auto-reload preload register (in upcounting or center-aligned modes) by setting the ARPE bit in the TIMx\_CR1 register.
As the preload registers are transferred to the shadow registers only when an update event occurs, before starting the counter, the user must initialize all the registers by setting the UG bit in the TIMx\_EGR register.
OCx polarity is software programmable using the CCxP bit in the TIMx\_CCER register. It can be programmed as active high or active low. OCx output is enabled by a combination of the CCxE, CCxNE, MOE, OSSI and OSSR bits (TIMx\_CCER and TIMx\_BDTR registers). Refer to the TIMx\_CCER register description for more details.
In PWM mode (1 or 2), TIMx\_CNT and TIMx\_CCRx are always compared to determine whether TIMx\_CCRx ≤ TIMx\_CNT or TIMx\_CNT ≤ TIMx\_CCRx (depending on the direction of the counter). The timer is able to generate PWM in edge-aligned mode or center-aligned mode depending on the CMS bits in the TIMx\_CR1 register.
#### **PWM edge-aligned mode**
#### **Upcounting configuration**
Upcounting is active when the DIR bit in the TIMx\_CR1 register is low. Refer to Upcounting mode in the following example, we consider PWM mode 1. The reference PWM signal OCxREF is high as long as TIMx\_CNT < IMx\_CCRx else it becomes low. If the compare value in TIMx\_CCRx is greater than the auto-reload value (in TIMx\_ARR) then OCxREF is held at '1'. If the compare value is 0 then OCxRef is held at '0'. Figure 15-34 shows some edge-aligned PWM waveforms in an example where TIMx\_ARR = 8.
![](_page_167_Figure_6.jpeg)
![](_page_167_Figure_7.jpeg)
#### **Downcounting configuration**
Downcounting is active when DIR bit in TIMx\_CR1 register is high.
In PWM mode 1, the reference signal OCxRef is low as long as TIMx\_CNT > TIMx\_CCRx else it becomes high. If the compare value in TIMx\_CCRx is greater than the auto-reload value in TIMx\_ARR, then OCxREF is held at '1'. 0% PWM is not possible in this mode.
#### **PWM center-aligned mode**
Center-aligned mode is active when the CMS bits in TIMx\_CR1 register are different from '00' (all the remaining configurations having the same effect on the OCxRef/OCx signals). The compare flag is set when the counter counts up, when it counts down or both when it counts up and down depending on the CMS bits configuration. The direction bit (DIR) in the TIMx\_CR1 register is updated by hardware and must not be changed by software.
Refer to Center-aligned mode (up/down counting).
- TIMx\_ARR = 8
- PWM mode 1
- The flag is set when the counter counts down corresponding to the center-aligned mode 1 selected for CMS = 01 in TIMx\_CR1 register.
![](_page_168_Figure_6.jpeg)
Figure 15-34 Center-aligned PWM waveforms (ARR = 8)
Hints on using center-aligned mode:
- When starting in center-aligned mode, the current up-down configuration is used. It means that the counter counts up or down depending on the value written in the DIR bit in the TIMx\_CR1 register. Moreover, the DIR and CMS bits must not be changed at the same time by the software.
- Writing to the counter while running in center-aligned mode is not recommended as it can lead to unexpected results. In particular: – The direction is not updated if the user writes a value in the counter greater than the auto-reload value (TIMx\_CNT > TIMx\_ARR). For example, if the counter was counting up, it will continue to count up. – The direction is updated if the user writes 0 or write the TIMx\_ARR value in the counter but no Update Event UEV is generated.
- The safest way to use center-aligned mode is to generate an update by software (setting the UG bit in the TIMx\_EGR register) just before starting the counter and not to write the counter while it is running.
#### <span id="page-168-0"></span>**15.3.11. Complementary outputs and dead-time insertion**
The advanced-control timers (TIM1) can output two complementary signals and manage the switching-off and the switching-on instants of the outputs. This time is generally known as deadtime and it has to be adjust it depending on the devices connected to the outputs and their characteristics (intrinsic delays of level-shifters, delays due to power switches). User can select the polarity of the outputs (main output OCx or complementary OCxN) independently for each output. This is done by writing to the CCxP and CCxNP bits in the TIMx\_CCER register.
The complementary signals OCx and OCxN are activated by a combination of several control bits: the CCxE and CCxNE bits in the TIMx\_CCER register and the MOE, OISx, OISxN, OSSI and OSSR bits in the TIMx\_BDTR and TIMx\_CR2 registers. Refer to Table for more details. In particular, the dead-time is activated when switching to the IDLE state (MOE falling down to 0).
Dead-time insertion is enabled by setting both CCxE and CCxNE bits, and the MOE bit if the break circuit is present. DTG[7:0] bits are used to control the dead-time generation for all channels. From a reference waveform OCxREF, it generates 2 outputs OCx and OCxN. If OCx and OCxN are active high:
- The OCx output signal is the same as the reference signal except for the rising edge, which is delayed relative to the reference rising edge.
- The OCxN output signal is the opposite of the reference signal except for the rising edge, which is delayed relative to the reference falling edge.
If the delay is greater than the width of the active output (OCx or OCxN) then the corresponding pulse is not generated.
The following figures show the relationships between the output signals of the dead-time generator and the reference signal OCxREF. (we suppose CCxP = 0, CCxNP = 0, MOE = 1, CCxE = 1 and CCxNE = 1 in these examples).
![](_page_169_Figure_8.jpeg)
Figure 15-35 Complementary output with dead-time insertion
![](_page_169_Figure_10.jpeg)
Figure 15-36 Dead-time waveforms with delay greater than the negative pulse.
![](_page_170_Figure_1.jpeg)
Figure 15-37 Dead-time waveforms with delay greater than the positive pulse
The dead-time delay is the same for each of the channels and is programmable with the DTG bits in the TIMx\_BDTR register.
#### **Re-directing OCxREF to OCx or OCxN**
In output mode (forced, output compare or PWM), OCxREF can be re-directed to the OCx output or to OCxN output by configuring the CCxE and CCxNE bits in the TIMx\_CCER register. This allows the user to send a specific waveform (such as PWM or static active level) on one output while the complementary remains at its inactive level. Other possibilities are to have both outputs at inactive level or both outputs active and complementary with dead-time.
Note: When only OCxN is enabled (CCxE = 0, CCxNE = 1), it is not complemented and becomes active as soon as OCxREF is high. For example, if CCxNP = 0 then OCxN = OCxRef. On the other hand, when both OCx and OCxN are enabled (CCxE = CCxNE = 1) OCx becomes active when OCxREF is high whereas OCxN is complemented and becomes active when OCxREF is low.
#### <span id="page-170-0"></span>**15.3.12. Using the break function**
The purpose of the braking function is to protect the power switch driven by the PWM signal generated by the timer. Two disconnect inputs are normally connected to the power stage and to the fault output of the three-phase inverter. When activated, the disconnect circuit turns off the PWM output and forces it to a predefined safe state. A number of internal MCU events can also be selected to trigger the output shutdown.
When using the break function, the output enable signals and inactive levels are modified according to additional control bits. In any case, the OCx and OCxN outputs cannot be set both to active level at a given time.
The brake source can be either the brake input pin, or the following internal sources:
- Output from CPU LOCKUP
- SRAM Parity Error Signal
- Clock failure events generated by the Clock Security System (CSS)
- Output from comparator
After reset, the break circuit is disabled and the MOE bit is low. User can enable the break function by setting the BKE bit in the TIMx\_BDTR register. The break input polarity can be selected by configuring the BKP bit in the same register. BKE and BKP can be modified at the same time. When the BKE and BKP bits are written, a delay of 1 APB clock cycle is applied before the writing is effective. Consequently, it is necessary to wait 1 APB clock period to correctly read back the bit after the write operation.
Because MOE falling edge can be asynchronous, a resynchronization circuit has been inserted between the actual signal (acting on the outputs) and the synchronous control bit (accessed in the TIMx\_BDTR register). It results in some delays between the asynchronous and the synchronous signals. In particular, if MOE is written to 1 whereas it was low, a delay (dummy instruction) must be inserted before reading it correctly. This is because the user writes an asynchronous signal, but reads a synchronous signal.
When a break occurs (selected level on the break input):
- The MOE bit is cleared asynchronously, putting the outputs in inactive state, idle state or in reset state (selected by the OSSI bit). This feature functions even if the MCU oscillator is off.
- Each output channel is driven with the level programmed in the OISx bit in the TIMx\_CR2 register as soon as MOE = 0. If OSSI = 0 then the timer releases the enable output else the enable output remains high.
- When complementary outputs are used:
- The outputs are first put in reset state inactive state (depending on the polarity). This is done asynchronously so that it works even if no clock is provided to the timer.
- If the timer clock is still present, then the dead-time generator is reactivated in order to drive the outputs with the level programmed in the OISx and OISxN bits after a deadtime. Even in this case, OCx and OCxN cannot be driven to their active level together. Note that because of the resynchronization on MOE, the dead-time duration is a bit longer than usual (around 2 ck\_tim clock cycles).
- If OSSI = 0 then the timer releases the enable outputs else the enable outputs remain or become high as soon as one of the CCxE or CCxNE bits is high.
- The break status flag (BIF bit in the TIMx\_SR register) is set. An interrupt can be generated if the BIE bit in the TIMx\_DIER register is set.
- If the AOE bit in the TIMx\_BDTR register is set, the MOE bit is automatically set again at the next update event UEV. This can be used to perform a regulation, for instance. Else, MOE remains low until it is written to '1' again. In this case, it can be used for security and the break input can be connected to an alarm from power drivers, thermal sensors or any security components.
Note: The break inputs is acting on level. Thus, the MOE cannot be set while the break input is active (neither automatically nor by software). In the meantime, the status flag BIF cannot be cleared.
The break can be generated by the BRK input which has a programmable polarity and an enable bit BKE in the TIMx\_BDTR register.
In addition to the break input and the output management, a write protection has been implemented inside the break circuit to safeguard the application. It allows freezing the configuration of several parameters (dead-time duration, OCx/OCxN polarities and state when disabled, OCxM configurations, break enable and polarity). The user can choose from three levels of protection
selected by the LOCK bits in the TIMx\_BDTR register. The LOCK bits can be written only once after an MCU reset.
The following figure shows the example of the output in response to a break.
![](_page_172_Figure_3.jpeg)
Figure 15-38 Output behavior in response to a break
## <span id="page-172-0"></span>**15.3.13. Clearing the OCxREF signal on an external event**
The OCxREF signal for a given channel can be driven Low by applying a High level to the OC-REF\_CLR\_INPUT (OCxCE enable bit of the corresponding TIMx\_CCMRx register set to '1'). The OCxREF signal remains Low until the next update event of UEV occurs. This function can only be used in output compare and PWM modes, and does not work in forced mode.
OCREF\_CLR\_INPUT can be configured through OCCS bit in TIMx\_ SMCR register, in Choose between OCREF\_ CLR and ETRF (after ETR filtering).
For example, the ETR signal can be connected to the output of a comparator to be used for current handling. In this case, the ETR must be configured as follow:
1. The External Trigger Prescaler should be kept off: bits ETPS[1:0] of the TIMx\_SMCR register set to '00'.
2. The external clock mode 2 must be disabled: bit ECE of the TIMx\_SMCR register set to '0'.
3. The External Trigger Polarity (ETP) and the External Trigger Filter (ETF) can be configured according to the user needs.
The Figure below shows the behavior of the OCxREF signal when the ETRF Input becomes High, for both values of the enable bit OCxCE. In this example, the timer TIMx is programmed in PWM mode.
![](_page_173_Figure_2.jpeg)
Figure 15-39 Clearing TIM1 OCxREF
## <span id="page-173-0"></span>**15.3.14. 6-step PWM generation**
When complementary outputs are used on a channel, preload bits are available on the OCxM, CCxE and CCxNE bits. The preload bits are transferred to the shadow bits at the COM commutation event. The user can thus program in advance the configuration for the next step and change the configuration of all the channels at the same time. COM can be generated by software by setting the COM bit in the TIMx\_EGR register or by hardware (on TRGI rising edge).
A flag is set when the COM event occurs (COMIF bit in the TIMx\_SR register), which can generate an interrupt (if the COMIE bit is set in the TIMx\_DIER register) or a DMA request (if the COMDE bit is set in the TIMx\_DIER register).
The figure blow describes the behavior of the OCx and OCxN outputs when a COM event occurs, in 3 different examples of programmed configurations.
![](_page_174_Figure_1.jpeg)
Figure 15-40 6-step generation, COM example (OSSR = 1)
## <span id="page-174-0"></span>**15.3.15. One-pulse mode**
One-pulse mode (OPM) is a particular case of the previous modes. It allows the counter to be started in response to a stimulus and to generate a pulse with a programmable length after a programmable delay.
Starting the counter can be controlled through the slave mode controller. Generating the waveform can be done in output compare mode or PWM mode. Select One-pulse mode by setting the OPM bit in the TIMx\_CR1 register. This makes the counter stop automatically at the next update event UEV.
A pulse can be correctly generated only if the compare value is different from the counter initial value.Before starting (when the timer is waiting for the trigger), the configuration must be:
- In upcounting: CNT < CCRx ≤ ARR (in particular, 0 < CCRx)
- In downcounting: CNT > CCRx
![](_page_175_Figure_1.jpeg)
Figure 15-41 Example of one pulse mode
For example the user may want to generate a positive pulse on OC1 with a length of tPULSE and after a delay of tDELAY as soon as a rising edge is detected on the TI2 input pin.
Let's use TI2FP2 as trigger 1
- Map TI2FP2 to TI2 by writing CC2S = '01' in the TIMx\_CCMR1 register.
- TI2FP2 must detect a rising edge, write CC2P = '0' in the TIMx\_CCER register.
- Configure TI2FP2 as trigger for the slave mode controller (TRGI) by writing TS = '110' in the TIMx\_SMCR register.
- TI2FP2 is used to start the counter by writing SMS to '110' in the TIMx\_SMCR register (trigger mode).
The OPM waveform is defined by writing the compare registers (taking into account the clock frequency and the counter prescaler).
- The tDELAY is defined by the value written in the TIMx\_CCR1 register
- The tPULSE is defined by the difference between the auto-reload value and the compare value (TIMx\_ARR-TIMx\_CCR1).
- Assuming that a waveform from 0 to 1 is generated when a comparison match occurs,and a waveform from '1' to '0' is generated when the counter reaches the preload value. To do this, enable PWM mode 2 by writing OC1M = 111 in the TIMx\_CCMR1 register.The user can optionally enable the preload registers by writing OC1PE = '1' in the TIMx\_CCMR1 register and ARPE in the TIMx\_CR1 register. In this case the compare value must be written in the TIMx\_CCR1 register, the auto-reload value in the TIMx\_ARR register, generate an update by setting the UG bit and wait for external trigger event on TI2. CC1P is written to '0' in this example.
In this example, the DIR and CMS bits in the TIMx\_CR1 register should be low.
The user only wants one pulse, so '1' must be written in the OPM bit in the TIMx\_CR1 register to stop the counter at the next update event (when the counter rolls over from the auto-reload value back to 0).
#### **Particular case: OCx fast enable:**
In One-pulse mode, the edge detection on TIx input set the CEN bit which enables the counter. Then the comparison between the counter and the compare value makes the output toggle. But several clock cycles are needed for these operations and it limits the minimum delay tDELAY.
If the user wants to output a waveform with the minimum delay, the OCxFE bit in the TIMx\_CCMRx register must be set. Then OCxRef (and OCx) are forced in response to the stimulus, without taking in account the comparison. Its new level is the same as if a compare match had occurred. OCxFE acts only if the channel is configured in PWM1 or PWM2 mode.
#### <span id="page-176-0"></span>**15.3.16. Encoder interface mode**
To select Encoder Interface mode write SMS = '001' in the TIMx\_SMCR register if the counter is counting on TI2 edges only, SMS = '010' if it is counting on TI1 edges only and SMS = '011' if it is counting on both TI1 and TI2 edges.
Select the TI1 and TI2 polarity by programming the CC1P and CC2P bits in the TIMx\_CCER register. When needed, the user can program the input filter as well.
The two inputs TI1 and TI2 are used to interface to an incremental encoder. Refer to Table 35. The counter is clocked by each valid transition on TI1FP1 or TI2FP2 assuming that it is enabled (CEN bit in TIMx\_CR1 register written to '1'). TI1 and TI2 after input filter and polarity selection, TI1FP1= TI1 if not filtered and not inverted,TI2FP2 = TI2 if not filtered and not inverted.The sequence of transitions of the two inputs is evaluated and generates count pulses as well as the direction signal. Depending on the sequence the counter counts up or down, the DIR bit in the TIMx\_CR1 register is modified by hardware accordingly. The DIR bit is calculated at each transition on any input (TI1 or TI2), whatever the counter is counting on TI1 only, TI2 only or both TI1 and TI2.
Encoder interface mode acts simply as an external clock with direction selection. This means that the counter just counts continuously between 0 and the auto-reload value in the TIMx\_ARR register (0 to ARR or ARR down to 0 depending on the direction). So user must configure TIMx\_ARR before starting. in the same way, the capture, compare, prescaler, repetition counter, trigger output features continue to work as normal. Encoder mode and External clock mode 2 are not compatible and must not be selected together. In this mode, the counter is modified automatically following the speed and the direction of the incremental encoder and its content, therefore, always represents the encoder's position. The count direction correspond to the rotation direction of the connected sensor. The table below summarizes the possible combinations, assuming TI1 and TI2 do not switch at the same time.
| Active edge | Level on opposite signal | TI1FP1 signal | | TI2FP2 signal | | | |
|-------------|----------------------------------|---------------|----------|---------------|----------|--|--|
| | (TI1FP1 for TI2, TI2FP2 for TI1) | Rising | Falling | Rising | Falling | | |
| Counting on | High | Down | Up | No count | No count | | |
| TI1 only | Low | Up | Down | No count | No count | | |
| Counting on | High | No count | No count | Up | Down | | |
| TI2 only | Low | No count | No count | Down | Up | | |
| Counting on | High | Down | Up | Up | Down | | |
| TI1 and TI2 | Low | Up | Down | Down | Up | | |
Table 15-1 Counting direction versus encoder signals
An external incremental encoder can be connected directly to the MCU without external interface logic. However, comparators are normally be used to convert the encoder's differential outputs to digital signals. This greatly increases noise immunity. The third encoder output which indicate the mechanical zero position, may be connected to an external interrupt input and trigger a counter reset. The figure below gives an example of counter operation, showing count signal generation and direction control. It also shows how input jitter is compensated where both edges are selected. This might occur if the sensor is positioned near to one of the switching points. For this example we assume that the configuration is the following:
- CC1S = '01'(TIMx\_CCMR1 register, TI1FP1 mapped on TI1).
- CC2S = '01' (TIMx\_CCMR2 register, TI1FP2 mapped on TI2).
- CC1P = '0' (TIMx\_CCER register, TI1FP1 non inverted, TI1FP1 = TI1).
- CC2P = '0' (TIMx\_CCER register, TI1FP2 non-inverted, TI1FP2 = TI2).
- SMS = '011' (TIMx\_SMCR register, both inputs are active on both rising and falling edges).
- CEN = '1' (TIMx\_CR1 register, counter enabled).
![](_page_177_Figure_8.jpeg)
Figure 15-42 Example of counter operation in encoder interface mode.
![](_page_177_Figure_10.jpeg)
Figure 15-43 Example of encoder interface mode with TI1FP1 polarity inverted
The timer when configured in Encoder Interface mode provides information on the sensor's current position.The user can obtain dynamic information (speed, acceleration, deceleration) by measuring the period between two encoder events using a second timer configured in capture mode. The output of the encoder which indicates the mechanical zero can be used for this purpose. Depending on the time between two events, the counter can also be read at regular times. This can be done by latching the counter value into a third input capture register if available (then the capture signal must be periodic and can be generated by another timer).
#### <span id="page-177-0"></span>**15.3.17. Timer input XOR function**
The TI1S bit in the TIMx\_CR2 register, allows the input filter of channel 1 to be connected to the output of a XOR gate, combining the three input pins TIMx\_CH1, TIMx\_CH2 and TIMx\_CH3. The XOR output can be used with all the timer input functions such as trigger or input capture.
#### <span id="page-178-0"></span>**15.3.18. Interfacing with Hall sensors**
Example: the user wants to change the PWM configuration of the advanced-control timer TIM1 after a programmed delay each time a change occurs on the Hall inputs connected to one of the TIMx timers.
- Configure 3 timer inputs ORed to the TI1 input channel by writing the TI1S bit in the TIMx\_CR2 register to'1'.
- Program the time base: write the TIMx\_ARR to the max value (the counter must be cleared by the TI1 change. Set the prescaler to get a maximum counter period longer than the time between 2 changes on the sensors.
- Program channel 1 in capture mode (TRC selected): write the CC1S bits in the TIMx\_CCMR1 register to'01'. The user can also program the digital filter if needed.
- Program channel 2 in PWM 2 mode with the desired delay: write the OC2M bits to '111' and the CC2S bits to '00' in the TIMx\_CCMR1 register.
- Select OC2REF as trigger output on TRGO: write the MMS bits in the TIMx\_CR2 register to '101'.
In the advanced-control timer TIM1, the right ITR input must be selected as trigger input, the timer is programmed to generate PWM signals, the capture/compare control signals are preloaded (CCPC = 1 in the TIMx\_CR2 register) and the COM event is controlled by the trigger input (CCUS = 1 in the TIMx\_CR2 register). The PWM control bits (CCxE, OCxM) are written after a COM event for the next step (this can be done in an interrupt subroutine generated by the rising edge of OC2REF).
![](_page_179_Figure_1.jpeg)
Figure 15-44 Example of Hall sensor interface
## <span id="page-179-0"></span>**15.3.19. TIMx and external trigger synchronization**
The TIMx timer can be synchronized with an external trigger in several modes: Reset mode, Gated mode and Trigger mode.
Slave mode: Reset mode
The counter and its prescaler can be reinitialized in response to an event on a trigger input. Moreover, if the URS bit from the TIMx\_CR1 register is low, an update event UEV is generated. Then all the preloaded registers (TIMx\_ARR, TIMx\_CCRx) are updated.
In the following example, the upcounter is cleared in response to a rising edge on TI1 input:
- Configure the channel 1 to detect rising edges on TI1. Configure the input filter duration (in this example, we don't need any filter, so we keep IC1F = 0000). The capture prescaler is not used for triggering, so there's no need to configure it. The CC1S bits select the input capture source only, CC1S = 01 in the TIMx\_CCMR1 register. Write CC1P = 0 in TIMx\_CCER register to validate the polarity (and detect rising edges only).
- Configure the timer in reset mode by writing SMS = 100 in TIMx\_SMCR register. Select TI1 as the input source by writing TS = 101 in TIMx\_SMCR register.
Start the counter by writing CEN = 1 in the TIMx\_CR1 register.
The counter starts counting on the internal clock, then behaves normally until TI1 rising edge. When TI1 rises, the counter is cleared and restarts from 0. In the meantime, the trigger flag is set (TIF bit in the TIMx\_SR register) and an interrupt request can be sent if enabled (depending on the TIE and TDE bits in TIMx\_DIER register).
The following figure shows this behavior when the auto-reload register TIMx\_ARR = 0x36. The delay between the rising edge on TI1 and the actual reset of the counter is due to the resynchronization circuit on TI1 input.
![](_page_180_Figure_4.jpeg)
Figure 15-45 Control circuit in reset mode
#### **Slave mode: Gated mode**
The counter can be enabled depending on the level of a selected input.
In the following example, the upcounter counts only when TI1 input is low:
- Configure the channel 1 to detect low levels on TI1. Configure the input filter duration (in this example, we don't need any filter, so we keep IC1F = 0000). The capture prescaler is not used for triggering, so the user does not need to configure it. The CC1S bits select the input capture source only, CC1S = 01 in TIMx\_CCMR1 register. Write CC1P = 1 in TIMx\_CCER register to validate the polarity (and detect low level only).
- Configure the timer in gated mode by writing SMS = 101 in TIMx\_SMCR register. Select TI1 as the input source by writing TS = 101 in TIMx\_SMCR register.
- Enable the counter by writing CEN = 1 in the TIMx\_CR1 register (in gated mode, the counter doesn't start if CEN = 0, whatever is the trigger input level).
The counter starts counting on the internal clock as long as TI1 is low and stops as soon as TI1 becomes high. The TIF flag in the TIMx\_SR register is set both when the counter start or stops. The delay between the rising edge on TI1 and the actual stop of the counter is due to the resynchronization circuit on TI1 input.
![](_page_181_Figure_1.jpeg)
Figure 15-46 Control circuit in gated mode
The counter can start in response to an event on a selected input.
In the following example, the upcounter starts in response to a rising edge on TI2 input:
- Configure the channel 2 to detect rising edges on TI2. Configure the input filter duration (in this example, we don't need any filter, so we keep IC2F = 0000). The capture prescaler is not used for triggering, so there's no need to configure it. The CC2S bits are configured to select the input capture source only, CC2S= 01 in TIMx\_CCMR1 register. Write CC2P = 1 in TIMx\_CCER register to validate the polarity (and detect low level only).
- Configure the timer in trigger mode by writing SMS = 110 in TIMx\_SMCR register. Select TI2 as the input source by writing TS = 110 in TIMx\_SMCR register.
When a rising edge occurs on TI2, the counter starts counting on the internal clock and the TIF flag is set. The delay between the rising edge on TI2 and the actual start of the counter is due to the resynchronization circuit on TI2 input.
![](_page_181_Figure_8.jpeg)
Figure 15-47 Control circuit in trigger mode
#### **Slave mode: external clock mode 2 + trigger mode**
The external clock mode 2 can be used in addition to another slave mode (except external clock mode 1 and encoder mode). In this case, the ETR signal is used as external clock input, and another input can be selected as trigger input (in reset mode, gated mode or trigger mode). It is recommended not to select ETR as TRGI through the TS bits of TIMx\_SMCR register.
In the following example, the upcounter is incremented at each rising edge of the ETR signal as soon as a rising edge of TI1 occurs:
- 1. Configure the external trigger input circuit by programming the TIMx\_SMCR register as follows:
- ETF = 0000: no filter.
- ─ ETPS=00:prescaler disabled.
- ─ ETP=0:detection of rising edges on ETR and ECE = 1 to enable the external clock mode 2
- 2. Configure the channel 1 as follows, to detect rising edges on TI:
- ─ IC1F=0000:no filter
- ─The capture prescaler is not used for triggering and does not need to be configured.
- ─CC1S = 01 in TIMx\_CCMR1 register to select only the input capture source
- ─CC1P = 0 in TIMx\_CCER register to validate the polarity (and detect rising edge only).
- 3. Configure the timer in trigger mode by writing SMS = 110 in TIMx\_SMCR register. Select TI1 as the input source by writing TS = 101 in TIMx\_SMCR register.
A rising edge on TI1 enables the counter and sets the TIF flag. The counter then counts on ETR rising edges.The delay between the rising edge of the ETR signal and the actual reset of the counter is due to the resynchronization circuit on ETRP input.
![](_page_182_Figure_12.jpeg)
Figure 15-48 Control circuit in external clock mode 2 + trigger mode
#### <span id="page-182-0"></span>**15.3.20. Timer synchronization**
The TIM timers are linked together internally for timer synchronization or chaining. When a timer is in master mode, it can reset, start, stop or clock the counter of another timer in slave mode.
## <span id="page-182-1"></span>**15.3.21. Debug mode**
When the chip enters the debug mode, according to the setting of DBG\_TIMx\_STOP in the DBG module, the TIMx counter can continue to work normally or stop working.
## <span id="page-182-2"></span>**15.4. TIM1 registers**
## <span id="page-182-3"></span>**15.4.1. TIM1 control register1 (TIM1\_CR1)**
#### **Address offset:**0x00
| 31 | 30 | 29 | 28 | 27 | 26 | 25 | 24 | 23 | 22 | 21 | 20 | 19 | 18 | 17 | 16 |
|-----|-----|-----|-----|-----|-----|-----|----------|------|-----|----------|-----|-----|-----|------|-----|
| Res | Res | Res | Res | Res | Res | Res | Res | Res | Res | Res | Res | Res | Res | Res | Res |
| - | - | - | - | - | - | - | - | - | - | - | - | - | - | - | - |
| 15 | 14 | 13 | 12 | 11 | 10 | 9 | 8 | 7 | 6 | 5 | 4 | 3 | 2 | 1 | 0 |
| Res | Res | Res | Res | Res | Res | | CKD[1:0] | ARPE | | CMS[1:0] | DIR | OPM | URS | UDIS | CEN |
| - | - | - | - | - | - | | RW | RW | | RW | RW | RW | RW | RW | RW |
| Bit | Name | R/W | Reset Value | Function |
|-------|----------|-----|-------------|-----------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------|
| 31:10 | Reserved | | | |
| 9:8 | CKD[1:0] | RW | 00 | Clock division factor<br>This bit-field indicates the division ratio between the timer<br>clock (CK_INT) frequency and the dead-time and sam<br>pling clock used by the dead-time generators and the digi<br>tal filters (ETR, TIx),<br>00: tDTS = tCK_INT<br>01: tDTS = 2 x tCK_INT |
| | | | | 10: tDTS = 4 x tCK_INT |
| | | | | 11: Reserved, do not use this configuration. |
| | | | | Auto-reload preload enable<br>0: TIM1_ARR register is not buffered |
| 7 | ARPE | RW | 0 | |
| | | | | 1: TIM1_ARR register is buffered<br>Center-aligned mode selection |
| | | | | 00:Edge-aligned mode. The counter counts up or down |
| | | | | depending on the direction bit (DIR). |
| | | | | 01:Center-aligned mode 1. The counter counts up and |
| | | RW | 00 | down alternatively. Output compare interrupt flags of chan<br>nels configured in output (CCxS = 00 in TIMx_CCMRx reg<br>ister) are set only when the counter is counting down. |
| | | | | 10:Center-aligned mode 2. The counter counts up and |
| 6:5 | CMS[1:0] | | | down alternatively. Output compare interrupt flags of chan<br>nels configured in output (CCxS = 00 in TIMx_CCMRx reg<br>ister) are set only when the counter is counting up. |
| | | | | 11:Center-aligned mode 3. The counter counts up and |
| | | | | down alternatively. Output compare interrupt flags of chan<br>nels configured in output (CCxS = 00 in TIMx_CCMRx reg<br>ister) are set both when the counter is counting up or down.<br>Note: It is not allowed to switch from edge-aligned mode to<br>center-aligned mode as long as the counter is enabled<br>(CEN = 1). |
| | | | | Direction |
| 4 | DIR | RW | 0 | 0: Counter used as upcounter<br>1: Counter used as downcounter<br>Note: This bit is read only when the timer is configured in<br>Center-aligned mode or Encoder mode. |
| 3 | OPM | RW | 0 | One pulse mode<br>0: Counter is not stopped at update event<br>1: Counter stops counting at the next update event (clear<br>ing the bit CEN) |
| 2 | URS | RW | 0 | Update request source<br>This bit is set and cleared by software to select the UEV<br>event sources.<br>0: Any of the following events generate an update interrupt<br>if enabled.These events can be:<br>– Counter overflow/underflow<br>– Setting the UG bit<br>– Update generation through the slave mode controller<br>1: Only counter overflow/underflow generates an update |
| 1 | UDIS | RW | 0 | interrupt or DMA request if enabled.<br>Update disable |
| Bit | Name | R/W | Reset Value | Function |
|-----|------|-----|-------------|----------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------|
| | | | | This bit is set and cleared by software to enable/disable<br>UEV event generation.<br>0: UEV enabled. The Update (UEV) event is generated by<br>one of the following events: |
| | | | | – Counter overflow/underflow |
| | | | | – Setting the UG bit |
| | | | | –Update generation through the slave mode controller Buff |
| | | | | ered registers are then loaded with their preload values.<br>1: UEV disabled. The Update event is not generated,<br>shadow registers keep their value(ARR, PSC, CCRx). How<br>ever the counter and the prescaler are reinitialized if the UG<br>bit is set or if a hardware reset is received from the slave<br>mode controller. |
| 0 | CEN | RW | 0 | Counter enable<br>0: Counter disabled<br>1: Counter enabled<br>Note: External clock, gated mode and encoder mode can |
| | | | | work only if the CEN bit has been previously set by soft<br>ware. However trigger mode can set the CEN bit automati<br>cally by hardware. |
## <span id="page-184-0"></span>**15.4.2. TIM1 control register2 (TIM1\_CR2)**
#### **Address offset:**0x04
| 31 | 30 | 29 | 28 | 27 | 26 | 25 | 24 | 23 | 22 | 21 | 20 | 19 | 18 | 17 | 16 |
|----|-----|------|-----|------|-----|------|-----|-----|----|----------|----|-----|-----|----|-----|
| Re | Res | Res | Res | Res | Res | Res | Res | Res | Re | Re | Re | Res | Res | Re | Res |
| s | | | | | | | | | s | s | s | | | s | |
| - | - | - | - | - | - | - | - | - | - | - | - | - | - | - | - |
| 15 | 14 | 13 | 12 | 11 | 10 | 9 | 8 | 7 | 6 | 5 | 4 | 3 | 2 | 1 | 0 |
| Re | OIS | OIS3 | OIS | OIS2 | OIS | OIS1 | OIS | TI1 | | | | RE | CCU | Re | CCP |
| s | 4 | N | 3 | N | 2 | N | 1 | S | | MMS[2:0] | | S | S | s | C |
| - | RW | RW | RW | RW | RW | RW | RW | RW | RW | RW | RW | - | RW | - | RW |
| Bit | Name | R/W | Reset Value | Function |
|-------|----------|-----|-------------|---------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------|
| 31:15 | Reserved | - | 0 | Reserved, must be kept at reset value |
| 14 | OIS4 | RW | | Output Idle state 4 (OC4 output) refer to OIS1 bit. |
| 13 | OIS3N | RW | 0 | Output Idle state 3 (OC3N output) refer to OIS1N bit |
| 12 | OIS3 | RW | 0 | Output Idle state 3 (OC3 output) refer to OIS1 bit |
| 11 | OIS2N | RW | 0 | Output Idle state 2 (OC2N output) refer to OIS1N bit |
| 10 | OIS2 | RW | 0 | Output Idle state 2 (OC2 output) refer to OIS1 bit |
| 9 | OIS1N | RW | 0 | Output Idle state 1 (OC1N output)<br>0: OC1N = 0 after a dead-time when MOE = 0<br>1: OC1N = 1 after a dead-time when MOE = 0<br>Note: This bit cannot be modified as long as LOCK level 1,<br>2 or 3 has been programmed (LOCK bits in TIMx_BKR<br>register). |
| 8 | OIS1 | RW | 0 | Output Idle state 1 (OC1 output)<br>0: OC1 = 0 (after a dead-time if OC1N is implemented)<br>when MOE = 0<br>1: OC1 = 1 (after a dead-time if OC1N is implemented)<br>when MOE = 0<br>Note: This bit cannot be modified as long as LOCK level 1,<br>2 or 3 has been programmed (LOCK bits in TIMx_BKR reg<br>ister) |
| 7 | TI1S | RW | 0 | TI1 selection<br>0: The TIMx_CH1 pin is connected to TI1 input<br>1: The TIMx_CH1, CH2 and CH3 pins are connected to<br>the TI1 input (XOR combination) |
| 6:4 | MMS[2:0] | RW | 000 | Master mode selection<br>These bits allow to select the information to be sent in<br>master mode to slave timers for synchronization (TRGO).<br>The combination is as follows: |
| Bit | Name | R/W | Reset Value | Function |
|-----|------|-----|-------------|------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------|
| | | | | 000: Reset - the UG bit from the TIMx_EGR register is used<br>as trigger output (TRGO). If the reset is generated by the<br>trigger input (slave mode controller configured in reset<br>mode) then the signal on TRGO is delayed compared to the<br>actual reset.<br>001: Enable - the Counter Enable signal CNT_EN is used<br>as trigger output (TRGO). It is useful to start several timers<br>at the same time or to control a window in which a slave<br>timer is enable. The Counter Enable signal is generated by<br>a logic OR between CEN control bit and the trigger input<br>when configured in gated mode. When the Counter Enable<br>signal is controlled by the trigger input, there is a delay on<br>TRGO, except if the master/slave mode is selected (see the<br>MSM bit description in TIMx_SMCR register).<br>010: Update - The update event is selected as trigger out<br>put (TRGO). For instance a master timer can then be used<br>as a prescaler for a slave timer.<br>011: Compare Pulse - The trigger output send a positive<br>pulse when the CC1IF flag is to be set (even if it was al<br>ready high), as soon as a capture or a compare match oc<br>curred(TRGO).<br>100: Compare - OC1REF signal is used as trigger output<br>(TRGO)<br>101: Compare - OC2REF signal is used as trigger output<br>(TRGO)<br>110: Compare - OC3REF signal is used as trigger output<br>(TRGO)<br>111: Compare - OC4REF signal is used as trigger output<br>(TRGO)<br>Note:<br>1. The clock of the slave timer and ADC must first be ena<br>bled to receive signals from the master timer and not<br>change during reception.<br>2. If the master and slave timers are not on the same bus,<br>the holotype should be configured as the width that can be<br>taken from the timer. |
| 3 | Res | - | 0 | Reserved,always read as 0. |
| 2 | CCUS | RW | 0 | Capture/compare control update selection<br>0: When capture/compare control bits are preloaded<br>(CCPC = 1), they are updated by setting the COMG bit only<br>1: When capture/compare control bits are preloaded<br>(CCPC = 1), they are updated by setting the COMG bit or<br>when an rising edge occurs on TRGI.<br>Note: This bit acts only on channels that have a comple<br>mentary output. |
| 1 | Res | - | 0 | Reserved,always read as 0. |
| 0 | CCPC | RW | 0 | Capture/compare preloaded control<br>0:CCxE, CCxNE and OCxM bits are not preloaded<br>1:CCxE, CCxNE and OCxM bits are preloaded, after having<br>been written, they are updated only when a communication<br>event (COM) occurs.<br>Note: This bit acts only on channels that have a comple<br>mentary output. |
## <span id="page-185-0"></span>**15.4.3. TIM1 slave mode control register (TIM1\_SMCR)**
#### **Address offset:**0x08
| Reset value:0x0000 0000 | |
|-------------------------|--|
| | |
| 31 | 30 | 29 | 28 | 27 | 26 | 25 | 24 | 23 | 22 | 21 | 20 | 19 | 18 | 17 | 16 |
|-----|-----|-----------|-----|-----|----------|-----|-----|-----|---------|-----|-----|------|----------|-----|-----|
| Res | Res | Res | Res | Res | Res | Res | Res | Res | Res | Res | Res | Res | Res | Res | Res |
| - | - | - | - | - | - | - | - | - | - | - | - | - | - | - | - |
| 15 | 14 | 13 | 12 | 11 | 10 | 9 | 8 | 7 | 6 | 5 | 4 | 3 | 2 | 1 | 0 |
| ETP | ECE | ETPS[1:0] | | | ETF[3:0] | | | MSM | TS[2:0] | | | OCCS | SMS[2:0] | | |
| RW | RW | RW | | | RW | | | | | RW | | RW | | RW | |
| Bit | Name | R/W | Reset Value | Function |
|-------|-----------|-----|-------------|-------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------|
| 31:16 | Reserved | | | |
| 15 | ETP | RW | 0 | External trigger polarity<br>This bit selects whether ETR or reverse of ETR is used for trigger<br>operations<br>0: ETR is non-inverted, active at high level or rising edge.<br>1: ETR is inverted, active at low level or falling edge. |
| 14 | ECE | RW | 0 | External clock enable<br>This bit enables External clock mode 2.<br>0: External clock mode 2 disabled<br>1: External clock mode 2 enabled. The counter is clocked by any<br>active edge on the ETRF signal. |
| 13:12 | ETPS[1:0] | RW | 00 | External trigger prescaler<br>External trigger signal ETRP frequency must be at most 1/4 of<br>TIM1CLK frequency. A prescaler can be enabled to reduce<br>ETRP frequency. It is useful when inputting fast external clocks.<br>00: Prescaler OFF<br>01: ETRP frequency divided by 2<br>10: ETRP frequency divided by 4<br>11: ETRP frequency divided by 8 |
| 11:8 | ETF[3:0] | RW | 0000 | External trigger filter<br>This bit-field then defines the frequency used to sample ETRP<br>signal and the length of the digital filter applied to ETRP. The dig<br>ital filter is made of an event counter in which N consecutive<br>events are needed to validate a transition on the output:<br>0000: No filter, sampling is done at fDTS<br>0001: fSAMPLING = fCK_INT, N = 2<br>0010: fSAMPLING = fCK_INT, N = 4<br>0011: fSAMPLING = fCK_INT, N = 8<br>0100: fSAMPLING = fDTS / 2, N = 6<br>0101: fSAMPLING = fDTS / 2, N = 8<br>0110: fSAMPLING = fDTS / 4, N = 6<br>0111: fSAMPLING = fDTS / 4, N = 8<br>1000: fSAMPLING = fDTS / 8, N = 6<br>1001: fSAMPLING = fDTS / 8, N = 8<br>1010: fSAMPLING = fDTS / 16, N = 5<br>1011: fSAMPLING = fDTS / 16, N = 6<br>1100: fSAMPLING = fDTS / 16, N = 8<br>1101: fSAMPLING = fDTS / 32, N = 5<br>1110: fSAMPLING = fDTS / 32, N = 6<br>1111: fSAMPLING = fDTS / 32, N = 8<br>Note: Care must be taken that fDTS is replaced in the formula by<br>CK_INT when ETF[3:0] = 1, 2 or 3. |
| 7 | MSM | RW | 0 | Master/slave mode<br>0: No action<br>1: The effect of an event on the trigger input (TRGI) is delayed<br>to allow a perfect synchronization between the current timer and<br>its slaves (through TRGO). It is useful if we want to synchronize<br>several timers on a single external event. |
| 6:4 | TS[2:0] | RW | 000 | Trigger selection<br>This 3 bits are selected as the trigger inputs for synchronizing the<br>counter.<br>000: TIM14 (ITR0)<br>001: Reserved (ITR1)<br>010: Reserved (ITR2)<br>011: Reserved (ITR3)<br>100: TI1 Edge Detector (TI1F_ED)<br>101: Filtered Timer Input 1 (TI1FP1)<br>110: Filtered Timer Input 2 (TI2FP2)<br>111: External Trigger input (ETRF)<br>Note: These bits must be modified only when they are not used<br>to avoid wrong edge detections at the transition. |
| 3 | OCCS | RW | 0 | OCREF clear selection.<br>This bit is used to select the OCREF clear source.<br>0: OCREF_CLR_INT is connected to the OCREF_CLR input<br>1: OCREF_CLR_INT is connected to ETRF |
| 2:0 | SMS[2:0] | RW | 000 | Slave mode selection |
| Bit | Name | R/W | Reset Value | Function |
|-----|------|-----|-------------|------------------------------------------------------------------------------------------------------------------------------------------|
| | | | | |
| | | | | When external signals are selected the active edge of the trigger<br>signal (TRGI) is linked to the polarity selected on the external in |
| | | | | |
| | | | | put (see Input Control register and Control Register description). |
| | | | | 000: Slave mode disabled |
| | | | | if CEN = '1' then the prescaler is clocked directly by the internal |
| | | | | clock. |
| | | | | 001: Encoder mode 1 |
| | | | | Counter counts up/down on TI2FP1 edge depending on TI1FP2 |
| | | | | level. |
| | | | | 010: Encoder mode 2 |
| | | | | Counter counts up/down on TI1FP2 edge depending on TI2FP1<br>level. |
| | | | | 011: Encoder mode 3 |
| | | | | Integration of Mode 1 and Mode 2 |
| | | | | 100: Reset Mode |
| | | | | Rising edge of the selected trigger input (TRGI) reinitializes the |
| | | | | counter and generates an update of the registers. |
| | | | | 101: Gated Mode |
| | | | | The counter clock is enabled when the trigger input (TRGI) is |
| | | | | high. The counter stops (but is not reset) as soon as the trigger |
| | | | | becomes low. Both start and stop of the counter are controlled. |
| | | | | 110: Trigger Mode |
| | | | | The counter starts at a rising edge of the trigger TRGI (but it is not |
| | | | | reset). Only the start of the counter is controlled. |
| | | | | 111: External Clock Mode 1 |
| | | | | Rising edges of the selected trigger (TRGI) clock the counter. |
| | | | | Note: The gated mode must not be used if TI1F_ED is selected |
| | | | | as the trigger input (TS = '100'). Indeed, TI1F_ED outputs 1 pulse |
| | | | | for each transition on TI1F, whereas the gated mode checks the |
| | | | | level of the trigger signal. |
TIM1 Internal trigger connection
| Slave TIM | ITR0(TS=000) | ITR1(TS=001) | ITR2(TS=010) | ITR3(TS=011) | | | | | | |
|-----------|--------------|--------------|--------------|--------------|--|--|--|--|--|--|
| TIM1 | TIM14 | reserved | reserved | reserved | | | | | | |
## <span id="page-187-0"></span>**15.4.4. TIM1 interrupt enable register (TIM1\_DIER)**
#### **Address offset:**0x0C
| 31 | 30 | 29 | 28 | 27 | 26 | 25 | 24 | 23 | 22 | 21 | 20 | 19 | 18 | 17 | 16 |
|----|-----|-----|-----|-----|-----|-----|-----|-----|-----|------|------|------|------|------|-----|
| Re | | | | | | | | Re | Re | | | | | Re | |
| s | Res | Res | Res | Res | Res | Res | Res | s | s | Res | Res | Res | Res | s | Res |
| - | - | - | - | - | - | - | - | - | - | - | - | - | - | - | - |
| 15 | 14 | 13 | 12 | 11 | 10 | 9 | 8 | 7 | 6 | 5 | 4 | 3 | 2 | 1 | 0 |
| Re | RE | RE | RE | RE | RE | RE | RE | | | COMI | CC4I | CC3I | CC2I | CC1I | UI |
| s | S | S | S | S | S | S | S | BIE | TIE | E | E | E | E | E | E |
| | | | | | | | | | | | | | | | R |
| - | - | - | - | - | - | - | - | RW | RW | RW | RW | RW | RW | RW | W |
| Bit | Name | R/W | Reset Value | Function |
|------|----------|-----|-------------|--------------------------------------|
| 31:8 | Reserved | | | Reserved,must be kept at reset value |
| | | | | BIE:Break interrupt enable |
| 7 | BIE | RW | 0 | 0:Break interrupt disabled |
| | | | | 1:Break interrupt enable |
| | TIE | RW | 0 | TIE:Trigger interrupt enable |
| 6 | | | | 0:Trigger interrupt disabled |
| | | | | 1:Trigger interrupt enabled |
| | | | | COMIE:COM interrupt enable |
| 5 | COMIE | RW | 0 | 0:COM interrupt disabled |
| | | | | 1:COM interrupt enabled |
| Bit | Name | R/W | Reset Value | Function |
|-----|-------|-----|-------------|------------------------------------------|
| | | | | CC4IE:Capture/Compare 4 interrupt enable |
| 4 | CC4IE | RW | 0 | 0:CC4 interrupt disabled |
| | | | | 1:CC4 interrupt enabled |
| | | | | CC3IE:Capture/Compare 3 interrupt enable |
| 3 | CC3IE | RW | 0 | 0:CC3 interrupt disabled |
| | | | | 1:CC3 interrupt enabled |
| | | | | CC2IE:Capture/Compare 2 interrupt enable |
| 2 | CC2IE | RW | 0 | 0:CC2 interrupt disabled |
| | | | | 1:CC2 interrupt enabled |
| | | | | CC1IE:Capture/Compare 1 interrupt enable |
| 1 | CC1IE | RW | 0 | 0:CC1 interrupt disabled |
| | | | | 1:CC1 interrupt enabled |
| | | | | UIE:Update interrupt enable |
| 0 | UIE | RW | 0 | 0:Update interrupt disabled |
| | | | | 1:Update interrupt enabled |
## <span id="page-188-0"></span>**15.4.5. TIM1 status register (TIM1\_SR)**
#### **Address offset:**0x010
| 31 | 30 | 29 | 28 | 27 | 26 | 25 | 24 | 23 | 22 | 21 | 20 | 19 | 18 | 17 | 16 |
|----|----|----|-----|-----|-----|-----|----|-------|-------|-------|-------|------|-------|-------|-------|
| R | R | R | Res | Res | Res | Res | R | IC4IF | IC3IF | IC2IF | IC1IF | IC4I | IC3IR | IC2I | IC1IR |
| es | es | es | | | | | es | | | | | R | | R | |
| | | | | | | | | RC_ | RC_ | RC_ | RC_ | RC_ | RC_ | RC_ | RC_ |
| - | - | - | - | - | - | - | - | W0 | W0 | W0 | W0 | W0 | W0 | W0 | W0 |
| 15 | 14 | 13 | 12 | 11 | 10 | 9 | 8 | 7 | 6 | 5 | 4 | 3 | 2 | 1 | 0 |
| R | R | R | CC4 | CC3 | CC2 | CC1 | R | | | COM | CC4I | CC3I | CC2I | | |
| es | es | es | OF | OF | OF | OF | es | BIF | TIF | IF | F | F | F | CC1IF | UIF |
| | | | Rc_ | Rc_ | Rc_ | Rc_ | | Rc_ | Rc_ | Rc_ | Rc_ | Rc_ | Rc_ | | Rc_ |
| - | - | - | w0 | w0 | w0 | w0 | - | w0 | w0 | w0 | w0 | w0 | w0 | Rc_w0 | w0 |
| Bit | Name | R/W | Reset<br>Value | Function | | | |
|-------|----------|-------|----------------|-----------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------|--|--|--|
| 31:24 | Reserved | - | 0 | Reserved, must be kept at reset value | | | |
| 23 | IC4IF | RC_W0 | 0 | Falling edge capture 4 flag<br>refer to IC1IF description | | | |
| 22 | IC3IF | RC_W0 | 0 | Falling edge capture 3 flag<br>refer to IC1IF description | | | |
| 21 | IC2IF | RC_W0 | 0 | Falling edge capture 2 flag<br>refer to IC1IF description | | | |
| 20 | IC1IF | RC_W0 | 0 | Falling edge capture 1 flag<br>refer to IC1IF description<br>This flag can be set by hardware to 1 only when the corre<br>sponding channel is configured for input capture and the<br>capture event is triggered by the falling edge. It is cleared<br>by software as' 0 'or by reading TIMx_ CCR1 clear '0'.<br>0: No duplicate capture generation.<br>1: Falling edge capture event occurs. | | | |
| 19 | IC4IR | RC_W0 | 0 | Rising edge capture 4 flag<br>refer to IC1IR description | | | |
| 18 | IC3IR | RC_W0 | 0 | Rising edge capture 3 flag<br>refer to IC1IR description | | | |
| 17 | IC2IR | RC_W0 | 0 | Rising edge capture 2 flag<br>refer to IC1IR description | | | |
| 16 | IC1IR | RC_W0 | 0 | Rising edge capture 1 flag<br>This flag can be set by hardware to 1 only when the corre<br>sponding channel is configured for input capture and the | | | |
| Bit | Name | R/W | Reset<br>Function<br>Value | |
|-----|-------|-------|----------------------------|-----------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------|
| | | | | capture event is triggered by the rising edge. It is cleared<br>by software as' 0 'or by reading TIMx_ CCR1 clear<br>0: No duplicate capture generation.<br>1: Rising edge capture event occurs. |
| 12 | CC4OF | Rc_w0 | 0 | Capture/Compare 4 overcapture flag<br>refer to CC1OF description |
| 11 | CC3OF | Rc_w0 | 0 | Capture/Compare 3 overcapture flag<br>refer to CC1OF description |
| 10 | CC2OF | Rc_w0 | 0 | Capture/Compare 2 overcapture flag<br>refer to CC1OF description |
| 9 | CC1OF | Rc_w0 | 0 | Capture/Compare 1 overcapture flag<br>This flag is set by hardware only when the corresponding<br>channel is configured in input capture mode. It is cleared<br>by software by writing it to '0'.<br>0: No overcapture has been detected.<br>1: The counter value has been captured in TIMx_CCR1<br>register while CC1OF flag was already set |
| 8 | Res | Rc_w0 | 0 | Reserved, must be kept at reset value. |
| 7 | BIF | Rc_w0 | 0 | Break interrupt flag<br>This flag is set by hardware as soon as the break input goes<br>active. It can be cleared by software if the break input is not<br>active.<br>0: No break event occurred.<br>1: An active level has been detected on the break input |
| 6 | TIF | Rc_w0 | 0 | Trigger interrupt flag<br>This flag is set by hardware on trigger event (active edge<br>detected on TRGI input when the slave mode controller is<br>enabled in all modes but gated mode.It is cleared by soft<br>ware.<br>0: No trigger event occurred.<br>1: Trigger interrupt pending |
| 5 | COMIF | Rc_w0 | 0 | COM interrupt flag<br>This flag is set by hardware on COM event (when Cap<br>ture/compare Control bits - CCxE, CCxNE, OCxM - have<br>been updated). It is cleared by software by writing it to '0'.<br>0: No COM event occurred.<br>1: COM interrupt pending. |
| 4 | CC4IF | Rc_w0 | 0 | Capture/Compare 4 interrupt flag<br>refer to CC1IF description |
| 3 | CC3IF | Rc_w0 | 0 | Capture/Compare 3 interrupt flag<br>refer to CC1IF description |
| 2 | CC2IF | Rc_w0 | 0 | Capture/Compare 2 interrupt flag<br>refer to CC1IF description |
| 1 | CC1IF | Rc_w0 | 0 | Capture/Compare 1 interrupt flag<br>If channel CC1 is configured as output:<br>This flag is set by hardware when the counter matches the<br>compare value, with some exception in center<br>-aligned<br>mode (refer to the CMS bits in the TIM1_CR1 register de<br>scription).<br>It is cleared by software.<br>0: No match.<br>1:The content of the counter TIM1_CNT matches the con<br>tent of the TIM1_CCR1 register.<br>If channel CC1 is configured as input:<br>This bit is set by hardware on a capture. It is cleared by<br>software or by reading the TIM1_CCR1 register.<br>0: No input capture occurred<br>1: The counter value has been captured in TIM<br>1_CCR1<br>register (An edge has been detected on IC1 which matches<br>the selected polarity)<br>Note:The bit will also be set when CEN is turned on. |
| 0 | UIF | Rc_w0 | 0 | Update interrupt flag<br>This bit is set by hardware on an update event. It is cleared<br>by software.<br>0: No update occurred.<br>1: Update interrupt pending. This bit is set by hardware<br>when the registers are updated: |
| Bit | Name | R/W | Reset<br>Value | Function |
|-----|------|-----|----------------|-------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------|
| | | | | –if the UDIS = 0 in the TIM1_CR1 register. When<br>REP_CNT=0 generate an update event.(At overflow or un<br>derflow regarding the repetition counter value )<br>–If UDIS=0, URS=0 in TIM1_CR1 register, when the UG=1<br>in TIM1_EGR register generate an update event (software<br>reinitializes the CNT);<br>–When CNT is reinitialized by a trigger event (refer to TIM1<br>slave mode control register (TIM1_SMCR)), if URS = 0 and<br>UDIS = 0 in the TIM1_CR1 register. |
## <span id="page-190-0"></span>**15.4.6. TIM1 event generation register (TIM1\_EGR)**
#### **Address offset:**0x14
| 31 | 30 | 29 | 28 | 27 | 26 | 25 | 24 | 23 | 22 | 21 | 20 | 19 | 18 | 17 | 16 |
|-----|-----|-----|-----|-----|-----|-----|-----|-----|-----|------|------|------|------|------|-----|
| Res | Res | Res | Res | Res | Res | Res | Res | Res | Res | Res | Res | Res | Res | Res | Res |
| - | - | - | - | - | - | - | - | - | - | - | - | - | - | - | - |
| 15 | 14 | 13 | 12 | 11 | 10 | 9 | 8 | 7 | 6 | 5 | 4 | 3 | 2 | 1 | 0 |
| Res | Res | Res | Res | Res | Res | Res | Res | BG | TG | COMG | CC4G | CC3G | CC2G | CC1G | UG |
| - | - | - | -- | - | - | - | - | W | W | W | W | W | W | W | W |
| Bit | Name | R/W<br>Reset Value | | Function | | | |
|------|----------|--------------------|---|-----------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------|--|--|--|
| 31:8 | Reserved | - | 0 | Reserved, must be kept at reset value. | | | |
| 7 | BG | W | 0 | Break generation<br>This bit is set by software in order to generate an event, it<br>is automatically cleared by hardware.<br>0:No action;<br>1:A break event is generated. MOE bit is cleared and<br>BIF flag is set. Related interrupt can occur if enabled. | | | |
| 6 | TG | W | 0 | Trigger generation<br>This bit is set by software in order to generate an event, it<br>is automatically cleared by hardware.<br>0: No action<br>1: The TIF flag is set in TIM1_SR register. Related interrupt<br>can occur if enabled. | | | |
| 5 | COMG | W | 0 | Capture/Compare control update generation<br>This bit can be set by software, it is automatically cleared<br>by hardware<br>0: No action<br>1: When CCPC bit is set, it allows to update CCxE, CCxNE<br>and OCxM bits<br>Note: This bit acts only on channels having a complemen<br>tary output. | | | |
| 4 | CC4G | W | 0 | Capture/Compare 4 generation<br>Refer to CC1G description | | | |
| 3 | CC3G | W | 0 | Capture/Compare 3 generation<br>Refer to CC1G description | | | |
| 2 | CC2G | W | 0 | Capture/Compare 2 generation<br>Refer to CC1G description | | | |
| 1 | CC1G | W | 0 | Capture/Compare 1 generation<br>This bit is set by software in order to generate an cap<br>ture/compare event, it is automatically cleared by hardware.<br>0: No action<br>1: A capture/compare event is generated on channel CC1:<br>If channel CC1 is configured as output:<br>CC1IF flag is set, Corresponding interrupt if enabled.<br>If channel CC1 is configured as input:<br>The current value of the counter is captured in TIM1_CCR1<br>register. The CC1IF flag is set, the corresponding interrupt<br>if enabled. The CC1OF flag is set if the CC1IF flag was al<br>ready be set. | | | |
| 0 | UG | W | 0 | Update generation | | | |
| Bit | Name | R/W | Reset Value | Function |
|-----|------|-----|-------------|----------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------|
| | | | | This bit can be set by software, it is automatically cleared<br>by hardware.<br>0: No action<br>1: Reinitialize the counter and generates an update of the<br>registers.<br>Note:that the prescaler counter is cleared too (anyway the<br>prescaler ratio is not affected). The counter is cleared if the<br>center-aligned mode is selected or if DIR = 0 (upcounting),<br>else it takes the auto-reload value (TIM1_ARR) if DIR = 1<br>(downcounting). |
## <span id="page-191-0"></span>**15.4.7. TIM1 capture/compare mode register1 (TIM1\_CCMR1)**
### **Address offset:**0x18
**Reset value:**0x0000 0000
#### **Output compare mode:**
| 31 | 30 | 29 | 28 | 27 | 26 | 25 | 24 | 23 | 22 | 21 | 20 | 19 | 18 | 17 | 16 |
|------|----|-----------|----|------|------|----------|----|------|----|-----------|----|------|------|-----|-----------|
| Res | Re | Re | Re | Res | Res | Re | Re | Res | Re | Re | Re | Res | Res | Res | Re |
| | s | s | s | | | s | s | | s | s | s | | | | s |
| - | - | - | - | - | - | - | - | - | - | - | - | - | - | - | - |
| 15 | 14 | 13 | 12 | 11 | 10 | 9 | 8 | 7 | 6 | 5 | 4 | 3 | 2 | 1 | 0 |
| OC2C | | OC2M[2:0] | | OC2P | CO2F | CC2S[1:0 | | OC1C | | OC1M[2:0] | | OC1P | OC1F | | CC1S[1:0] |
| E | | | | E | E | ] | | E | | | | E | E | | |
| | R | R | R | | | R | R | | R | R | R | | | R | |
| RW | W | W | W | RW | RW | W | W | RW | W | W | W | RW | RW | W | RW |
| Bit | Name | R/W | Reset Value | Function |
|-------|-----------|-----|-------------|------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------|
| 31:16 | Reserved | - | | Reserved, must be kept at reset value. |
| 15 | OC2CE | RW | 0 | Output Compare 2 clear enable |
| 14:12 | OC2M[2:0] | RW | 000 | Output Compare 2 mode selection |
| 11 | OC2PE | RW | 0 | Output Compare 2 preload enable |
| 10 | OC2FE | RW | 0 | Output Compare 2 fast enable |
| 9:8 | CC2S[1:0] | RW | 00 | Capture/Compare 2 selection<br>This bit-field defines the direction of the channel (input/out<br>put) as well as the used input.<br>00: CC2 channel is configured as output<br>01: CC2 channel is configured as input, IC2 is mapped on<br>TI2<br>10: CC2 channel is configured as input, IC2 is mapped on<br>TI1<br>11: CC2 channel is configured as input, IC2 is mapped on<br>TRC. This mode is working only if an internal trigger input<br>is selected through the TS bit (TIM1_SMCR register)<br>Note: CC2S bits are writable only when the channel is OFF<br>(CC2E = '0' in TIM1_CCER). |
| 7 | OC1CE | RW | 0 | Output Compare 1 clear enable<br>OC1CE: Output Compare 1 Clear Enable<br>0: OC1Ref is not affected by the ETRF Input<br>1: OC1Ref is cleared as soon as a High level is detected<br>on ETRF input |
| 6:4 | OC1M[2:0] | RW | 00 | Output Compare 1 mode<br>These bits define the behavior of the output reference sig<br>nal OC1REF from which OC1 and OC1N are derived.<br>OC1REF is active high whereas OC1 and OC1N active<br>level depends on CC1P and CC1NP bits.<br>000:Frozen - The comparison between the output com<br>pare register TIM1_CCR1 and the counter TIM1_CNT has<br>no effect on the OC1REF.<br>001:Set channel 1 to active level on match. OC1REF sig<br>nal is forced high when the counter TIMx_CNT matches the<br>capture/compare register 1 (TIMx_CCR1). |
| Bit | Name | R/W | Reset Value | Function |
|-----|-----------|-----|-------------|--------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------|
| | | | | 010 :Set channel 1 to inactive level on match. OC1REF<br>signal is forced low when the counter TIMx_CNT matches<br>the capture/compare register 1 (TIMx_CCR1). |
| | | | | 011 : Toggle -<br>OC1REF toggles when TIM1_CNT =<br>TIM1_CCR1. |
| | | | | 100:Force inactive level - OC1REF is forced low. |
| | | | | 101:Force active level - OC1REF is forced high. |
| | | | | 110: PWM mode 1 - In upcounting, channel 1 is active as<br>long<br>as<br>TIM1_CNT<TIM1_CCR1<br>else<br>inactive.<br>In<br>downcounting, channel 1 is inactive (OC1REF = '0') as long<br>as TIM1_CNT > TIM1_CCR1 else active (OC1REF= '1'). |
| | | | | 111:PWM mode 2 - In upcounting, channel 1 is inactive<br>as long as TIM1_CNT < TIM1_CCR1 else active. In<br>downcounting, channel 1 is active as long as TIM1_CNT ><br>TIM1_CCR1 else inactive. |
| | | | | Note1:These bits can not be modified as long as LOCK<br>level 3 has been programmed(LOCK bits in TIMx_BDTR<br>register) and CC1S = '00' (the channel is configured in out |
| | | | | put).<br>Note2: In PWM mode 1 or 2, the OCREF level changes only<br>when the result of the comparison changes or when the out |
| | | | | put compare mode switches from "frozen" mode to "PWM"<br>mode. |
| | OC1PE | RW | 0 | Output Compare 1 preload enable<br>0: Preload register on TIM1_CCR1 disabled. TIM1_CCR1<br>can be written at anytime, the new value is taken in account<br>immediately. |
| 3 | | | | 1: Preload register on TIM1_CCR1 enabled. Read/Write<br>operations access the preload register. TIM1_CCR1 pre<br>load value is loaded in the active register at each update<br>event. |
| | | | | Note: 1: These bits can not be modified as long as LOCK<br>level 3 has been programmed (LOCK bits in TIMx_BDTR<br>register) and CC1S = '00' (the channel is configured in out<br>put).<br>2: The PWM mode can be used without validating the pre |
| | | | | load register only in one pulse mode. Else the behavior is<br>not guaranteed. |
| | | RW | 0 | Output Compare 1 fast enable<br>This bit is used to accelerate the effect of an event on the<br>trigger in input on the CC output. |
| | | | | 0: CC1 behaves normally depending on counter and CCR1<br>values even when the trigger is ON. The minimum delay to<br>activate CC1 output when an edge occurs on the trigger |
| 2 | OC1FE | | | input is 5 clock cycles.<br>1: An active edge on the trigger input acts like a compare<br>match on CC1 output. Then, OC is set to the compare level<br>independently from the result of the comparison. Delay to<br>sample the trigger input and to activate CC1 output is re<br>duced to 3 clock cycles. OCFE acts only if the channel is<br>configured in PWM1 or PWM2 mode. |
| | | | 00 | Capture/Compare 1 selection<br>This bit-field defines the direction of the channel (input/out<br>put) as well as the used input.<br>00: CC1 channel is configured as output<br>01: CC1 channel is configured as input, IC1 is mapped on |
| 1:0 | CC1S[1:0] | RW | | TI1<br>10: CC1 channel is configured as input, IC1 is mapped on<br>TI2 |
| | | | | 11: CC1 channel is configured as input, IC1 is mapped on<br>TRC. This mode is working only if an internal trigger input<br>is selected through TS bit (TIMx_SMCR register)<br>Note: CC1S bits are writable only when the channel is OFF<br>(CC1E = '0' in TIM1_CCER). |
| | | | Input Capture mode: | | | | | | | | | | | | |
|---------------------------------------|-----|-----|---------------------|-----------|-----|-----|-----|-------------|-----|-----------|-----|-----|-----|-----|-----|
| 31 | 30 | 29 | 28 | 27 | 26 | 25 | 24 | 23 | 22 | 21 | 20 | 19 | 18 | 17 | 16 |
| Res | Res | Res | Res | Res | Res | Res | Res | Res | Res | Res | Res | Res | Res | Res | Res |
| - | - | - | - | - | - | - | - | - | - | - | - | - | - | - | - |
| 15 | 14 | 13 | 12 | 11 | 10 | 9 | 8 | 7 | 6 | 5 | 4 | 3 | 2 | 1 | 0 |
| IC2F[3:0]<br>IC2PSC[1:0]<br>CC2S[1:0] | | | | IC1F[3:0] | | | | IC1PSC[1:0] | | CC1S[1:0] | | | | | |
| RW | RW | RW | RW | RW | RW | RW | RW | RW | RW | RW | RW | RW | RW | RW | RW |
**Input Capture mode:**
| Bit | Name | R/W | Reset Value | Function |
|-------|-------------|-----|-------------|---------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------|
| 31:16 | Reserved | - | | Reserved, must be kept at reset value. |
| 15:12 | IC2F | RW | 0000 | Input capture 2 filter |
| 11:10 | IC2PSC[1:0] | RW | 00 | Input/capture 2 prescaler |
| 9:8 | CC2S[1:0] | RW | 0 | Capture/Compare 2 selection<br>This two bits defines the direction of the channel (input/out<br>put) as well as the used input.<br>00: CC2 channel is configured as output<br>01: CC2 channel is configured as input, IC2 is mapped on<br>TI2<br>10: CC2 channel is configured as input, IC2 is mapped on |
| | | | | TI1<br>11: CC2 channel is configured as input, IC2 is mapped on<br>TRC. This mode is working only if an internal trigger input<br>is selected through TS bit (TIM1_SMCR register)<br>Note: CC2S bits are writable only when the channel is OFF<br>(CC2E = '0' in TIM1_CCER) |
| 7:4 | IC1F[3:0] | RW | 0000 | Input capture 1 filter<br>This bit-field defines the frequency used to sample TI1 input<br>and the length of the digital filter applied to TI1. The digital<br>filter is made of an event counter in which N consecutive<br>events are needed to validate a transition on the output:<br>0000: No filter, sampling is done at fDTS<br>1000: fSAMPLING=fDTS/8, N=6<br>0001: fSAMPLING = fCK_INT, N = 2<br>1001: fSAMPLING=fDTS/8,N=8<br>0010: fSAMPLING = fCK_INT, N = 4<br>1010:fSAMPLING=fDTS/16,N=5<br>0011:fSAMPLING=fCK_INT,N=8<br>1011:fSAMPLING=fDTS/16,N=6<br>0100:fSAMPLING=fDTS/2,N=6<br>1100:fSAMPLING=fDTS/16,N=8<br>0101:fSAMPLING=fDTS/2,N=8<br>1101:fSAMPLING=fDTS/32,N=5<br>0110:fSAMPLING=fDTS/4,N=6<br>1110:fSAMPLING=fDTS/32,N=6<br>0111:fSAMPLING=fDTS/4,N=8 |
| 3:2 | IC1PSC[1:0] | RW | 00 | 1111:fSAMPLING=fDTS/32,N=8<br>Input capture 1 prescaler<br>This two bits defines the ratio of the prescaler acting on<br>CC1 input (IC1). The prescaler is reset as soon as CC1E<br>= '0' (TIM1_CCER register).<br>00: no prescaler, capture is done each time an edge is de<br>tected on the capture input<br>01: capture is done once every 2 events<br>10: capture is done once every 4 events<br>11: capture is done once every 8 events |
| 1:0 | CC1S[1:0] | RW | 00 | Capture/Compare 1 Selection<br>This two bits defines the direction of the channel (input/out<br>put) as well as the used input.<br>00: CC1 channel is configured as output<br>01: CC1 channel is configured as input, IC1 is mapped on<br>TI1 |
| Bit | Name | R/W | Reset Value | Function |
|-----|------|-----|-------------|------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------|
| | | | | 10: CC1 channel is configured as input, IC1 is mapped on<br>TI2<br>11: CC1 channel is configured as input, IC1 is mapped on<br>TRC. This mode is working only if an internal trigger input<br>is selected through TS bit (TIM1_SMCR register)<br>Note: CC1S bits are writable only when the channel is OFF<br>(CC1E = '0' in TIM1_CCER). |
## <span id="page-194-0"></span>**15.4.8. TIM1 capture/compare mode register 2 (TIM1\_CCMR2)**
#### **Address offset:**0x1C
**Reset value:**0x0000 0000
#### **Output compare mode:**
| 31 | 30 | 29 | 28 | 27 | 26 | 25 | 24 | 23 | 22 | 21 | 20 | 19 | 18 | 17 | 16 |
|-----------|----|-----------|-------------|------|------|-----------|----|------|-------------|-----------|----|------|------|-----------|----|
| Res | Re | Re | Re | Res | Res | Re | Re | Res | Re | Re | Re | Res | Res | Res | Re |
| | s | s | s | | | s | s | | s | s | s | | | | s |
| - | - | - | - | - | - | - | - | - | - | - | - | - | - | - | - |
| 15 | 14 | 13 | 12 | 11 | 10 | 9 | 8 | 7 | 6 | 5 | 4 | 3 | 2 | 1 | 0 |
| OC4C | | | | OC4P | CO4F | | | OC3C | | | | OC3P | OC3F | | |
| E | | OC4M[2:0] | | E | E | CC4S[1:0 | | E | | OC3M[2:0] | | E | E | CC3S[1:0] | |
| IC4F[3:0] | | | IC4PSC[1:0] | ] | | IC3F[3:0] | | | IC3PSC[1:0] | | | | | | |
| | R | R | R | | | R | R | | R | R | R | | | R | |
| RW | W | W | W | RW | RW | W | W | RW | W | W | W | RW | RW | W | RW |
| Bit | Name | R/W | Reset Value | Function |
|-------|-----------|-----|-------------|--------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------|
| 31:16 | Reserved | - | | Reserved, must be kept at reset value. |
| 15 | OC4CE | RW | 0 | Output compare 4 clear enable |
| 14:12 | OC4M[2:0] | RW | 000 | Output compare 4 mode |
| 11 | OC4PE | RW | 0 | Output compare 4 preload enable |
| 10 | OC4FE | RW | 0 | Output compare 4 fast enable |
| 9:8 | CC4S[1:0] | RW | 00 | Capture/Compare 4 selection<br>This bit-field defines the direction of the channel (in<br>put/output) as well as the used input.<br>00: CC4 channel is configured as output<br>01: CC4 channel is configured as input, IC4 is mapped on<br>TI4<br>10: CC4 channel is configured as input, IC4 is mapped on<br>TI3<br>11: CC4 channel is configured as input, IC4 is mapped on<br>TRC. This mode is working only if an internal trigger input<br>is selected through TS bit (TIM1_SMCR register)<br>Note: CC4S bits are writable only when the channel is<br>OFF (CC4E = '0' in TIM1_CCER). |
| 7 | OC3CE | RW | 0 | Output compare 3 clear enable |
| 6:4 | OC3M[2:0] | RW | 00 | Output compare 3 mode |
| 3 | OC3PE | RW | 0 | Output compare 3 preload enable |
| 2 | OC3FE | RW | 0 | Output compare 3 fast enable |
| 1:0 | CC3S[1:0] | RW | 00 | Capture/Compare 3 selection<br>This bit-field defines the direction of the channel (input/out<br>put) as well as the used input.<br>00: CC3 channel is configured as output<br>01: CC3 channel is configured as input, IC3 is mapped on<br>TI3<br>10: CC3 channel is configured as input, IC3 is mapped on<br>TI4<br>11: CC3 channel is configured as input, IC3 is mapped on<br>TRC. This mode is working only if an internal trigger input<br>is selected through TS bit (TIM1_SMCR register)<br>Note: CC3S bits are writable only when the channel is OFF<br>(CC3E = '0' in TIM1_CCER) |
**Input Capture mode:**
| Bit | Name | R/W | Reset Value | Function |
|-------|----------|-----|-------------|--------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------|
| 31:16 | Reserved | - | | Reserved, must be kept at reset value. |
| 15:12 | IC4F | RW | 0000 | Input capture 4 filter |
| 11:10 | IC4PSC | RW | 00 | Input capture 4 prescaler |
| 9:8 | CC4S | RW | 00 | Capture/Compare 4 selection<br>This bit-field defines the direction of the channel (input/out<br>put) as well as the used input.<br>00: CC4 channel is configured as output<br>01: CC4 channel is configured as input, IC4 is mapped on<br>TI4<br>10: CC4 channel is configured as input, IC4 is mapped on<br>TI3<br>11: CC4 channel is configured as input, IC4 is mapped on<br>TRC. This mode is working only if an internal trigger input<br>is selected through TS bit (TIM1_SMCR register)<br>Note: CC4S bits are writable only when the channel is OFF<br>(CC4E = '0' in TIM1_CCER) |
| 7:4 | IC3F | RW | 0000 | Input capture 3 filter |
| 3:2 | IC3PSC | RW | 00 | Input capture 3 prescaler |
| 1:0 | OC3S | RW | 00 | Capture/compare 3 selection<br>This bit-field defines the direction of the channel (input/out<br>put) as well as the used input.<br>00: CC3 channel is configured as output<br>01: CC3 channel is configured as input, IC3 is mapped on<br>TI3<br>10: CC3 channel is configured as input, IC3 is mapped on<br>TI4<br>11: CC3 channel is configured as input, IC3 is mapped on<br>TRC. This mode is working only if an internal trigger input<br>is selected through TS bit (TIM1_SMCR register)<br>Note: CC3S bits are writable only when the channel is OFF<br>(CC3E = '0' in TIM1_CCER). |
## <span id="page-195-0"></span>**15.4.9. TIM1 capture/compare enable register (TIM1\_CCER)**
#### **Address offset:**0x20
| 31 | 30 | 29 | 28 | 27 | 26 | 25 | 24 | 23 | 22 | 21 | 20 | 19 | 18 | 17 | 16 |
|---------|---------|----------|----------|-----------|-----------|----------|----------|-----------|-----------|----------|----------|-----------|-----------|----------|----------|
| Re | Re | Res | Res | Res | Res | Res | Res | Res | Res | Res | Res | Res | Res | Res | Res |
| s | s | | | | | | | | | | | | | | |
| - | - | - | - | - | - | - | - | - | - | - | - | - | - | - | - |
| | | | | | | | | | | | | | | | |
| 15 | 14 | 13 | 12 | 11 | 10 | 9 | 8 | 7 | 6 | 5 | 4 | 3 | 2 | 1 | 0 |
| | | | | | | | | | | | | | | | |
| Re<br>s | Re<br>s | CC4<br>P | CC4<br>E | CC3<br>NP | CC3<br>NE | CC3<br>P | CC3<br>E | CC2<br>NP | CC2<br>NE | CC2<br>P | CC2<br>E | CC1<br>NP | CC1<br>NE | CC1<br>P | CC1<br>E |
| Bit | Name | R/W | Reset Value | Function |
|-------|----------|-----|-------------|-------------------------------------------------------------------------------|
| 31:14 | Reserved | - | 0 | Reserved, must be kept at reset value. |
| 13 | CC4P | RW | 0 | Capture/Compare 4 output polarity<br>refer to CC1P description |
| 12 | CC4E | RW | 0 | Capture/Compare 4 output enable<br>refer to CC1E description |
| 11 | CC3NP | RW | 0 | Capture/Compare 3 complementary output polarity<br>refer to CC1NP description |
| 10 | CC3NE | RW | 0 | Capture/Compare 3 complementary output enable<br>refer to CC1NE description |
| 9 | CC3P | RW | 0 | Capture/Compare 3 output polarity<br>refer to CC1P description |
| 8 | CC3E | RW | 0 | Capture/Compare 3 output enable<br>refer to CC1E description |
| 7 | CC2NP | RW | 0 | Capture/Compare 2 complementary output polarity<br>refer to CC1NP description |
| 6 | CC2NE | RW | 0 | Capture/Compare 2 complementary output enable<br>refer to CC1NE description |
| 5 | CC2P | RW | 0 | Capture/Compare 2 output polarity |
| Bit | Name | R/W | Reset Value | Function |
|-----|-------|-----|-------------|------------------------------------------------------------------------------------------------------------------------------|
| | | | | refer to CC1P description |
| 4 | CC2E | RW | 0 | Capture/Compare 2 output enable |
| | | | 0 | refer to CC1E description |
| | | RW | | Capture/Compare 1 complementary output polarity<br>0: OC1N active high. |
| | CC1NP | | | 1: OC1N active low. |
| 3 | | | | Note: This bit is not writable as soon as LOCK level 2 or 3 |
| | | | | has been programmed (LOCK bits in TIM1_BDTR register) |
| | | | | and CC1S = "00" (the channel is configured in output).<br>Capture/Compare 1 complementary output enable |
| | | | | 0: Off - OC1N is not active. OC1N level is then function of |
| 2 | CC1NE | RW | 0 | MOE, OSSI, OSSR, OIS1, OIS1N and CC1E bits. |
| | | | | 1: On - OC1N signal is output on the corresponding output |
| | | | | pin depending on MOE, OSSI, OSSR, OIS1, OIS1N and<br>CC1E bits. |
| | | | | Capture/Compare 1 output polarity |
| | | | | CC1 channel configured as output: |
| | | | | 0: OC1 active high |
| | | | | 1: OC1 active low<br>CC1 channel configured as input: |
| | | | | CC1NP/CC1P bits select the active polarity of TI1FP1 and |
| | | | | TI2FP1 for trigger or capture operations. |
| | | | | 00: non-inverted/rising edge |
| | | | | The circuit is sensitive to TIxFP1 rising edge (capture or<br>trigger operations in reset, external clock or trigger mode), |
| | | | | TIxFP1 is not inverted (trigger operation in gated mode or |
| | | | | encoder mode). |
| | | | | TIxFP1 is not inverted (trigger operation in gated mode or<br>encoder mode). |
| | | | | 01: inverted/falling edge |
| 1 | CC1P | RW | 0 | The circuit is sensitive to TIxFP1 falling edge (capture or |
| | | | | trigger operations in reset, external clock or trigger mode), |
| | | | | TIxFP1 is inverted (trigger operation in gated mode or en<br>coder mode). |
| | | | | 10: reserved, do not use this configuration. |
| | | | | 11: non-inverted/both edges |
| | | | | The circuit is sensitive to both TIxFP1 rising and falling |
| | | | | edges (capture or trigger operations in reset, external clock<br>or trigger mode), TIxFP1 is not inverted (trigger operation |
| | | | | in gated mode). This configuration must not be used in en |
| | | | | coder mode. |
| | | | | Note: On channels having a complementary output, this bit<br>is preloaded. If the CCPC bit is set in the TIMx_CR2 register |
| | | | | then the CC1P active bit takes the new value from the pre |
| | | | | loaded bits only when a Commutation event is generated. |
| | | | | Note: This bit is not writable as soon as LOCK level 2 or 3 |
| | | | | has been programmed (LOCK bits in TIMx_BDTR register).<br>Capture/Compare 1 output enable |
| | | | | CC1 channel configured as output: |
| | | | | 0: Off - OC1 is not active. OC1 level is then function of |
| | | | | MOE, OSSI, OSSR, OIS1, OIS1N and CC1NE bits. |
| | | | | 1: On - OC1 signal is output on the corresponding output<br>pin depending on MOE, OSSI, OSSR, OIS1, OIS1N and |
| 0 | CC1E | RW | 0 | CC1NE bits. |
| | | | | CC1 channel configured as input: |
| | | | | This bit determines if a capture of the counter value can |
| | | | | actually be done into the input capture/compare register 1<br>(TIM1_CCR1) or not. |
| | | | | 0: Capture disabled. |
| | | | | 1: Capture enabled. |
#### Table 15-49 Output control bits for complementary OCx and OCxN channels with break feature
| Control bits | | | | | Output state | |
|--------------|------|------|------|-------|----------------------------------------------------------------------|-------------------------------------------------------------------|
| MOE | OSSI | OSSR | CcxE | CcxNE | OCx output state | OCxN output state |
| 1 | X | 0 | 0 | 0 | Output Disabled (not driven by the<br>timer), OCx = 0,<br>OCx_EN = 0 | Output Disabled (not driven by the<br>timer)<br>OCxN=0, OCxN_EN=0 |
| | | Control bits | | | Output state | | | | | |
|-----|------|--------------|------|-------|-------------------------------------------------------------------------------------------------------------------------------------------------------------------------|---------------------------------------------------------------------------|--|--|--|--|
| MOE | OSSI | OSSR | CcxE | CcxNE | OCx output state | OCxN output state | | | | |
| | | 0 | 0 | 1 | Output Disabled (not driven by the<br>timer), OCx = 0,<br>OCx_EN = 0 | OCxREF + Polarity<br>OCxN=OCxREF xor CCxNP,<br>OCxN_EN=1 | | | | |
| | | 0 | 1 | 0 | OCxREF + Polarity<br>OCx = OCxREF xor CCxP,<br>OCx_EN = 1 | Output Disabled (not driven by the<br>timer)<br>OCxN=0, OCxN_EN=0 | | | | |
| | | 0 | 1 | 1 | OCREF + Polarity + dead-time<br>OCx_EN=1 | Complementary to OCREF(not<br>OCREF)+ Polarity + dead-time<br>OCxN_EN=1 | | | | |
| | | 1 | 0 | 0 | Output Disabled (not driven by the<br>timer)<br>OCx=CCxP, OCx_EN=0 | Output Disabled (not driven by the<br>timer),<br>OCxN=CCxNP, OCxN_EN=0 | | | | |
| | | 1 | 0 | | Output Disabled (not driven by the<br>timer)<br>OCx=CCxP, OCx_EN=1 | OCxREF+Polarity<br>OCxN=OCxREF xor CCxNP,<br>OCxN_EN=1 | | | | |
| | | 1 | 1 | 0 | OCxREF+Polarity<br>OCx=OCxREF xor CCxP,<br>OCx_EN=1 | Off-State (output enabled and<br>invalid level),<br>OCxN=CCxNP, OCxN_EN=1 | | | | |
| | | 1 | 1 | 1 | OCREF+Polarity + dead-time<br>OCx_EN=1 | Complementary to OCREF(not<br>OCREF)+ polarity + dead-time<br>OCN_EN=1 | | | | |
| | 0 | | 0 | 0 | Output Disabled (not driven by the<br>timer),<br>OCx=CCxP, OCx_EN=0 | Output Disabled (not driven by the<br>timer),<br>OCxN=CCxNP, OCxN_EN=0 | | | | |
| | 0 | | 0 | 1 | Output Disabled (not driven by the timer), | | | | | |
| | 0 | | 1 | 0 | Asynchronously: OCx=CCxP, OCx_EN=0, OCxN=CCxNP, OCxN_EN=0 | | | | | |
| | 0 | X | 1 | 1 | Then if the clock is present: OCx = OISx and OCxN = OISxN after a dead<br>time, assuming that OISx and OISxN do not correspond to OCX and OCxN<br>both in active state. | | | | | |
| 0 | 1 | | 0 | 0 | Output Disabled (not driven by the<br>timer),<br>OCx=CCxP, OCx_EN=0 | Output Disabled (not driven by the<br>timer),<br>OCxN=CCxNP, OCxN_EN=0 | | | | |
| | 1 | | 0 | 1 | Off-State (output enabled and invalid level), | | | | | |
| | 1 | | 1 | 0 | Asynchronously: OCx=CCxP, OCx_EN=1,OCxN=CCxNP, OCxN_EN=1 | | | | | |
| | 1 | | 1 | 1 | Then if the clock is present: OCx = OISx and OCxN = OISxN after a dead<br>time, assuming that OISx and OISxN do not correspond to OCX and OCxN<br>both in active state | | | | | |
## <span id="page-197-0"></span>**15.4.10. TIM1 counter (TIM1\_CNT)**
#### **Address offset:**0x24
#### **Reset value:**0x0000 0000
| 31 | 30 | 29 | 28 | 27 | 26 | 25 | 24 | 23 | 22 | 21 | 20 | 19 | 18 | 17 | 16 |
|-----|-----------|-----|-----|-----|-----|-----|-----|-----|-----|-----|-----|-----|-----|-----|-----|
| Res | Res | Res | Res | Res | Res | Res | Res | Res | Res | Res | Res | Res | Res | Res | Res |
| - | - | - | - | - | - | - | - | - | - | - | - | - | - | - | - |
| 15 | 14 | 13 | 12 | 11 | 10 | 9 | 8 | 7 | 6 | 5 | 4 | 3 | 2 | 1 | 0 |
| | CNT[15:0] | | | | | | | | | | | | | | |
| | RW | | | | | | | | | | | | | | |
| Bit | Name | R/W | Reset Value | Function |
|-------|-----------|-----|-------------|---------------------------------------|
| 31:16 | Reserved | | | Reserved, must be kept at reset value |
| 15:0 | CNT[15:0] | RW | 0 | Counter value |
## <span id="page-197-1"></span>**15.4.11. TIM1 prescaler (TIM1\_PSC)**
#### **Address offset:**0x28
| 31 | 30 | 29 | 28 | 27 | 26 | 25 | 24 | 23 | 22 | 21 | 20 | 19 | 18 | 17 | 16 |
|-----|-----|-----|-----|-----|-----|-----|-----|-----|-----|-----|-----|-----|-----|-----|-----|
| Res | Res | Res | Res | Res | Res | Res | Res | Res | Res | Res | Res | Res | Res | Res | Res |
| - | - | - | - | - | - | - | - | - | - | - | - | - | - | - | - |
|----|-----------|----|----|----|----|---|---|---|---|---|---|---|---|---|---|
| 15 | 14 | 13 | 12 | 11 | 10 | 9 | 8 | 7 | 6 | 5 | 4 | 3 | 2 | 1 | 0 |
| | PSC[15:0] | | | | | | | | | | | | | | |
| | | | | | | | | | | | | | | | |
#### RW
| Bit | Name | R/W | Reset Value | Function |
|-------|-----------|-----|-------------|----------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------|
| 31:16 | Reserved | | | Reserved, must be kept at reset value. |
| 15:0 | PSC[15:0] | RW | 0 | Prescaler value<br>The counter clock frequency (CK_CNT) is equal to<br>fCK_PSC / (PSC[15:0] + 1).<br>PSC contains the value to be loaded in the active prescaler<br>register at each update event (including when the counter<br>is cleared through UG bit of TIMx_EGR register or through<br>trigger controller when configured in "reset mode"). |
## <span id="page-198-0"></span>**15.4.12. TIM1 auto-reload register (TIM1\_ARR)**
#### **Address offset:**0x2c
#### **Reset value:**0x0000 FFFF
| 31 | 30 | 29 | 28 | 27 | 26 | 25 | 24 | 23 | 22 | 21 | 20 | 19 | 18 | 17 | 16 |
|-----------|-----|-----|-----|-----|-----|-----|-----|-----|-----|-----|-----|-----|-----|-----|-----|
| Res | Res | Res | Res | Res | Res | Res | Res | Res | Res | Res | Res | Res | Res | Res | Res |
| - | - | - | - | - | - | - | - | - | - | - | - | - | - | - | - |
| 15 | 14 | 13 | 12 | 11 | 10 | 9 | 8 | 7 | 6 | 5 | 4 | 3 | 2 | 1 | 0 |
| ARR[15:0] | | | | | | | | | | | | | | | |
| | | | | | | | | | | | | | | | |
| Bit | Name | R/W | Reset Value | Function |
|-------|-----------|-----|-------------|-----------------------------------------------------------------------------------------------------------------------------------------------------------|
| 31:16 | Reserved | | | Reserved, must be kept at reset value. |
| 15:0 | ARR[15:0] | RW | 0 | Auto-reload value<br>ARR is the value to be loaded in the actual auto-reload reg<br>ister.<br>The counter is blocked while the auto-reload value is null. |
## <span id="page-198-1"></span>**15.4.13. TIM1 repetition counter register (TIM1\_RCR)**
#### **Address offset:**0x30
| 31 | 30 | 29 | 28 | 27 | 26 | 25 | 24 | 23 | 22 | 21 | 20 | 19 | 18 | 17 | 16 | |
|-----|-----|-----|-----|-----|-----|-----|-----|----------|-----|-----|-----|-----|-----|-----|-----|--|
| Res | Res | Res | Res | Res | Res | Res | Res | Res | Res | Res | Res | Res | Res | Res | Res | |
| - | - | - | - | - | - | - | - | - | - | - | - | - | - | - | - | |
| 15 | 14 | 13 | 12 | 11 | 10 | 9 | 8 | 7 | 6 | 5 | 4 | 3 | 2 | 1 | 0 | |
| | | | | | | | | REP[7:0] | | | | | | | | |
| Res | Res | Res | Res | Res | Res | Res | Res | | | | | | | | | |
| Bit | Name | R/W | Reset Value | Function |
|------|----------|-----|-------------|----------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------|
| 31:8 | Reserved | | | Reserved, must be kept at reset value. |
| 7:0 | REP[7:0] | RW | 0 | Repetition counter value<br>These bits allow the user to set-up the update rate of the<br>compare registers (i.e. periodic transfers from preload to<br>active registers) when preload registers are enable, as well<br>as the update interrupt generation rate, if this interrupt is<br>enable.<br>Each time the REP_CNT related downcounter reaches<br>zero, an update event is generated and it restarts counting<br>from REP value. As REP_CNT is reloaded with REP value<br>only at the repetition update event U_RC, any write to the<br>TIMx_RCR register is not taken in account until the next<br>repetition update event.<br>It means in PWM mode (REP+1) corresponds to:<br>– the number of PWM periods in edge-aligned mode<br>– the number of half PWM period in center-aligned mode. |
## <span id="page-199-0"></span>**15.4.14. TIM1 capture/compare register 1 (TIM1\_CCR1)**
#### **Address offset:**0x34
| 31 | 30 | 29 | 28 | 27 | 26 | 25 | 24 | 23 | 22 | 21 | 20 | 19 | 18 | 17 | 16 |
|------------|-----|-----|-----|-----|-----|-----|-----|-----|-----|-----|-----|-----|-----|-----|-----|
| Res | Res | Res | Res | Res | Res | Res | Res | Res | Res | Res | Res | Res | Res | Res | Res |
| - | - | - | - | - | - | - | - | - | - | - | - | - | - | - | - |
| 15 | 14 | 13 | 12 | 11 | 10 | 9 | 8 | 7 | 6 | 5 | 4 | 3 | 2 | 1 | 0 |
| CCR1[15:0] | | | | | | | | | | | | | | | |
| | RW | | | | | | | | | | | | | | |
**Reset value:**0x0000 0000
| Bit | Name | R/W | Reset Value | Function |
|-------|------------|-----|-------------|--------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------|
| 31:16 | Reserved | | | Reserved, must be kept at reset value. |
| 15:0 | CCR1[15:0] | RW | 0 | Capture/Compare 1 value<br>If channel CC1 is configured as output:<br>CCR1 is the value to be loaded in the actual capture/com<br>pare 1 register (preload value).<br>It is loaded permanently if the preload feature is not se<br>lected in the TIM1_CCMR1 register (bit OC1PE). Else the<br>preload value is copied in the active capture/compare 1 reg<br>ister when an update event occurs.<br>The active capture/compare register contains the value to<br>be compared to the counter TIM1_CNT and signaled on<br>OC1 output.<br>If channel CC1 is configured as input:<br>CCR1 is the counter value transferred by the last input cap<br>ture 1 event (IC1). |
## <span id="page-199-1"></span>**15.4.15. TIM1 capture/compare register 2 (TIM1\_CCR2)**
#### **Address offset:**0x38
#### **Reset value:**0x0000 0000
| 31 | 30 | 29 | 28 | 27 | 26 | 25 | 24 | 23 | 22 | 21 | 20 | 19 | 18 | 17 | 16 |
|------------|-----|-----|-----|-----|-----|-----|-----|-----|-----|-----|-----|-----|-----|-----|-----|
| Res | Res | Res | Res | Res | Res | Res | Res | Res | Res | Res | Res | Res | Res | Res | Res |
| - | - | - | - | - | - | - | - | - | - | - | - | - | - | - | - |
| 15 | 14 | 13 | 12 | 11 | 10 | 9 | 8 | 7 | 6 | 5 | 4 | 3 | 2 | 1 | 0 |
| CCR2[15:0] | | | | | | | | | | | | | | | |
| | RW | | | | | | | | | | | | | | |
#### **Bit Name R/W Reset Value Function** 31:16 Reserved Reserved, must be kept at reset value. 15:0 CCR2[15:0] RW 0 Capture/Compare 2 value If channel CC2 is configured as output: CCR2 is the value to be loaded in the actual capture/compare 2 register (preload value). It is loaded permanently if the preload feature is not selected in the TIM1\_CCMR2 register (bit OC2PE). Else the preload value is copied in the active capture/compare 2 register when an update event occurs. The active capture/compare register contains the value to be compared to the counter TIM1\_CNT and signalled on OC2 output. If channel CC2 is configured as input: CCR2 is the counter value transferred by the last input capture 2 event (IC2).
## <span id="page-199-2"></span>**15.4.16. TIM1 capture/compare register 3 (TIM1\_CCR3)**
**Address offset:**0x3C
| 31 | 30 | 29 | 28 | 27 | 26 | 25 | 24 | 23 | 22 | 21 | 20 | 19 | 18 | 17 | 16 |
|------------|-----|-----|-----|-----|-----|-----|-----|-----|-----|-----|-----|-----|-----|-----|-----|
| Res | Res | Res | Res | Res | Res | Res | Res | Res | Res | Res | Res | Res | Res | Res | Res |
| - | - | - | - | - | - | - | - | - | - | - | - | - | - | - | - |
| 15 | 14 | 13 | 12 | 11 | 10 | 9 | 8 | 7 | 6 | 5 | 4 | 3 | 2 | 1 | 0 |
| CCR3[15:0] | | | | | | | | | | | | | | | |
| | | | | | | | | | | | | | | | |
#### RW
| Bit | Name | R/W | Reset Value | Function |
|-------|------------|-----|-------------|-------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------|
| 31:16 | Reserved | | | Reserved, must be kept at reset value. |
| 15:0 | CCR3[15:0] | RW | 0 | Capture/Compare value<br>If channel CC3 is configured as output:<br>CCR3 is the value to be loaded in the actual capture/com<br>pare 3 register (preload value).<br>It is loaded permanently if the preload feature is not se<br>lected in the TIM1_CCMR3 register (bit OC3PE). Else the<br>preload value is copied in the active capture/compare 3 reg<br>ister when an update event occurs.<br>The active capture/compare register contains the value to<br>be compared to the counter TIM1_CNT and signalled on<br>OC3 output.<br>If channel CC3 is configured as input:<br>CCR3 is the counter value transferred by the last input cap<br>ture 3 event (IC3). |
## <span id="page-200-0"></span>**15.4.17. TIM1 capture/compare register 4 (TIM1\_CCR4)**
#### **Address offset:**0x40
**Reset value:**0x0000 0000
| 31 | 30 | 29 | 28 | 27 | 26 | 25 | 24 | 23 | 22 | 21 | 20 | 19 | 18 | 17 | 16 |
|------------|-----|-----|-----|-----|-----|-----|-----|-----|-----|-----|-----|-----|-----|-----|-----|
| Res | Res | Res | Res | Res | Res | Res | Res | Res | Res | Res | Res | Res | Res | Res | Res |
| - | - | - | - | - | - | - | - | - | - | - | - | - | - | - | - |
| 15 | 14 | 13 | 12 | 11 | 10 | 9 | 8 | 7 | 6 | 5 | 4 | 3 | 2 | 1 | 0 |
| CCR4[15:0] | | | | | | | | | | | | | | | |
| | | | | | | | | | | | | | | | |
#### RW
| Bit | Name | R/W | Reset Value | Function |
|-------|------------|-----|-------------|-------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------|
| 31:16 | Reserved | | | Reserved, must be kept at reset value. |
| 15:0 | CCR4[15:0] | RW | 0 | Capture/Compare value<br>If channel CC4 is configured as output:<br>CCR4 is the value to be loaded in the actual capture/com<br>pare 4 register (preload value).<br>It is loaded permanently if the preload feature is not se<br>lected in the TIM1_CCMR4 register (bit OC4PE). Else the<br>preload value is copied in the active capture/compare 4 reg<br>ister when an update event occurs.<br>The active capture/compare register contains the value to<br>be compared to the counter TIM1_CNT and signalled on<br>OC4 output.<br>If channel CC4 is configured as input:<br>CCR4 is the counter value transferred by the last input cap<br>ture 4 event (IC4). |
## <span id="page-200-1"></span>**15.4.18. TIM1 break and dead-time register (TIM1\_BDTR)**
#### **Address offset:**0x44
| 31 | 30 | 29 | 28 | 27 | 26 | 25 | 24 | 23 | 22 | 21 | 20 | 19 | 18 | 17 | 16 | | | |
|-----|-----|-----|-----|------|------|-----------|-----|-----|-----|-----|-----|----------|-----|-----|-----|--|--|--|
| Res | Res | Res | Res | Res | Res | Res | Res | Res | Res | Res | Res | Res | Res | Res | Res | | | |
| - | - | - | - | - | - | - | - | - | - | - | - | - | - | - | - | | | |
| 15 | 14 | 13 | 12 | 11 | 10 | 9 | 8 | 7 | 6 | 5 | 4 | 3 | 2 | 1 | 0 | | | |
| | | | | | | LOCK[1:0] | | | | | | DTG[7:0] | | | | | | |
| MOE | AOE | BKP | BKE | OSSR | OSSI | | | | | | | | | | | | | |
| Bit | Name | R/W | Reset Value | Function |
|-------|-----------|-----|-------------|-----------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------|
| 31:16 | Reserved | RW | 0 | Reserved, must be kept at reset value. |
| 15 | MOE | RW | 0 | Main output enable<br>This bit is cleared asynchronously by hardware as soon as<br>the break input is active. It is set by software or automati<br>cally depending on the AOE bit. It is acting only on the chan<br>nels which are configured in output.<br>0: OC and OCN outputs are disabled or forced to idle state.<br>1: OC and OCN outputs are enabled if their respective en<br>able bits are set (CCxE, CCxNE in TIM1_CCER register). |
| 14 | AOE | RW | 0 | Automatic output enable<br>0: MOE can be set only by software<br>1: MOE can be set by software or automatically at the next<br>update event (if the break input is not be active)<br>Note: This bit cannot be modified as long as LOCK level 1<br>has been programmed (LOCK bits in TIM1_BDTR register). |
| 13 | BKP | RW | 0 | Break polarity<br>0: Break input BRK is active low<br>1: Break input BRK is active high<br>Note: This bit can not be modified as long as LOCK level 1<br>has been programmed (LOCK bits in TIM1_BDTR register). |
| 12 | BKE | RW | 0 | Break enable<br>0: Break inputs (BRK and BRK_ACTH) disabled<br>1, Break inputs (BRK and BRK_ACTH) enabled<br>Note: This bit cannot be modified when LOCK level 1 has<br>been programmed (LOCK bits in TIM1_BDTR register). |
| 11 | OSSR | RW | 0 | Off-state selection for Run mode<br>This bit is used when MOE = 1 on channels having a com<br>plementary output which are configured as outputs. OSSR<br>is not implemented if no complementary output is imple<br>mented in the timer.<br>Refer to the detailed decreption of OC/OCN enable(cap<br>ture/compare enable register(TIM1_CCER)).<br>0: When inactive, OC/OCN outputs are disabled (OC/OCN<br>enable output signal = 0).<br>1: When inactive, OC/OCN outputs are enabled with their<br>inactive level as soon as CCxE = 1 or CCxNE = 1. Then,<br>OC/OCN enable output signal = 1<br>Note: This bit can not be modified as soon as the LOCK<br>level 2 has been programmed (LOCK bits in TIM1_BDTR<br>register). |
| 10 | OSSI | RW | 0 | Off-state selection for Idle mode<br>This bit is used when MOE = 0 on channels configured as<br>outputs.<br>0: When inactive, OC/OCN outputs are disabled (OC/OCN<br>enable output signal = 0).<br>1: When inactive, OC/OCN outputs are forced first with their<br>idle level as soon as CCxE = 1 or CCxNE = 1. OC/OCN<br>enable output signal = 1)<br>Note: This bit can not be modified as soon as the LOCK<br>level 2 has been programmed (LOCK bits in TIM1_BDTR<br>register). |
| 9:8 | LOCK[1:0] | RW | 00 | Lock configuration<br>These bits offer a write protection against software errors.<br>00: LOCK OFF - No bit is write protected.<br>01: LOCK Level 1,DTG/BKE/BKP/AOE bits in TIM1_BDTR<br>register and OISx/OISxN bits in TIM1_CR2 register and can<br>no longer be written.<br>10: LOCK Level 2,LOCK Level 1 + CC Polarity bits<br>(CCxP/CCxNP bits in TIM1_CCER register, as long as the<br>related channel is configured in output through the CCxS<br>bits) as well as OSSR and OSSI bits can no longer be writ<br>ten.<br>11: LOCK Level 3, LOCK Level 2 + CC Control bits (OCxM<br>and OCxPE bits in TIM1_CCMRx registers, as long as the<br>related channel is configured in output through the CCxS<br>bits) can no longer be written. |
| Bit | Name | R/W | Reset Value | Function |
|-----|----------|-----|-------------|------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------|
| | | | | Note: The LOCK bits can be written only once after the re<br>set. Once the TIM1_BDTR register has been written, their<br>content is frozen until the next reset. |
| 7:0 | DTG[7:0] | RW | 0000 0000 | Dead-time generator setup<br>This bit-field defines the duration of the dead-time inserted<br>between the complementary outputs. DT correspond to this<br>duration.<br>DTG[7:5] = 0xx = > DT = DTG[7:0]x tdtg with tdtg = tDTS.<br>DTG[7:5] = 10x = > DT = (64+DTG[5:0])xtdtg with Tdtg =<br>2xtDTS.<br>DTG[7:5] = 110 = > DT = (32+DTG[4:0])xtdtg with Tdtg =<br>8xtDTS.<br>DTG[7:5] = 111 = > DT = (32+DTG[4:0])xtdtg with Tdtg =<br>16xtDTS.<br>Example if TDTS = 125 ns (8 MHz), dead-time possible val<br>ues are:<br>0 to 15875 ns by 125 ns steps,<br>16 us to 31750 ns by 250 ns steps,<br>32 us to 63 us by 1 us steps,<br>64 us to 126 us by 2 us steps<br>Note: This bit-field can not be modified as long as LOCK<br>level 1, 2 or 3 has been programmed (LOCK bits in<br>TIM1_BDTR register). |
### <span id="page-202-0"></span>**15.4.19. TIM1 register mapping**
| O<br>ff<br>s<br>et | Regis<br>ter | 31 | 30 | 29 | 28 | 27 | 26 | 25 | 24 | 23 | 22 | 21 | 20 | 19 | 18 | 17 | 16 | 15 | 14 | 13 | 12 | 11 | 10 | 9 | 8 | 7 | 6 | 5 | 4 | 3 | 2 | 1 | 0 |
|--------------------|-------------------------------------------------------|------|------|------|------|------|------|------|------|-------|-------|-------|-------|-------|-------|-------|-------|-------|-----------|---------------|-------|--------------|----------|-------------------|------|-------|-----------|---------------|-------|--------------|-------|-------------------|------|
| 0<br>x<br>0 | TIM1_<br>CR1 | Res. | Res. | Res. | Res. | Res. | Res. | Res. | Res. | Res. | Res. | Res. | Res. | Res. | Res. | Res. | Res. | Res. | Res. | Res. | Res. | Res. | Res. | CKD[1:0] | | ARPE | CMS[1:0] | | DIR | OPM | URS | UDIS | CEN |
| 0 | Reset<br>value | | | | | | | | | | | | | | | | | | | | | | | 0 | 0 | 0 | 0 | 0 | 0 | 0 | 0 | 0 | 0 |
| 0<br>x<br>0 | TIM1_<br>CR2 | Res. | Res. | Res. | Res. | Res. | Res. | Res. | Res. | Res. | Res. | Res. | Res. | Res. | Res. | Res. | Res. | Res. | OIS4 | OIS3N | OIS3 | OIS2N | OIS2 | OIS1N | OIS1 | TI1S | | MMS [2:0] | | Res. | CCUS | Res. | CCPC |
| 4 | Reset<br>value | | | | | | | | | | | | | | | | | | 0 | 0 | 0 | 0 | 0 | 0 | 0 | 0 | 0 | 0 | 0 | | 0 | | 0 |
| 0<br>x<br>0 | TIM1_<br>SMCR | Res. | Res. | Res. | Res. | Res. | Res. | Res. | Res. | Res. | Res. | Res. | Res. | Res. | Res. | Res. | Res. | ETP | ECE | ETPS[1:0] | | | ETF[3:0] | MSM<br>TS[2:0] | | | | | | OCCS | | SMS [2:0] | |
| 8 | Reset<br>value | | | | | | | | | | | | | | | | | 0 | 0 | 0 | 0 | 0 | 0 | 0 | 0 | 0 | 0 | 0 | 0 | 0 | 0 | 0 | 0 |
| 0<br>x<br>0 | TIM1_<br>DIER | Res. | Res. | Res. | Res. | Res. | Res. | Res. | Res. | Res. | Res. | Res. | Res. | Res. | Res. | Res. | Res. | Res. | Res. | Res. | Res. | Res. | Res. | Res. | Res. | BIE | TIE | COMIE | CC4IE | CC3IE | CC2IE | CC1IE | UIE |
| C | Reset<br>value | | | | | | | | | | | | | | | | | | | | | | | | | 0 | 0 | 0 | 0 | 0 | 0 | 0 | 0 |
| 0<br>x<br>1 | TIM1_<br>SR | Res. | Res. | Res. | Res. | Res. | Res. | Res. | Res. | IC4IF | IC3IF | IC2IF | IC1IF | IC4IR | IC3IR | IC2IR | IC1IR | Res. | Res. | Res. | CC4OF | CC3OF | CC2OF | CC1OF | Res. | BIF | TIF | COMIF | CC4IF | CC3IF | CC2IF | CC1IF | UIF |
| 0 | Reset<br>value | | | | | | | | | 0 | 0 | 0 | 0 | 0 | 0 | 0 | 0 | | | | 0 | 0 | 0 | 0 | | 0 | 0 | 0 | 0 | 0 | 0 | 0 | 0 |
| 0<br>x<br>1 | TIM1_<br>EGR | Res. | Res. | Res. | Res. | Res. | Res. | Res. | Res. | Res. | Res. | Res. | Res. | Res. | Res. | Res. | Res. | Res. | Res. | Res. | Res. | Res. | Res. | Res. | Res. | BG | TG | COMG | CC4G | CC3G | CC2G | CC1G | UG |
| 4 | Reset<br>value | | | | | | | | | | | | | | | | | | | | | | | | | 0 | 0 | 0 | 0 | 0 | 0 | 0 | 0 |
| 0<br>x<br>1<br>8 | TIM1_<br>CCMR<br>1(out<br>put<br>com<br>pare<br>mode) | Res. | Res. | Res. | Res. | Res. | Res. | Res. | Res. | Res. | Res. | Res. | Res. | Res. | Res. | Res. | Res. | OC2CE | | OC2M<br>[2:0] | | OC2PE | CO2FE | CC2<br>S<br>[1:0] | | OC1CE | | OC1M<br>[2:0] | | OC1PE | OC1FE | CC1<br>S<br>[1:0] | |
| | Reset<br>value | | | | | | | | | | | | | | | | | 0 | 0 | 0 | 0 | 0 | 0 | 0 | 0 | 0 | 0 | 0 | 0 | 0 | 0 | 0 | 0 |
| 0<br>x<br>1<br>8 | TIM1_<br>CCMR<br>1(In<br>put<br>Cap<br>ture<br>mode) | Res. | Res. | Res. | Res. | Res. | Res. | Res. | Res. | Res. | Res. | Res. | Res. | Res. | Res. | Res. | Res. | | IC2F[3:0] | | | IC2PSC [1:0] | | CC2<br>S<br>[1:0] | | | IC1F[3:0] | | | IC1PSC [1:0] | | CC1<br>S<br>[1:0] | |
| O<br>ff<br>s<br>et | Regis<br>ter | 31 | 30 | 29 | 28 | 27 | 26 | 25 | 24 | 23 | 22 | 21 | 20 | 19 | 18 | 17 | 16 | 15 | 14 | 13 | 12 | 11 | 10 | 9 | 8 | 7 | 6 | 5 | 4 | 3 | 2 | 1 | 0 |
|--------------------|-------------------------------------------------------|------|------|------|------|------|------|------|------|------|------|------|------|------|------|------|------|-------|--------------------------------------------------------------------|---------------|-----------|--------------|-------|--------------------------------|------|------------|-------|---------------|----------|--------------|-------|-------------------|-------------------|
| | Reset<br>value | | | | | | | | | | | | | | | | | 0 | 0 | 0 | 0 | 0 | 0 | 0 | 0 | 0 | 0 | 0 | 0 | 0 | 0 | 0 | 0 |
| 0<br>x<br>1<br>C | TIM1_<br>CCMR<br>2(out<br>put<br>cap<br>ture<br>mode) | Res. | Res. | Res. | Res. | Res. | Res. | Res. | Res. | Res. | Res. | Res. | Res. | Res. | Res. | Res. | Res. | OC4CE | | OC4M<br>[2:0] | | OC4PE | CO4FE | CC4<br>S<br>[1:0] | | OC3CE | | OC3M<br>[2:0] | | OC3PE | OC3FE | CC3<br>S<br>[1:0] | |
| | Reset<br>value | | | | | | | | | | | | | | | | | 0 | 0 | 0 | 0 | 0 | 0 | 0 | 0 | 0 | 0 | 0 | 0 | 0 | 0 | 0 | 0 |
| 0<br>x<br>1<br>C | TIM1_<br>CCMR<br>2(In<br>put<br>Cap<br>ture<br>mode) | Res. | Res. | Res. | Res. | Res. | Res. | Res. | Res. | Res. | Res. | Res. | Res. | Res. | Res. | Res. | Res. | | IC4F[3:0] | | | IC4PSC [1:0] | | CC4<br>S<br>IC3F[3:0]<br>[1:0] | | | | | | IC3PSC [1:0] | | | CC3<br>S<br>[1:0] |
| | Reset<br>value | | | | | | | | | | | | | | | | | 0 | 0 | 0 | 0 | 0 | 0 | 0 | 0 | 0 | 0 | 0 | 0 | 0 | 0 | 0 | 0 |
| 0<br>x | TIM1_<br>CCER | Res. | Res. | Res. | Res. | Res. | Res. | Res. | Res. | Res. | Res. | Res. | Res. | Res. | Res. | Res. | Res. | Res. | Res. | CC4P | CC4E | CC3NP | CC3NE | CC3P | CC3E | CC2NP | CC2NE | CC2P | CC2E | CC1NP | CC1NE | CC1P | CC1E |
| 2<br>0 | Reset<br>value | | | | | | | | | | | | | | | | | | | | | | | | | 0 | 0 | 0 | 0 | 0 | 0 | 0 | 0 |
| 0<br>x | TIM1_<br>CNT | Res. | Res. | Res. | Res. | Res. | Res. | Res. | Res. | Res. | Res. | Res. | Res. | Res. | Res. | Res. | Res. | | | CNT[15:0] | | | | | | | | | | | | | |
| 2<br>4 | Reset | | | | | | | | | | | | | | | | | 0 | 0 | 0 | 0 | 0 | 0 | 0 | 0 | 0 | 0 | 0 | 0 | 0 | 0 | 0 | 0 |
| 0 | value<br>TIM1_ | Res. | Res. | Res. | Res. | Res. | Res. | Res. | Res. | Res. | Res. | Res. | Res. | Res. | Res. | Res. | Res. | | | | | PSC[15:0] | | | | | | | | | | | |
| x<br>2<br>8 | PSC<br>Reset | | | | | | | | | | | | | | | | | 0 | 0 | 0 | 0 | 0 | 0 | 0 | 0 | 0 | 0 | 0 | 0 | 0 | 0 | 0 | 0 |
| 0 | value<br>TIM1_<br>ARR | Res. | Res. | Res. | Res. | Res. | Res. | Res. | Res. | Res. | Res. | Res. | Res. | Res. | Res. | Res. | Res. | | | | ARR[15:0] | | | | | | | | | | | | |
| x<br>2<br>C | Reset<br>value | | | | | | | | | | | | | | | | | 1 | 1 | 1 | 1 | 1 | 1 | 1 | 1 | 1 | 1 | 1 | 1 | 1 | 1 | 1 | 1 |
| 0<br>x | TIM1_<br>RCR | Res. | Res. | Res. | Res. | Res. | Res. | Res. | Res. | Res. | Res. | Res. | Res. | Res. | Res. | Res. | Res. | Res. | Res. | Res. | Res. | Res. | Res. | Res. | Res. | | | | REP[7:0] | | | | |
| 3<br>0 | Reset<br>value | | | | | | | | | | | | | | | | | | | | | | | | | 0 | 0 | 0 | 0 | 0 | 0 | 0 | 0 |
| 0 | TIM1_ | Res. | Res. | Res. | Res. | Res. | Res. | Res. | Res. | Res. | Res. | Res. | Res. | Res. | Res. | Res. | Res. | | | | | | | | | CCR1[15:0] | | | | | | | |
| x<br>3<br>4 | CCR1<br>Reset | | | | | | | | | | | | | | | | | 0 | 0 | 0 | 0 | 0 | 0 | 0 | 0 | 0 | 0 | 0 | 0 | 0 | 0 | 0 | 0 |
| 0 | value<br>TIM1_ | Res. | Res. | Res. | Res. | Res. | Res. | Res. | Res. | Res. | Res. | Res. | Res. | Res. | Res. | Res. | Res. | | | | | | | | | CCR2[15:0] | | | | | | | |
| x<br>3<br>8 | CCR2<br>Reset | | | | | | | | | | | | | | | | | 0 | 0 | 0 | 0 | 0 | 0 | 0 | 0 | 0 | 0 | 0 | 0 | 0 | 0 | 0 | 0 |
| 0 | value<br>TIM1_ | Res. | Res. | Res. | Res. | Res. | Res. | Res. | Res. | Res. | Res. | Res. | Res. | Res. | Res. | Res. | Res. | | CCR3[15:0] | | | | | | | | | | | | | | |
| x<br>3 | CCR3<br>Reset | | | | | | | | | | | | | | | | | 0 | 0<br>0<br>0<br>0<br>0<br>0<br>0<br>0<br>0<br>0<br>0<br>0<br>0<br>0 | | | | | | 0 | | | | | | | | |
| C<br>0 | value<br>TIM1_ | Res. | Res. | Res. | Res. | Res. | Res. | Res. | Res. | Res. | Res. | Res. | Res. | Res. | Res. | Res. | Res. | | CCR4[15:0] | | | | | | | | | | | | | | |
| x<br>4 | CCR4<br>Reset | | | | | | | | | | | | | | | | | 0 | 0 | 0 | 0 | 0 | 0 | 0 | 0 | 0 | 0 | 0 | 0 | 0 | 0 | 0 | 0 |
| 0 | value<br>TIM1_ | | | | | | | | | | | | | | | | | | | | | | | LOC | | | | | | | | | |
| 0<br>x<br>4 | BDTR | Res. | Res. | Res. | Res. | Res. | Res. | Res. | Res. | Res. | Res. | Res. | Res. | Res. | Res. | Res. | Res. | MOE | AOE | BKP | BKE | OSSR | OSSI | K<br>[1:0] | | | | | DTG[7:0] | | | | |
| 4 | Reset<br>value | | | | | | | | | | | | | | | | | 0 | 0 | 0 | 0 | 0 | 0 | 0 | 0 | 0 | 0 | 0 | 0 | 0 | 0 | 0 | 0 |
# <span id="page-204-0"></span>**16. General purpose timer (TIM14)**
## <span id="page-204-1"></span>**16.1. TIM14introduction**
The general-purpose timer TIM14 consist of a 16-bit auto-reload counter driven by a programmable prescaler.
It may be used for a variety of purposes, including measuring the pulse lengths of input signals (input capture) or generating output waveforms (output compare and PWM).
Pulse lengths and waveform periods can be modulated from a few microseconds to several milliseconds using the timer prescaler and the RCC clock controller prescalers.
## <span id="page-204-2"></span>**16.2. TIM14 main features**
- 16-bit up auto-reload counter
- 16-bit programmable prescaler used to divide the counter clock frequency by any factor between 1 and 65535
- One independent channel for:
- Input capture
- Output capture
- PWM generation(Edge-aligned modes)
- Interrupt generation on the following events:
- Update:counter overflow,counter initialization (by software)
- Input capture
- Output capture
![](_page_205_Figure_1.jpeg)
#### Figure 16 1 TIM14 Diagram
## <span id="page-205-0"></span>**16.3. TIM14 functional description**
#### <span id="page-205-1"></span>**16.3.1. Time-base unit**
The main block of the programmable general purpose timer is a 16-bit upcounter with its related auto-reload register. The counter clock can be divided by a prescaler.
The counter, the auto-re.load register and the prescaler register can be written or read by software. This is true even when the counter is running.The time-base unit includes:
- Counter register(TIM14\_CNT)
- Prescaler register(TIM14\_PSC)
- Auto-reload register(TIM14\_ARR)
The auto-reload register is preloaded. Writing to or reading from the auto-reload register accesses the preload register. The content of the preload register are transferred into the shadow register permanently or at each update event (UEV), depending on the auto-reload preload enable bit (ARPE) in TIM14\_CR1 register. The update event is sent when the counter reaches the overflow and if the UDIS bit equals 0 in the TIM14\_CR1 register. It can also be generated by software. The counter is clocked by the prescaler output CK\_CNT, which is enabled only when the counter enable bit (CEN) in TIM14\_CR1 register is set.
Note that the counter starts counting 1 clock cycle after setting the CEN bit in the TIM14\_CR1 register.
#### **Prescaler description**:
The prescaler can divide the counter clock frequency by any factor between 1 and 65536. It is based on a 16-bit counter controlled through a 16-bit register (in the TIM14\_PSC register). It can be changed on the fly as this control register is buffered. The new prescaler ratio is taken into account at the next update event.
The following figures give some examples of the counter behavior when the prescaler ratio is changedy:
![](_page_206_Figure_4.jpeg)
Figure 16-1 Counter timing diagram with prescaler division change from 1 to 2
![](_page_206_Figure_6.jpeg)
图 16-2 Counter timing diagram with prescaler division change from 1 to 4
#### **Upcounting mode**
The counter counts from 0 to the auto-reload value(TIM14\_ARR register value), then restarts from 0 and generates a counter overflow event.
Each count overflow generates an update event. An update event can also be generated by setting the UG bit in the TIM\_EGR register(by software or by using the slave mode controller).
The UEV event can be disabled by software by setting the UDIS bit in TIM14\_CR1 register. This is to avoid updating the shadow registers while writing new values in the preload registers. Then no update event occurs until the UDIS bit has been written to 0. However, the counter restarts from 0, as well as the counter of the prescaler (but the prescale rate does not change). In addition, if the URS bit (update request selection) in TIM14\_CR1 register is set, setting the UG bit generates an update event UEV but without setting the UIF flag (thus no interrupt request is sent). This is to avoid generating both update and capture interrupts when clearing the counter on the capture event.
When an update event occurs, all the registers are updated and the update flag (UIF bit in TIM14\_SR register) is set (depending on the URS bit):
- The auto-reload shadow register is updated with the preload value (TIM14\_ARR).
- The buffer of the prescaler is reloaded with the preload value (content of the TIM14\_PSC register).
The following figures show some examples of the counter behavior for different clock frequencies when TIM14\_ARR = 0x36
| CK_PSC | |
|----------------------------|---------------------------------------------------------------------------------------------|
| CNT_EN | |
| Timer clock = CK_CNT | |
| Counter register | 3 1<br>3 2<br>3 3<br>3 5<br>3 6<br>0 0<br>0 1<br>0 2<br>0 4<br>0 5<br>0 6 0 7<br>3 4<br>0 3 |
| Counter overflow | |
| Update event(UEV) | |
| Update interrupt flag(UIF) | |
| | |
Figure 16-3 Counter timing diagram,internal clock divided by 1
| CK_PSC | |
|----------------------------|------------------------------------------------------|
| CNT_EN | |
| Timer clock = CK_CNT | |
| Counter register | 0035<br>0036<br>0000<br>0001<br>0002<br>0003<br>0034 |
| Counter overflow | |
| Update event(UEV) | |
| Update interrupt flag(UIF) | |
Figure 16-4 Counter timing diagram,internal clock divided by 2
| CK_PSC | |
|----------------------------|------------------------------|
| CNT_EN | |
| Timer clock = CK_CNT | |
| Counter register | 0035<br>0036<br>0000<br>0001 |
| Counter overflow | |
| Update event(UEV) | |
| Update interrupt flag(UIF) | |
Figure 16-5 Counter timing diagram,internal clock divided by 4
| CK_PSC | | |
|----------------------------|------------------|--------|
| CNT_EN | | |
| Timer clock = CK_CNT | | |
| Counter register | 1<br>F<br>2<br>0 | 0<br>0 |
| Counter overflow | | |
| Update event(UEV) | | |
| Update interrupt flag(UIF) | | |
Figure 16-6 Counter timing diagram,internal clock divided by N
| CK_PSC | | | |
|------------------------------|---------------------------------|-----------------------------------------------|---------|
| CNT_EN | | | |
| Timer clock = CK_CNT | | | |
| Counter register | 3 1<br>3 2<br>3 3<br>3 5<br>3 4 | 3 6<br>0 0<br>0 1<br>0 2<br>0 4<br>0 5<br>0 3 | 0 6 0 7 |
| Counter overflow | | | |
| Update event(UEV) | | | |
| Update interrupt flag(UIF) | | | |
| Auto-reload preload register | FF | 3 6 | |
| | Write a new value in TIMx_ARR | | |
Figure 16-7 Counter timing diagram,update event when ARPE=0 (TIMx\_ARR not preload)
![](_page_209_Figure_1.jpeg)
Figure 16-8 Counter timing diagram,update event when ARPE=1 (TIMx\_ARR preloaded)
### <span id="page-209-0"></span>**16.3.2. Clock sources**
The clock for the counter is provided by the internal clock (CK\_INT).The CEN BIT of the TIMx\_CR1 register and the UG bit of th TIM 14\_EGR register are the actual control bits (except that the UG bit is automatically cleared) and can only be changed by software. Once the CEN bit is set to 1, the internal clock supplies the clock to the divider.
| CK_PSC | |
|---------------------------------|---------------------------------------------------------------------------------------------|
| CEN=CNT_EN | |
| U G | |
| CNT_INIT | |
| Counter clock = CK_CNT = CK_PSC | |
| Counter register | 3 1<br>3 2<br>3 3<br>3 5<br>3 6<br>0 0<br>0 1<br>0 2<br>0 4<br>0 5<br>0 6 0 7<br>3 4<br>0 3 |
| | |
Figure 16-9 Control circuit in normal mode,internal clock divided by 1
## <span id="page-209-1"></span>**16.3.3. Capture/compare channels**
Each Capture/Compare channel is built around a capture/compare register (including a shadow register), a input stage for capture (with digital filter, multiplexing and prescaler) and an output stage (with comparator and output control).
![](_page_210_Figure_1.jpeg)
Figure 16-10 TIM14 Capture/compare channel(example: channel 1 input stage)
The input stage samples the corresponding TIx input to generate a filtered signal TIxF. Then, an edge detector with polarity selection generates a signal (TIxFPx) which can be used as trigger input by the slave mode controller or as the capture command. It is prescaled before the capture register (ICxPS).
The output stage generates an intermediate waveform which is then used for reference (active high). The polarity acts at the end of the chain.
The capture/compare block is made of one preload register and one shadow register. Write and read always access the preload register.
In capture mode, captures are actually done in the shadow register, which is copied into the preload register.
In compare mode, the content of the preload register is copied into the shadow register which is compared to the counter.
#### <span id="page-210-0"></span>**16.3.4. Input capture mode**
In input capture mode, the Capture/Compare Registers(TIM14\_CCRx) are used to latch the value of the counter after a transition detected by the corresponding ICx signal. When a capture occurs, the corresponding CCxIF flag (TIM14\_SR register) is set. If a capture occurs while the CCxIF flag was already hign, the the over-capure flag CCxOF(TIMx\_SR register) is set. CCxIF can be cleared by software by writing it to 0 or by reading the capure data stored in the register. CCxOF is cleared when it is written with 0.
The following example shows how to capture the counter value in TIM14\_CCR1 when TI1 input rises. As the following two procedure show:
- Select the active input: TIM14\_CCR1 must be linked to the TI1 input, so write the CC1S= 01 in the TIM14\_CCMR1 register. As soon as CC1S becomes different from 00, the channel is configured in input and the TIM14\_CCR1 register becomes read-only.
- Program the appropriate input filter duration in relation with the signal connected to the timer (when the input is one of the TIx (ICxF bits in the TIM14\_CCMRx register). Suppose that, when toggling, the input signal is not stable during at must 5 internal clock cycles. We must program a filter duration longer than these 5 clock cycles. We can validate a transition on TI1 when 8 consecutive samples with the new level have been detected (sampled at fDTS frequency). Then write IC1F= 0011 in the TIM14\_CCMR1 register.
- Select the edge of the active transition on the TI1 channel by writing the CC1P=0(rising) (and CC1NP=0 )in the TIMx\_CCER register.
- Program the input prescaler. In our example, we wish the capture to be performed at each valid transition, so the prescaler is disabled (write IC1PS=00 in the TIMx\_CCMR1 register).
- Enable capture from the counter into the capture register by setting the CC1E bit in the TIMx\_CCER register.
- If needed, enable the related interrupt request by setting the CC1IE bit in the TIMx\_DIER register.
When an input capture occurs:
- The TIM14\_CCR1 register gets the value of the counter on the active transition.
- CC1IF flag is set (interrupt flag). CC1OF is also set if at least two consecutive captures occurred whereas the flag was not cleared.
- An interrupt is generated depending on the CC1IE bit.
In order to handle the overcapture, it is recommended to read the data before the overcapture flag. This is to avoid missing an overcapture which could happen after reading the flag and before reading the data.
Note: IC interrupt requests can be generated by software by setting the corresponding CCxG bit in the TIMx\_EGR register.
#### <span id="page-211-0"></span>**16.3.5. Force ouput mode**
In this mode (CCxS bits=00 in the TIM14\_CCMRx register), each output compare signal (OCxREF and the corresponding OCx) can be forced to active or inactive level directly by software, independently of any comparison between the output compare register and the counter. To force an output compare signal (OCxREF/OCx) to its active level, one just needs to write OCxM bits=101, in the corresponding TIM14\_CCMRx register. Thus OCxREF is forced high(OCxREF is always active high) and OCx get opposite value to CCxP polarity bit. For instance, CCxP = 0 (OCx active high) = > OCx is forced to high level. OCxREF signal can be forced low by writing the OCxM bits to 100 in the TIM14\_CCMRx register.
The comparison between the TIM14\_CCRx shadow register and the counter is still performed and allows the flag to be set. This is described in the Output Compare Mode section.
## <span id="page-212-0"></span>**16.3.6. Output compare mode**
This function is used to control an output waveform or indicating when a period of time has elapsed.
When a match is found between the capture/compare register and the counter, the output compare function:
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