gcc-x86_64-use-tls-gs.diff

diff -urN gcc-4.1.2-orig/gcc/config/i386/i386.c gcc-4.1.2/gcc/config/i386/i386.c
--- gcc-4.1.2-orig/gcc/config/i386/i386.c	2006-11-17 07:01:22.000000000 +0000
+++ gcc-4.1.2/gcc/config/i386/i386.c	2007-09-05 13:16:36.950573962 +0100
@@ -5313,7 +5313,7 @@
 	      if (XINT (op, 1) == UNSPEC_TP
 	          && TARGET_TLS_DIRECT_SEG_REFS
 	          && seg == SEG_DEFAULT)
-		seg = TARGET_64BIT ? SEG_FS : SEG_GS;
+		seg = (TARGET_64BIT && !TARGET_TLS_USE_GS) ? SEG_FS : SEG_GS;
 	      else
 		return 0;
 	      break;
diff -urN gcc-4.1.2-orig/gcc/config/i386/i386.h gcc-4.1.2/gcc/config/i386/i386.h
--- gcc-4.1.2-orig/gcc/config/i386/i386.h	2006-12-16 19:24:56.000000000 +0000
+++ gcc-4.1.2/gcc/config/i386/i386.h	2007-09-05 13:06:49.933121746 +0100
@@ -237,6 +237,9 @@
 #ifndef TARGET_TLS_DIRECT_SEG_REFS_DEFAULT
 #define TARGET_TLS_DIRECT_SEG_REFS_DEFAULT 0
 #endif
+#ifndef TARGET_TLS_USE_GS_DEFAULT
+#define TARGET_TLS_USE_GS_DEFAULT 0
+#endif
 
 /* Once GDB has been enhanced to deal with functions without frame
    pointers, we can change this to allow for elimination of
diff -urN gcc-4.1.2-orig/gcc/config/i386/i386.md gcc-4.1.2/gcc/config/i386/i386.md
--- gcc-4.1.2-orig/gcc/config/i386/i386.md	2006-09-15 18:42:40.000000000 +0100
+++ gcc-4.1.2/gcc/config/i386/i386.md	2007-09-05 20:08:14.237992162 +0100
@@ -14658,7 +14658,12 @@
   [(set (match_operand:DI 0 "register_operand" "=r")
 	(unspec:DI [(const_int 0)] UNSPEC_TP))]
   "TARGET_64BIT"
-  "mov{q}\t{%%fs:0, %0|%0, QWORD PTR %%fs:0}"
+  {
+	if (TARGET_TLS_USE_GS)
+		return "mov{q}\t{%%gs:0, %0|%0, QWORD PTR %%gs:0}";
+	else
+		return "mov{q}\t{%%fs:0, %0|%0, QWORD PTR %%fs:0}";
+  }
   [(set_attr "type" "imov")
    (set_attr "modrm" "0")
    (set_attr "length" "7")
@@ -14671,7 +14676,12 @@
 		 (match_operand:DI 1 "register_operand" "0")))
    (clobber (reg:CC FLAGS_REG))]
   "TARGET_64BIT"
-  "add{q}\t{%%fs:0, %0|%0, QWORD PTR %%fs:0}"
+  {
+	if (TARGET_TLS_USE_GS)
+		return "add{q}\t{%%gs:0, %0|%0, QWORD PTR %%gs:0}";
+	else
+		return "add{q}\t{%%fs:0, %0|%0, QWORD PTR %%fs:0}";
+  }
   [(set_attr "type" "alu")
    (set_attr "modrm" "0")
    (set_attr "length" "7")
@@ -20573,7 +20583,12 @@
    (set (match_scratch:DI 2 "=&r") (const_int 0))
    (clobber (reg:CC FLAGS_REG))]
   "TARGET_64BIT"
-  "mov{q}\t{%%fs:%P1, %2|%2, QWORD PTR %%fs:%P1}\;mov{q}\t{%2, %0|%0, %2}\;xor{l}\t%k2, %k2"
+  {
+	if (TARGET_TLS_USE_GS)
+		return "mov{q}\t{%%gs:%P1, %2|%2, QWORD PTR %%gs:%P1}\;mov{q}\t{%2, %0|%0, %2}\;xor{l}\t%k2, %k2";
+	else
+		return "mov{q}\t{%%fs:%P1, %2|%2, QWORD PTR %%fs:%P1}\;mov{q}\t{%2, %0|%0, %2}\;xor{l}\t%k2, %k2";
+  }
   [(set_attr "type" "multi")])
 
 (define_expand "stack_protect_test"
@@ -20641,7 +20656,12 @@
 		    UNSPEC_SP_TLS_TEST))
    (clobber (match_scratch:DI 3 "=r"))]
   "TARGET_64BIT"
-  "mov{q}\t{%1, %3|%3, %1}\;xor{q}\t{%%fs:%P2, %3|%3, QWORD PTR %%fs:%P2}"
+  {
+	if (TARGET_TLS_USE_GS)
+		return "mov{q}\t{%1, %3|%3, %1}\;xor{q}\t{%%gs:%P2, %3|%3, QWORD PTR %%gs:%P2}";
+	else
+		return "mov{q}\t{%1, %3|%3, %1}\;xor{q}\t{%%fs:%P2, %3|%3, QWORD PTR %%fs:%P2}";
+  }
   [(set_attr "type" "multi")])
 
 (include "sse.md")
diff -urN gcc-4.1.2-orig/gcc/config/i386/i386.opt gcc-4.1.2/gcc/config/i386/i386.opt
--- gcc-4.1.2-orig/gcc/config/i386/i386.opt	2006-05-17 19:38:58.000000000 +0100
+++ gcc-4.1.2/gcc/config/i386/i386.opt	2007-09-05 14:11:16.733478137 +0100
@@ -217,6 +217,10 @@
 Target Report Mask(TLS_DIRECT_SEG_REFS)
 Use direct references against %gs when accessing tls data
 
+mtls-gs
+Target RejectNegative Report Mask(TLS_USE_GS)
+Use the GS register for AMD64 TLS code
+
 mtune=
 Target RejectNegative Joined Var(ix86_tune_string)
 Schedule code for given CPU