Galaxy S10 Mainline DTS

exynos9820-beyond1lte.dts

// SPDX-License-Identifier: GPL-2.0 OR BSD-3-Clause

/dts-v1/;

#include "exynos9820.dtsi"
#include <dt-bindings/gpio/gpio.h>

/ {
	model = "Samsung Galaxy S10";
	compatible = "samsung,s10", "samsung,exynos9820";
	chassis-type = "handset";

	chosen {
		#address-cells = <2>;
		#size-cells = <1>;
		ranges;

		bootargs = "pmos.nosplash";

		stdout-path = "fb0";

		fb0: framebuffer@ca000000 {
			compatible = "simple-framebuffer";
			reg = <0x0 0xca000000 (1440 * 3040 * 4)>;
			width = <1440>;
			height = <3040>;
			stride = <(1440 * 4)>;
			format = "a8r8g8b8";
		};
	};

	reserved-memory {
		#address-cells = <2>;
		#size-cells = <1>;
		ranges;

		framebuffer_region@ca000000 {
			reg = <0x0 0xca000000 (1440 * 3040 * 4)>;
			no-map;
		};

	};

	memory@80000000 {
		device_type = "memory";
		reg = <0x0 0x80000000 0x80000000>;
	};
};

exynos9820.dtsi

// SPDX-License-Identifier: GPL-2.0
/*
 * Samsung Exynos 9810 SoC device tree source
 *
 * Copyright (c) 2024 Markuss Broks <markuss.broks@gmail.com>
 * Copyright (c) 2024 Maksym Holovach <nergzd@nergzd723.xyz>
 */

#include <dt-bindings/interrupt-controller/arm-gic.h>

/ {
	compatible = "samsung,exynos9820";
	#address-cells = <2>;
	#size-cells = <1>;

	interrupt-parent = <&gic>;

	cpus {
		#address-cells = <1>;
		#size-cells = <0>;

		cpu-map {
			cluster0 {
				core0 {
					cpu = <&cpu0>;
				};
			};
		};

		cpu0: cpu@0 {
			device_type = "cpu";
			compatible = "arm,cortex-a53";
			reg = <0x0>;
			enable-method = "psci";
		};
	};

	psci {
		compatible = "arm,psci";
		method = "smc";
		cpu_off = <0x84000002>;
		cpu_on = <0xc4000003>;
		cpu_suspend = <0xc4000001>;
	};

	timer {
		compatible = "arm,armv8-timer";
		/* Hypervisor Virtual Timer interrupt is not wired to GIC */
		interrupts = <GIC_PPI 13 (GIC_CPU_MASK_SIMPLE(8) | IRQ_TYPE_LEVEL_LOW)>,
			     <GIC_PPI 14 (GIC_CPU_MASK_SIMPLE(8) | IRQ_TYPE_LEVEL_LOW)>,
			     <GIC_PPI 11 (GIC_CPU_MASK_SIMPLE(8) | IRQ_TYPE_LEVEL_LOW)>,
			     <GIC_PPI 10 (GIC_CPU_MASK_SIMPLE(8) | IRQ_TYPE_LEVEL_LOW)>;
	};


	soc: soc@0 {
		compatible = "simple-bus";
		ranges = <0x0 0x0 0x0 0x20000000>;

		#address-cells = <1>;
		#size-cells = <1>;

		gic: interrupt-controller@10100000 {
			compatible = "arm,gic-400";
			#interrupt-cells = <3>;
			#address-cells = <0>;
			interrupt-controller;
			reg = <0x10101000 0x1000>,
			      <0x10102000 0x2000>,
			      <0x10104000 0x2000>,
			      <0x10106000 0x2000>;
			interrupts = <GIC_PPI 9 (GIC_CPU_MASK_SIMPLE(8) |
						 IRQ_TYPE_LEVEL_HIGH)>;
		};

	};
};