Obfuscate Verilog/SystemVerilog code

!readme.md

Basics

Use Verible Code Obfuscator for obfuscation.

Obfuscate foo.v and save dictionary with all replacements:

verible-verilog-obfuscate --save_map obf.map < foo.v > foo_obf.v

Remove all comments inside bar.v:

verible-verilog-preprocessor strip-comments bar.v

obfuscate.py

Steps:

• Save list with all Verilog/SystemVerilog sources to file obf.files.
• Add module name and interface signals to ignore.map.
• Run script python3 obfuscate.py.

Output artifacts:

• merged.v - all sources without comments merged to one file
• obfuscated.v - obfuscated merged.v
• obfuscated_nf.v - obfuscated.v without any formatting
• obf.map - dictionary of replacements

ignore.map

pclk pclk
presetn presetn
psel psel
paddr paddr
penable penable
pwrite pwrite
pwdata pwdata
pstrb pstrb
prdata prdata
pready pready
pslverr pslverr

obf.files

top.sv
fifo.sv
apb.sv

obfuscate.py

import os

if __name__ == '__main__':
    # get all source paths from some file 
    with open('obf.files', 'r') as sources_f:
        sources = sources_f.read().splitlines()

    # strip comments and merge all sources to the one output file
    os.system(' > merged.v')  # clear file
    for src in sources:
        os.system('./verible-verilog-preprocessor strip-comments %s >> merged.v' % src)

    # obfuscate this file and preserve only signals specified in ignore.map
    os.system('./verible-verilog-obfuscate --load_map ignore.map --save_map obf.map < merged.v > obfuscated.v')

    # remove formatting: spaces, newlines and tabs
    os.system("tr -s ' ' < obfuscated.v | tr -d '\t' | tr -d '\n' > obfuscated_nf.v")