spl.c

/* Samsung K4B2G1646Q-BY */
#define K4B2G1646QBY_EMIF_READ_LATENCY		0x07
#define K4B2G1646QBY_EMIF_TIM1			0x0AAAD4DB
#define K4B2G1646QBY_EMIF_TIM2			0x26437FDA
#define K4B2G1646QBY_EMIF_TIM3			0x501F83FF
#define K4B2G1646QBY_EMIF_SDCFG			0x61C052B2
#define K4B2G1646QBY_EMIF_SDREF			0x2000049E
#define K4B2G1646QBY_ZQ_CFG			0x50074BE4
#define K4B2G1646QBY_RATIO			0x80
#define K4B2G1646QBY_INVERT_CLKOUT		0x0
#define K4B2G1646QBY_RD_DQS			0x3B
#define K4B2G1646QBY_WR_DQS			0x3E
#define K4B2G1646QBY_PHY_FIFO_WE		0x98
#define K4B2G1646QBY_PHY_WR_DATA		0x78
#define K4B2G1646QBY_IOCTRL_VALUE		0x18B

// -------------------

static struct ddr_data const	ddr3_data = {
	.datardsratio0		= K4B2G1646QBY_RD_DQS,
	.datawdsratio0		= K4B2G1646QBY_WR_DQS,
	.datafwsratio0		= K4B2G1646QBY_PHY_FIFO_WE,
	.datawrsratio0		= K4B2G1646QBY_PHY_WR_DATA,
};

static struct cmd_control const	ddr3_cmd_ctrl_data = {
	.cmd0csratio		= K4B2G1646QBY_RATIO,
	.cmd0iclkout		= K4B2G1646QBY_INVERT_CLKOUT,

	.cmd1csratio		= K4B2G1646QBY_RATIO,
	.cmd1iclkout		= K4B2G1646QBY_INVERT_CLKOUT,

	.cmd2csratio		= K4B2G1646QBY_RATIO,
	.cmd2iclkout		= K4B2G1646QBY_INVERT_CLKOUT,
};

static struct emif_regs const	ddr3_emif_reg_data = {
	.sdram_config		= K4B2G1646QBY_EMIF_SDCFG,
	.ref_ctrl		= (0x20000000 | (400 * 39 / 10)),
	.sdram_tim1		= K4B2G1646QBY_EMIF_TIM1,
	.sdram_tim2		= K4B2G1646QBY_EMIF_TIM2,
	.sdram_tim3		= K4B2G1646QBY_EMIF_TIM3,
	.zq_config		= K4B2G1646QBY_ZQ_CFG,
	.emif_ddr_phy_ctlr_1	= K4B2G1646QBY_EMIF_READ_LATENCY,
};

static struct ctrl_ioregs const	ioregs = {
	.cm0ioctl		= K4B2G1646QBY_IOCTRL_VALUE,
	.cm1ioctl		= K4B2G1646QBY_IOCTRL_VALUE,
	.cm2ioctl		= K4B2G1646QBY_IOCTRL_VALUE,
	.dt0ioctl		= K4B2G1646QBY_IOCTRL_VALUE,
	.dt1ioctl		= K4B2G1646QBY_IOCTRL_VALUE,
};

void sdram_init(void)
{
	config_ddr(400, &ioregs,
		   &ddr3_data,
		   &ddr3_cmd_ctrl_data,
		   &ddr3_emif_reg_data, 0);

	udelay(250);
}

const struct dpll_params *get_dpll_ddr_params(void)
{
	int ind = get_sys_clk_index();

	return &dpll_ddr3_400MHz[ind];
}