Example script for generate a block design.

zynq_shared_memory.tcl

## Shared memory between microblaze and hdl for share parameters.
## Digital tav

set projectDir ../project

## Delete log and journal
file delete {*}[glob vivado*.backup.jou]
file delete {*}[glob vivado*.backup.log]
file delete -force .Xil/

## Create project in ../project
create_project -force $projectDir/zynq_shared_memory.xpr

## Set verilog as default language
set_property target_language Verilog [current_project]

## Adding verilog files
add_file ../src/bram_filler.v

## Set current board. Microzed
set_property BOARD_PART em.avnet.com:microzed_7020:part0:1.1 [current_project]

## Create block design
create_bd_design zynq_shared_mem_bd

## Configure block design through external file
source ./zynq_shared_memory_bd_2018.3.tcl

## Regenerate block design layout
regenerate_bd_layout

## Validate block design design
validate_bd_design

## Generate and add wrapper file for synthesis
make_wrapper -files [get_files $projectDir/zynq_shared_memory.srcs/sources_1/bd/zynq_shared_mem_bd/zynq_shared_mem_bd.bd] -top
add_files -norecurse $projectDir/zynq_shared_memory.srcs/sources_1/bd/zynq_shared_mem_bd/hdl/zynq_shared_mem_bd_wrapper.v

## Open vivado for verify
start_gui