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@controlpaths
Created March 21, 2020 11:07
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Clock forwarding example for Xilinx 7 series
/* Clock forwarding for DAC. Single anded clock */
ODDR #(
.DDR_CLK_EDGE("SAME_EDGE"),
.INIT(1'b0),
.SRTYPE("SYNC")
)ODDR_CLKDAC(
.Q(o_dac_clkout),
.C(clk100mhz),
.CE(1'b1),
.D1(1'b0),
.D2(1'b1),
.R(rst),
.S(1'b0)
);
/* Clock forwarding for ADC. Differential clock */
ODDR #(
.DDR_CLK_EDGE("SAME_EDGE"),
.INIT(1'b0),
.SRTYPE("SYNC")
)ODDR_CLKADC(
.Q(clk50mhz_ddr),
.C(clk50mhz),
.CE(1'b1),
.D1(1'b0),
.D2(1'b1),
.R(rst),
.S(1'b0)
);
OBUFDS #(
.IOSTANDARD("DEFAULT"),
.SLEW("SLOW")
) OBUFDS_CLKADC (
.O(o_adc_clkout_p),
.OB(o_adc_clkout_n),
.I(clk50mhz_ddr)
);
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