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Decimate module by 4
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| /** | |
| Module name: decimate_x4_v1_0 | |
| Author: P Trujillo (pablo@controlpaths.com) | |
| Date: Nov 2020 | |
| Description: Module to decimate by 4 increasing 1 bit resolution. | |
| Revision: 1.0 Module created. | |
| **/ | |
| module decimate_x4_v1_0 #( | |
| parameter pw_input_width = 14 | |
| )( | |
| input clk, | |
| input rstn, | |
| input signed [pw_input_width-1:0] i_data, | |
| input i_data_valid, | |
| output o_data_valid, | |
| output reg signed [pw_input_width:0] or_data | |
| ); | |
| reg signed [pw_input_width:0] rp_data_0; | |
| reg signed [pw_input_width:0] rp_data_1; | |
| reg signed [pw_input_width:0] rp_data_2; | |
| reg signed [pw_input_width:0] rp_data_3; | |
| reg [1:0] r2_data_counter; | |
| always @(posedge clk) | |
| if (!rstn) begin | |
| rp_data_1 <= 0; | |
| rp_data_2 <= 0; | |
| rp_data_3 <= 0; | |
| r2_data_counter <= 2'd0; | |
| end | |
| else | |
| if (i_data_valid) begin | |
| rp_data_0 <= {i_data[13], i_data}; | |
| rp_data_1 <= rp_data_0; | |
| rp_data_2 <= rp_data_1; | |
| rp_data_3 <= rp_data_2; | |
| r2_data_counter <= r2_data_counter + 2'b1; | |
| end | |
| always @(posedge clk) | |
| if (!rstn) | |
| or_data <= 0; | |
| else | |
| if (&r2_data_counter) | |
| or_data <= rp_data_0[14:1] + rp_data_1[14:1] + rp_data_2[14:1] + rp_data_3[14:1]; | |
| endmodule |
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