Displaying bus value at the end of time slot #systemverilog

ignore_bus_assignment_delta_cycles.rst

SystemVerilog: Display eventual observed bus value

Problem: For a bus, ignore delta cycle changes and report only the eventual value at the and of the current time (slot).

`timescale 1ns/1ps

module tb;

logic [3:0] my_bus;

initial $timeformat(-9, 3, " ns", 10);

initial begin
    my_bus = '0;
    $display("0: %t: new value: %bb", $realtime, my_bus);

    #5ns;
    foreach (my_bus[i]) begin
        my_bus[i] = ~my_bus[i];
        #1;
    end
    $display("0: %t: new value: %bb", $realtime, my_bus);

    #(10ns - $realtime);
    foreach (my_bus[i]) begin
        my_bus[i] = ~my_bus[i];
        #0;
    end
    $display("0: %t: new value: %bb", $realtime, my_bus);

    #(15ns - $realtime);
    $finish;
end

initial begin
    logic[3:0] old_val;
    realtime tstamp;

    old_val = my_bus;
    tstamp = $realtime;
    forever begin
        @(my_bus)
        if ($realtime > tstamp) begin
            tstamp = $realtime;
            if (old_val != my_bus) begin
                $display("1: %t: new value: %bb", $realtime, my_bus);
                old_val = my_bus;
            end
        end
    end
end

initial begin
    logic[3:0] old_val;
    realtime tstamp;

    old_val = my_bus;
    tstamp = $realtime;
    forever begin
        @(my_bus)
        tstamp = $realtime;
        if (old_val != my_bus) begin
            $display("3: %t: new value: %bb", $realtime, my_bus);
            old_val = my_bus;
        end
    end
end

initial begin
    logic[3:0] old_val;
    realtime tstamp;
    event e;

    fork begin
        forever begin
            wait(e.triggered);
            $display("2: %t: new value: %bb", $realtime, my_bus);
            #1step;
        end
    end join_none

    old_val = my_bus;
    tstamp = $realtime;
    forever begin
        @(my_bus)
        if (old_val != my_bus) begin
            ->> e;
            old_val = my_bus;
        end
    end
end

initial begin
    logic[3:0] old_val;
    realtime tstamp;
    event e;

    fork begin
        forever begin
            wait(e.triggered);
            $display("4: %t: new value: %bb", $realtime, my_bus);
            #1step;
        end
    end join_none

    old_val = my_bus;
    tstamp = $realtime;
    forever begin
        @(my_bus)
        if (old_val != my_bus) begin
            -> e;
            old_val = my_bus;
        end
    end
end

initial begin
    forever begin
        @(my_bus);
        $monitor("6: %t: new value: %bb", $realtime, my_bus);
    end
end

program p1 (
    input logic[3:0] pbus
);
initial begin
    forever begin
        @(pbus);
        $display("5: %t: new value: %bb", $realtime, my_bus);
    end
end
endprogram

p1 p(.pbus(my_bus));

endmodule

The output from Questa 2024.1:

# 0:   0.000 ns: new value: 0000b
# 3:   5.000 ns: new value: 1000b
# 1:   5.000 ns: new value: 1000b
# 4:   5.000 ns: new value: 1000b
# 2:   5.000 ns: new value: 1000b
# 5:   5.000 ns: new value: 1000b
# 6:   5.000 ns: new value: 1000b
# 3:   6.000 ns: new value: 1100b
# 1:   6.000 ns: new value: 1100b
# 4:   6.000 ns: new value: 1100b
# 2:   6.000 ns: new value: 1100b
# 5:   6.000 ns: new value: 1100b
# 6:   6.000 ns: new value: 1100b
# 3:   7.000 ns: new value: 1110b
# 1:   7.000 ns: new value: 1110b
# 4:   7.000 ns: new value: 1110b
# 2:   7.000 ns: new value: 1110b
# 5:   7.000 ns: new value: 1110b
# 6:   7.000 ns: new value: 1110b
# 3:   8.000 ns: new value: 1111b
# 1:   8.000 ns: new value: 1111b
# 4:   8.000 ns: new value: 1111b
# 2:   8.000 ns: new value: 1111b
# 5:   8.000 ns: new value: 1111b
# 6:   8.000 ns: new value: 1111b
# 0:   9.000 ns: new value: 1111b
# 3:  10.000 ns: new value: 0111b
# 1:  10.000 ns: new value: 0111b
# 4:  10.000 ns: new value: 0111b
# 3:  10.000 ns: new value: 0011b
# 3:  10.000 ns: new value: 0001b
# 3:  10.000 ns: new value: 0000b
# 0:  10.000 ns: new value: 0000b
# 2:  10.000 ns: new value: 0000b
# 5:  10.000 ns: new value: 0000b
# 6:  10.000 ns: new value: 0000b