sdram_sim.py

from amaranth import *
from amaranth.lib import wiring
from amaranth.lib.wiring import In, Out
from amaranth.sim import Simulator, SimulatorContext
from dataclasses import dataclass

@dataclass
class SdramSpec:
    row_bits: int
    col_bits: int
    bank_bits: int
    data_bits: int
    dqm_bits: int

class SdramSimulator(wiring.Component):
    def __init__(self, spec: SdramSpec, init_data: list[int]):
        self.spec = spec
        self.addr_bits = max(spec.row_bits, spec.col_bits)
        self.init_data = init_data
        super().__init__({
            "addr": In(self.addr_bits),
            "bank": In(spec.bank_bits),
            "data_i": In(spec.data_bits),
            "dqm": In(spec.dqm_bits),
            "cke": In(1),
            "cs_n": In(1),
            "ras_n": In(1),
            "cas_n": In(1),
            "we_n": In(1),
            "data_o": Out(spec.data_bits),
        })

    def elaborate(self, platform):
        return Module()

    async def simulate(self, ctx: SimulatorContext):
        data = self.init_data[:]
        async for clk, rst, addr in ctx.tick().sample(self.addr):
            if clk:
                ctx.set(self.data_o, data[addr])

class Top(Elaboratable):
    def __init__(self, spec: SdramSpec, init_data: list[int]):
        self.spec = spec
        self.sim = SdramSimulator(spec, init_data)
        self.counter = Signal(spec.row_bits)
        self.result = Signal(spec.data_bits)

    def elaborate(self, platform):
        m = Module()

        m.submodules.sim = sim = self.sim

        m.d.sync += [
            self.counter.eq(self.counter + 1),
        ]
        m.d.comb += [
            sim.addr.eq(self.counter),
            self.result.eq(sim.data_o),
        ]

        return m

mini_spec = SdramSpec(
    row_bits=3,
    col_bits=2,
    bank_bits=1,
    data_bits=4,
    dqm_bits=1,
)

init_data = [0xD, 0xA, 0xB, 0xB, 0xE, 0xD, 0x0, 0x1]
dut = Top(mini_spec, init_data)
sim = Simulator(dut)
sim.add_process(dut.sim.simulate)
sim.add_clock(1e-6)
with sim.write_vcd("test.vcd", traces=[dut.counter, dut.result]):
    sim.run_until(10e-6)