Created
August 18, 2020 14:13
-
-
Save bbrezillon/f3ece2f41fde4d88602be9395873a59d to your computer and use it in GitHub Desktop.
This file contains hidden or bidirectional Unicode text that may be interpreted or compiled differently than what appears below. To review, open the file in an editor that reveals hidden Unicode characters.
Learn more about bidirectional Unicode characters
| shader: MESA_SHADER_KERNEL | |
| local-size: 12, 1, 1 (variable) | |
| shared-size: 0 | |
| inputs: 2 | |
| outputs: 0 | |
| uniforms: 0 | |
| shared: 0 | |
| decl_var ubo INTERP_MODE_NONE uint[4] kernel_inputs (0, 0, 0) | |
| decl_var ubo INTERP_MODE_NONE uint[11] kernel_work_properies (0, 0, 1) | |
| decl_var shader_in INTERP_MODE_NONE uint64_t @0 (0.x, 0, 0) | |
| decl_var shader_in INTERP_MODE_NONE uint64_t @1 (1.x, 8, 0) | |
| decl_function __wrapped_main_test (0 params) (entrypoint) | |
| impl __wrapped_main_test { | |
| block block_0: | |
| /* preds: */ | |
| vec1 32 ssa_48 = load_const (0x00000000 /* 0.000000 */) | |
| vec4 32 ssa_67 = intrinsic load_ubo_dxil (ssa_48, ssa_48) () | |
| vec1 32 ssa_442 = mov ssa_67.y | |
| vec4 32 ssa_87 = intrinsic load_ubo_dxil (ssa_48, ssa_48) () | |
| vec1 32 ssa_440 = mov ssa_87.w | |
| vec3 32 ssa_42 = intrinsic load_global_invocation_id () () | |
| vec1 32 ssa_31 = load_const (0x00000003 /* 0.000000 */) | |
| vec1 32 ssa_32 = ishl ssa_42.x, ssa_31 | |
| vec1 32 ssa_35 = iadd ssa_87.z, ssa_32 | |
| vec1 32 ssa_103 = load_const (0xfffffffc /* -nan */) | |
| vec1 32 ssa_104 = iand ssa_35, ssa_103 | |
| vec2 32 ssa_107 = intrinsic load_ssbo (ssa_440, ssa_104) (0, 4, 0) /* access=0 */ /* align_mul=4 */ /* align_offset=0 */ | |
| vec1 1 ssa_134 = ilt ssa_107.y, ssa_48 | |
| vec1 32 ssa_136 = load_const (0x3f800000 /* 1.000000 */) | |
| vec1 32 ssa_137 = load_const (0xbf800000 /* -1.000000 */) | |
| vec1 32 ssa_138 = bcsel ssa_134, ssa_137, ssa_136 | |
| vec1 32 ssa_475 = load_const (0x00000000 /* 0.000000 */) | |
| vec1 32 ssa_476 = isub ssa_475, ssa_107.x | |
| vec1 1 ssa_274 = ult ssa_48, ssa_107.x | |
| vec1 32 ssa_275 = b2i32 ssa_274 | |
| vec1 32 ssa_473 = load_const (0x00000000 /* 0.000000 */) | |
| vec1 32 ssa_474 = isub ssa_473, ssa_275 | |
| vec1 32 ssa_471 = load_const (0x00000000 /* 0.000000 */) | |
| vec1 32 ssa_472 = isub ssa_471, ssa_107.y | |
| vec1 32 ssa_470 = isub ssa_472, ssa_275 | |
| vec1 32 ssa_284 = bcsel ssa_134, ssa_470, ssa_107.y | |
| vec1 32 ssa_285 = bcsel ssa_134, ssa_476, ssa_107.x | |
| vec1 32 ssa_146 = ufind_msb ssa_285 | |
| vec1 32 ssa_147 = ufind_msb ssa_284 | |
| vec1 1 ssa_149 = ine ssa_284, ssa_48 | |
| vec1 32 ssa_150 = load_const (0x00000020 /* 0.000000 */) | |
| vec1 32 ssa_151 = iadd ssa_150, ssa_147 | |
| vec1 32 ssa_152 = bcsel ssa_149, ssa_151, ssa_146 | |
| vec1 32 ssa_447 = load_const (0xffffffe9 /* -nan */) | |
| vec1 32 ssa_432 = iadd ssa_152, ssa_447 | |
| vec1 32 ssa_156 = imax ssa_432, ssa_48 | |
| vec1 32 ssa_159 = load_const (0xffffffe0 /* -nan */) | |
| vec1 32 ssa_160 = iadd ssa_156, ssa_159 | |
| vec1 32 ssa_477 = load_const (0x00000000 /* 0.000000 */) | |
| vec1 32 ssa_478 = isub ssa_477, ssa_160 | |
| vec1 32 ssa_469 = imax ssa_160, ssa_478 | |
| vec1 32 ssa_162 = ushr ssa_285, ssa_156 | |
| vec1 32 ssa_164 = ishl ssa_284, ssa_469 | |
| vec1 32 ssa_165 = ior ssa_162, ssa_164 | |
| vec1 32 ssa_168 = ushr ssa_284, ssa_469 | |
| vec1 1 ssa_171 = uge ssa_156, ssa_150 | |
| vec1 32 ssa_292 = bcsel ssa_171, ssa_168, ssa_165 | |
| vec1 1 ssa_174 = ieq ssa_156, ssa_48 | |
| vec1 32 ssa_299 = bcsel ssa_174, ssa_285, ssa_292 | |
| vec1 32 ssa_395 = load_const (0x00000001 /* 0.000000 */) | |
| vec1 32 ssa_183 = ishl ssa_395, ssa_156 | |
| vec1 32 ssa_185 = ushr ssa_395, ssa_469 | |
| vec1 32 ssa_189 = ishl ssa_395, ssa_469 | |
| vec1 32 ssa_305 = bcsel ssa_171, ssa_189, ssa_185 | |
| vec1 32 ssa_306 = bcsel ssa_171, ssa_48, ssa_183 | |
| vec1 32 ssa_312 = bcsel ssa_174, ssa_48, ssa_305 | |
| vec1 32 ssa_313 = bcsel ssa_174, ssa_395, ssa_306 | |
| vec1 32 ssa_448 = load_const (0xffffffff /* -nan */) | |
| vec1 32 ssa_429 = iadd ssa_313, ssa_448 | |
| vec1 1 ssa_203 = ult ssa_313, ssa_395 | |
| vec1 32 ssa_204 = b2i32 ssa_203 | |
| vec1 32 ssa_466 = load_const (0x00000000 /* 0.000000 */) | |
| vec1 32 ssa_467 = isub ssa_466, ssa_204 | |
| vec1 32 ssa_465 = isub ssa_312, ssa_204 | |
| vec1 32 ssa_402 = load_const (0x0000001f /* 0.000000 */) | |
| vec1 32 ssa_215 = ushr ssa_313, ssa_395 | |
| vec1 32 ssa_216 = ishr ssa_312, ssa_395 | |
| vec1 32 ssa_217 = ishl ssa_312, ssa_402 | |
| vec1 32 ssa_218 = ior ssa_215, ssa_217 | |
| vec1 32 ssa_234 = iand ssa_284, ssa_465 | |
| vec1 32 ssa_235 = iand ssa_285, ssa_429 | |
| vec1 1 ssa_241 = ieq ssa_235, ssa_218 | |
| vec1 1 ssa_242 = ieq ssa_234, ssa_216 | |
| vec1 1 ssa_243 = iand ssa_242, ssa_241 | |
| vec1 1 ssa_245 = ine ssa_156, ssa_48 | |
| vec1 1 ssa_246 = iand ssa_243, ssa_245 | |
| vec1 32 ssa_248 = iand ssa_299, ssa_395 | |
| vec1 1 ssa_446 = ine ssa_248, ssa_48 | |
| vec1 1 ssa_254 = ult ssa_218, ssa_235 | |
| vec1 1 ssa_256 = iand ssa_242, ssa_254 | |
| vec1 1 ssa_257 = ilt ssa_216, ssa_234 | |
| vec1 1 ssa_258 = ior ssa_257, ssa_256 | |
| vec1 1 ssa_259 = iand ssa_246, ssa_446 | |
| vec1 1 ssa_260 = ior ssa_258, ssa_259 | |
| vec1 32 ssa_261 = b2i32 ssa_260 | |
| vec1 32 ssa_262 = iadd ssa_299, ssa_261 | |
| vec1 32 ssa_263 = u2f32 ssa_156 | |
| vec1 32 ssa_264 = fexp2 ssa_263 | |
| vec1 32 ssa_265 = u2f32 ssa_262 | |
| vec1 32 ssa_266 = fmul ssa_265, ssa_264 | |
| vec1 32 ssa_267 = fmul ssa_266, ssa_138 | |
| vec1 1 ssa_420 = flt ssa_48, ssa_267 | |
| vec1 32 ssa_421 = b2f32 ssa_420 | |
| vec1 1 ssa_423 = flt ssa_267, ssa_48 | |
| vec1 32 ssa_424 = b2f32 ssa_423 | |
| vec1 32 ssa_331 = load_const (0xdf000000 /* -9223372036854775808.000000 */) | |
| vec1 32 ssa_333 = load_const (0x5f000000 /* 9223372036854775808.000000 */) | |
| vec1 1 ssa_335 = fge ssa_331, ssa_267 | |
| vec1 1 ssa_336 = fge ssa_267, ssa_333 | |
| vec1 32 ssa_337 = fabs ssa_267 | |
| vec1 32 ssa_338 = load_const (0x4f800000 /* 4294967296.000000 */) | |
| vec1 32 ssa_339 = fdiv ssa_337, ssa_338 | |
| vec1 32 ssa_340 = f2u32 ssa_339 | |
| vec1 32 ssa_456 = load_const (0x00000000 /* 0.000000 */) | |
| vec1 32 ssa_457 = isub ssa_456, ssa_340 | |
| vec1 32 ssa_416 = ftrunc ssa_339 | |
| vec1 32 ssa_417 = fmul ssa_338, ssa_416 | |
| vec1 32 ssa_463 = load_const (0xbf800000 /* -1.000000 */) | |
| vec1 32 ssa_464 = fmul ssa_417, ssa_463 | |
| vec1 32 ssa_462 = fsub ssa_337, ssa_417 | |
| vec1 32 ssa_342 = f2u32 ssa_462 | |
| vec1 32 ssa_460 = load_const (0x00000000 /* 0.000000 */) | |
| vec1 32 ssa_461 = isub ssa_460, ssa_342 | |
| vec1 1 ssa_454 = flt ssa_421, ssa_424 | |
| vec1 1 ssa_356 = ult ssa_48, ssa_342 | |
| vec1 32 ssa_357 = b2i32 ssa_356 | |
| vec1 32 ssa_458 = load_const (0x00000000 /* 0.000000 */) | |
| vec1 32 ssa_459 = isub ssa_458, ssa_357 | |
| vec1 32 ssa_455 = isub ssa_457, ssa_357 | |
| vec1 32 ssa_366 = bcsel ssa_454, ssa_455, ssa_340 | |
| vec1 32 ssa_367 = bcsel ssa_454, ssa_461, ssa_342 | |
| vec1 32 ssa_408 = load_const (0x7fffffff /* nan */) | |
| vec1 32 ssa_373 = bcsel ssa_336, ssa_408, ssa_366 | |
| vec1 32 ssa_374 = bcsel ssa_336, ssa_448, ssa_367 | |
| vec1 32 ssa_410 = load_const (0x80000000 /* -0.000000 */) | |
| vec1 32 ssa_380 = bcsel ssa_335, ssa_410, ssa_373 | |
| vec1 32 ssa_381 = bcsel ssa_335, ssa_48, ssa_374 | |
| vec1 32 ssa_25 = iadd ssa_67.x, ssa_32 | |
| vec1 32 ssa_113 = iand ssa_25, ssa_103 | |
| vec2 32 ssa_118 = vec2 ssa_381, ssa_380 | |
| intrinsic store_ssbo (ssa_118, ssa_442, ssa_113) (0, 0, 4, 0) /* wrmask= */ /* access=0 */ /* align_mul=4 */ /* align_offset=0 */ | |
| /* succs: block_1 */ | |
| block block_1: | |
| } | |
| Convert 'vec1 32 ssa_48 = load_const (0x00000000 /* 0.000000 */)' | |
| Convert 'vec4 32 ssa_67 = intrinsic load_ubo_dxil (ssa_48, ssa_48) ()' | |
| Convert 'vec1 32 ssa_442 = mov ssa_67.y' | |
| Convert 'vec4 32 ssa_87 = intrinsic load_ubo_dxil (ssa_48, ssa_48) ()' | |
| Convert 'vec1 32 ssa_440 = mov ssa_87.w' | |
| Convert 'vec3 32 ssa_42 = intrinsic load_global_invocation_id () ()' | |
| Convert 'vec1 32 ssa_31 = load_const (0x00000003 /* 0.000000 */)' | |
| Convert 'vec1 32 ssa_32 = ishl ssa_42.x, ssa_31' | |
| Convert 'vec1 32 ssa_35 = iadd ssa_87.z, ssa_32' | |
| Convert 'vec1 32 ssa_103 = load_const (0xfffffffc /* -nan */)' | |
| Convert 'vec1 32 ssa_104 = iand ssa_35, ssa_103' | |
| Convert 'vec2 32 ssa_107 = intrinsic load_ssbo (ssa_440, ssa_104) (0, 4, 0) /* access=0 */ /* align_mul=4 */ /* align_offset=0 */' | |
| Convert 'vec1 1 ssa_134 = ilt ssa_107.y, ssa_48' | |
| Convert 'vec1 32 ssa_136 = load_const (0x3f800000 /* 1.000000 */)' | |
| Convert 'vec1 32 ssa_137 = load_const (0xbf800000 /* -1.000000 */)' | |
| Convert 'vec1 32 ssa_138 = bcsel ssa_134, ssa_137, ssa_136' | |
| Convert 'vec1 32 ssa_475 = load_const (0x00000000 /* 0.000000 */)' | |
| Convert 'vec1 32 ssa_476 = isub ssa_475, ssa_107.x' | |
| Convert 'vec1 1 ssa_274 = ult ssa_48, ssa_107.x' | |
| Convert 'vec1 32 ssa_275 = b2i32 ssa_274' | |
| Convert 'vec1 32 ssa_473 = load_const (0x00000000 /* 0.000000 */)' | |
| Convert 'vec1 32 ssa_474 = isub ssa_473, ssa_275' | |
| Convert 'vec1 32 ssa_471 = load_const (0x00000000 /* 0.000000 */)' | |
| Convert 'vec1 32 ssa_472 = isub ssa_471, ssa_107.y' | |
| Convert 'vec1 32 ssa_470 = isub ssa_472, ssa_275' | |
| Convert 'vec1 32 ssa_284 = bcsel ssa_134, ssa_470, ssa_107.y' | |
| Convert 'vec1 32 ssa_285 = bcsel ssa_134, ssa_476, ssa_107.x' | |
| Convert 'vec1 32 ssa_146 = ufind_msb ssa_285' | |
| Convert 'vec1 32 ssa_147 = ufind_msb ssa_284' | |
| Convert 'vec1 1 ssa_149 = ine ssa_284, ssa_48' | |
| Convert 'vec1 32 ssa_150 = load_const (0x00000020 /* 0.000000 */)' | |
| Convert 'vec1 32 ssa_151 = iadd ssa_150, ssa_147' | |
| Convert 'vec1 32 ssa_152 = bcsel ssa_149, ssa_151, ssa_146' | |
| Convert 'vec1 32 ssa_447 = load_const (0xffffffe9 /* -nan */)' | |
| Convert 'vec1 32 ssa_432 = iadd ssa_152, ssa_447' | |
| Convert 'vec1 32 ssa_156 = imax ssa_432, ssa_48' | |
| Convert 'vec1 32 ssa_159 = load_const (0xffffffe0 /* -nan */)' | |
| Convert 'vec1 32 ssa_160 = iadd ssa_156, ssa_159' | |
| Convert 'vec1 32 ssa_477 = load_const (0x00000000 /* 0.000000 */)' | |
| Convert 'vec1 32 ssa_478 = isub ssa_477, ssa_160' | |
| Convert 'vec1 32 ssa_469 = imax ssa_160, ssa_478' | |
| Convert 'vec1 32 ssa_162 = ushr ssa_285, ssa_156' | |
| Convert 'vec1 32 ssa_164 = ishl ssa_284, ssa_469' | |
| Convert 'vec1 32 ssa_165 = ior ssa_162, ssa_164' | |
| Convert 'vec1 32 ssa_168 = ushr ssa_284, ssa_469' | |
| Convert 'vec1 1 ssa_171 = uge ssa_156, ssa_150' | |
| Convert 'vec1 32 ssa_292 = bcsel ssa_171, ssa_168, ssa_165' | |
| Convert 'vec1 1 ssa_174 = ieq ssa_156, ssa_48' | |
| Convert 'vec1 32 ssa_299 = bcsel ssa_174, ssa_285, ssa_292' | |
| Convert 'vec1 32 ssa_395 = load_const (0x00000001 /* 0.000000 */)' | |
| Convert 'vec1 32 ssa_183 = ishl ssa_395, ssa_156' | |
| Convert 'vec1 32 ssa_185 = ushr ssa_395, ssa_469' | |
| Convert 'vec1 32 ssa_189 = ishl ssa_395, ssa_469' | |
| Convert 'vec1 32 ssa_305 = bcsel ssa_171, ssa_189, ssa_185' | |
| Convert 'vec1 32 ssa_306 = bcsel ssa_171, ssa_48, ssa_183' | |
| Convert 'vec1 32 ssa_312 = bcsel ssa_174, ssa_48, ssa_305' | |
| Convert 'vec1 32 ssa_313 = bcsel ssa_174, ssa_395, ssa_306' | |
| Convert 'vec1 32 ssa_448 = load_const (0xffffffff /* -nan */)' | |
| Convert 'vec1 32 ssa_429 = iadd ssa_313, ssa_448' | |
| Convert 'vec1 1 ssa_203 = ult ssa_313, ssa_395' | |
| Convert 'vec1 32 ssa_204 = b2i32 ssa_203' | |
| Convert 'vec1 32 ssa_466 = load_const (0x00000000 /* 0.000000 */)' | |
| Convert 'vec1 32 ssa_467 = isub ssa_466, ssa_204' | |
| Convert 'vec1 32 ssa_465 = isub ssa_312, ssa_204' | |
| Convert 'vec1 32 ssa_402 = load_const (0x0000001f /* 0.000000 */)' | |
| Convert 'vec1 32 ssa_215 = ushr ssa_313, ssa_395' | |
| Convert 'vec1 32 ssa_216 = ishr ssa_312, ssa_395' | |
| Convert 'vec1 32 ssa_217 = ishl ssa_312, ssa_402' | |
| Convert 'vec1 32 ssa_218 = ior ssa_215, ssa_217' | |
| Convert 'vec1 32 ssa_234 = iand ssa_284, ssa_465' | |
| Convert 'vec1 32 ssa_235 = iand ssa_285, ssa_429' | |
| Convert 'vec1 1 ssa_241 = ieq ssa_235, ssa_218' | |
| Convert 'vec1 1 ssa_242 = ieq ssa_234, ssa_216' | |
| Convert 'vec1 1 ssa_243 = iand ssa_242, ssa_241' | |
| Convert 'vec1 1 ssa_245 = ine ssa_156, ssa_48' | |
| Convert 'vec1 1 ssa_246 = iand ssa_243, ssa_245' | |
| Convert 'vec1 32 ssa_248 = iand ssa_299, ssa_395' | |
| Convert 'vec1 1 ssa_446 = ine ssa_248, ssa_48' | |
| Convert 'vec1 1 ssa_254 = ult ssa_218, ssa_235' | |
| Convert 'vec1 1 ssa_256 = iand ssa_242, ssa_254' | |
| Convert 'vec1 1 ssa_257 = ilt ssa_216, ssa_234' | |
| Convert 'vec1 1 ssa_258 = ior ssa_257, ssa_256' | |
| Convert 'vec1 1 ssa_259 = iand ssa_246, ssa_446' | |
| Convert 'vec1 1 ssa_260 = ior ssa_258, ssa_259' | |
| Convert 'vec1 32 ssa_261 = b2i32 ssa_260' | |
| Convert 'vec1 32 ssa_262 = iadd ssa_299, ssa_261' | |
| Convert 'vec1 32 ssa_263 = u2f32 ssa_156' | |
| Convert 'vec1 32 ssa_264 = fexp2 ssa_263' | |
| Convert 'vec1 32 ssa_265 = u2f32 ssa_262' | |
| Convert 'vec1 32 ssa_266 = fmul ssa_265, ssa_264' | |
| Convert 'vec1 32 ssa_267 = fmul ssa_266, ssa_138' | |
| Convert 'vec1 1 ssa_420 = flt ssa_48, ssa_267' | |
| Convert 'vec1 32 ssa_421 = b2f32 ssa_420' | |
| Convert 'vec1 1 ssa_423 = flt ssa_267, ssa_48' | |
| Convert 'vec1 32 ssa_424 = b2f32 ssa_423' | |
| Convert 'vec1 32 ssa_331 = load_const (0xdf000000 /* -9223372036854775808.000000 */)' | |
| Convert 'vec1 32 ssa_333 = load_const (0x5f000000 /* 9223372036854775808.000000 */)' | |
| Convert 'vec1 1 ssa_335 = fge ssa_331, ssa_267' | |
| Convert 'vec1 1 ssa_336 = fge ssa_267, ssa_333' | |
| Convert 'vec1 32 ssa_337 = fabs ssa_267' | |
| Convert 'vec1 32 ssa_338 = load_const (0x4f800000 /* 4294967296.000000 */)' | |
| Convert 'vec1 32 ssa_339 = fdiv ssa_337, ssa_338' | |
| Convert 'vec1 32 ssa_340 = f2u32 ssa_339' | |
| Convert 'vec1 32 ssa_456 = load_const (0x00000000 /* 0.000000 */)' | |
| Convert 'vec1 32 ssa_457 = isub ssa_456, ssa_340' | |
| Convert 'vec1 32 ssa_416 = ftrunc ssa_339' | |
| Convert 'vec1 32 ssa_417 = fmul ssa_338, ssa_416' | |
| Convert 'vec1 32 ssa_463 = load_const (0xbf800000 /* -1.000000 */)' | |
| Convert 'vec1 32 ssa_464 = fmul ssa_417, ssa_463' | |
| Convert 'vec1 32 ssa_462 = fsub ssa_337, ssa_417' | |
| Convert 'vec1 32 ssa_342 = f2u32 ssa_462' | |
| Convert 'vec1 32 ssa_460 = load_const (0x00000000 /* 0.000000 */)' | |
| Convert 'vec1 32 ssa_461 = isub ssa_460, ssa_342' | |
| Convert 'vec1 1 ssa_454 = flt ssa_421, ssa_424' | |
| Convert 'vec1 1 ssa_356 = ult ssa_48, ssa_342' | |
| Convert 'vec1 32 ssa_357 = b2i32 ssa_356' | |
| Convert 'vec1 32 ssa_458 = load_const (0x00000000 /* 0.000000 */)' | |
| Convert 'vec1 32 ssa_459 = isub ssa_458, ssa_357' | |
| Convert 'vec1 32 ssa_455 = isub ssa_457, ssa_357' | |
| Convert 'vec1 32 ssa_366 = bcsel ssa_454, ssa_455, ssa_340' | |
| Convert 'vec1 32 ssa_367 = bcsel ssa_454, ssa_461, ssa_342' | |
| Convert 'vec1 32 ssa_408 = load_const (0x7fffffff /* nan */)' | |
| Convert 'vec1 32 ssa_373 = bcsel ssa_336, ssa_408, ssa_366' | |
| Convert 'vec1 32 ssa_374 = bcsel ssa_336, ssa_448, ssa_367' | |
| Convert 'vec1 32 ssa_410 = load_const (0x80000000 /* -0.000000 */)' | |
| Convert 'vec1 32 ssa_380 = bcsel ssa_335, ssa_410, ssa_373' | |
| Convert 'vec1 32 ssa_381 = bcsel ssa_335, ssa_48, ssa_374' | |
| Convert 'vec1 32 ssa_25 = iadd ssa_67.x, ssa_32' | |
| Convert 'vec1 32 ssa_113 = iand ssa_25, ssa_103' | |
| Convert 'vec2 32 ssa_118 = vec2 ssa_381, ssa_380' | |
| Convert 'intrinsic store_ssbo (ssa_118, ssa_442, ssa_113) (0, 0, 4, 0) /* wrmask= */ /* access=0 */ /* align_mul=4 */ /* align_offset=0 */' | |
| DXIL MODULE: | |
| Shader: COMPUTE | |
| Version: 6.1 | |
| Features: | |
| Shader Info: | |
| Types: | |
| float32 | |
| float32[4] | |
| struct kernel_inputs { | |
| float32[4] | |
| } | |
| struct kernel_inputs* | |
| int32 | |
| int8 | |
| int1 | |
| int8* | |
| struct dx.types.Handle { | |
| int8* | |
| } | |
| (struct dx.types.Handle)(int32, int8, int32, int32, int1) | |
| float32[11] | |
| struct kernel_work_properies { | |
| float32[11] | |
| } | |
| struct kernel_work_properies* | |
| struct (null) { | |
| int32 | |
| } | |
| struct (null)[2] | |
| struct (null)[2]* | |
| struct dx.types.CBufRet.i32 { | |
| int32 | |
| int32 | |
| int32 | |
| int32 | |
| } | |
| (struct dx.types.CBufRet.i32)(int32, struct dx.types.Handle, int32) | |
| (int32)(int32, int32) | |
| struct dx.types.ResRet.i32 { | |
| int32 | |
| int32 | |
| int32 | |
| int32 | |
| int32 | |
| } | |
| (struct dx.types.ResRet.i32)(int32, struct dx.types.Handle, int32, int32) | |
| (int32)(int32, int32) | |
| (int32)(int32, int32, int32) | |
| (float32)(int32, float32) | |
| void | |
| (void)(int32, struct dx.types.Handle, int32, int32, int32, int32, int32, int32, int8) | |
| (void)() | |
| (void)()* | |
| int64 | |
| Functions: | |
| declare dx.op.createHandle (struct dx.types.Handle)(int32, int8, int32, int32, int1) #1 | |
| declare dx.op.cbufferLoadLegacy.i32 (struct dx.types.CBufRet.i32)(int32, struct dx.types.Handle, int32) #1 | |
| declare dx.op.threadId.i32 (int32)(int32, int32) #2 | |
| declare dx.op.bufferLoad.i32 (struct dx.types.ResRet.i32)(int32, struct dx.types.Handle, int32, int32) #1 | |
| declare dx.op.unaryBits.i32 (int32)(int32, int32) #2 | |
| declare dx.op.binary.i32 (int32)(int32, int32, int32) #2 | |
| declare dx.op.unary.f32 (float32)(int32, float32) #2 | |
| declare dx.op.bufferStore.i32 (void)(int32, struct dx.types.Handle, int32, int32, int32, int32, int32, int32, int8) #3 | |
| main (void)() | |
| Attribute set: | |
| #1: {nounwind readonly} | |
| #2: {nounwind readnone} | |
| #3: {nounwind} | |
| Constants: | |
| %9struct kernel_inputs* = struct kernel_inputs* undef | |
| %10int32 = int32 0 | |
| %11int32 = int32 1 | |
| %12int32 = int32 16 | |
| %13int32 = int32 57 | |
| %14int8 = int8 2 | |
| %15int1 = int1 0 | |
| %16struct kernel_work_properies* = struct kernel_work_properies* undef | |
| %17int32 = int32 44 | |
| %18struct (null)[2]* = struct (null)[2]* undef | |
| %19int32 = int32 2 | |
| %20int32 = int32 11 | |
| %21int32 = int32 59 | |
| %22int32 = int32 93 | |
| %23int32 = int32 3 | |
| %24int32 = int32 -4 | |
| %25int32 = int32 undef | |
| %26int8 = int8 1 | |
| %27int32 = int32 68 | |
| %28int32 = int32 1065353216 | |
| %29int32 = int32 -1082130432 | |
| %30int32 = int32 33 | |
| %31int32 = int32 31 | |
| %32int32 = int32 -1 | |
| %33int32 = int32 32 | |
| %34int32 = int32 -23 | |
| %35int32 = int32 37 | |
| %36int32 = int32 -32 | |
| %37int32 = int32 21 | |
| %38float32 = float32 1.00000 | |
| %39float32 = float32 0.00000 | |
| %40int32 = int32 -553648128 | |
| %41int32 = int32 1593835520 | |
| %42int32 = int32 6 | |
| %43int32 = int32 1333788672 | |
| %44int32 = int32 29 | |
| %45int32 = int32 2147483647 | |
| %46int32 = int32 -2147483648 | |
| %47int8 = int8 3 | |
| %48int32 = int32 69 | |
| %49int32 = int32 4 | |
| %50int32 = int32 12 | |
| %51int64 = int64 16 | |
| Shader body: | |
| %52struct dx.types.Handle = dx.op.createHandle(int32 %13int32, int8 %14int8, int32 %10int32, int32 %10int32, int1 %15int1) | |
| %53struct dx.types.Handle = dx.op.createHandle(int32 %13int32, int8 %14int8, int32 %11int32, int32 %11int32, int1 %15int1) | |
| %54struct dx.types.CBufRet.i32 = dx.op.cbufferLoadLegacy.i32(int32 %21int32, struct dx.types.Handle %52struct dx.types.Handle, int32 %10int32) | |
| %55int32 = extractvalue struct dx.types.CBufRet.i32 %54struct dx.types.CBufRet.i32, 0 | |
| %56int32 = extractvalue struct dx.types.CBufRet.i32 %54struct dx.types.CBufRet.i32, 1 | |
| %57int32 = extractvalue struct dx.types.CBufRet.i32 %54struct dx.types.CBufRet.i32, 2 | |
| %58int32 = extractvalue struct dx.types.CBufRet.i32 %54struct dx.types.CBufRet.i32, 3 | |
| %59struct dx.types.CBufRet.i32 = dx.op.cbufferLoadLegacy.i32(int32 %21int32, struct dx.types.Handle %52struct dx.types.Handle, int32 %10int32) | |
| %60int32 = extractvalue struct dx.types.CBufRet.i32 %59struct dx.types.CBufRet.i32, 0 | |
| %61int32 = extractvalue struct dx.types.CBufRet.i32 %59struct dx.types.CBufRet.i32, 1 | |
| %62int32 = extractvalue struct dx.types.CBufRet.i32 %59struct dx.types.CBufRet.i32, 2 | |
| %63int32 = extractvalue struct dx.types.CBufRet.i32 %59struct dx.types.CBufRet.i32, 3 | |
| %64int32 = dx.op.threadId.i32(int32 %22int32, int32 %10int32) | |
| %65int32 = shl %64int32, %23int32 | |
| %66int32 = add %62int32, %65int32 | |
| %67int32 = and %66int32, %24int32 | |
| %68struct dx.types.Handle = dx.op.createHandle(int32 %13int32, int8 %26int8, int32 %10int32, int32 %63int32, int1 %15int1) | |
| %69struct dx.types.ResRet.i32 = dx.op.bufferLoad.i32(int32 %27int32, struct dx.types.Handle %68struct dx.types.Handle, int32 %67int32, int32 %25int32) | |
| %70int32 = extractvalue struct dx.types.ResRet.i32 %69struct dx.types.ResRet.i32, 0 | |
| %71int32 = extractvalue struct dx.types.ResRet.i32 %69struct dx.types.ResRet.i32, 1 | |
| %72int1 = iLT %71int32, %10int32 | |
| %73int32 = sel %72int1, %29int32, %28int32 | |
| %74int32 = sub %10int32, %70int32 | |
| %75int1 = uiLT %10int32, %70int32 | |
| %76int32 = zext.int32 %75int1 | |
| %77int32 = sub %10int32, %76int32 | |
| %78int32 = sub %10int32, %71int32 | |
| %79int32 = sub %78int32, %76int32 | |
| %80int32 = sel %72int1, %79int32, %71int32 | |
| %81int32 = sel %72int1, %74int32, %70int32 | |
| %82int32 = dx.op.unaryBits.i32(int32 %30int32, int32 %81int32) | |
| %83int32 = sub %31int32, %82int32 | |
| %84int1 = iNE %81int32, %10int32 | |
| %85int32 = sel %84int1, %83int32, %32int32 | |
| %86int32 = dx.op.unaryBits.i32(int32 %30int32, int32 %80int32) | |
| %87int32 = sub %31int32, %86int32 | |
| %88int1 = iNE %80int32, %10int32 | |
| %89int32 = sel %88int1, %87int32, %32int32 | |
| %90int1 = iNE %80int32, %10int32 | |
| %91int32 = add %33int32, %89int32 | |
| %92int32 = sel %90int1, %91int32, %85int32 | |
| %93int32 = add %92int32, %34int32 | |
| %94int32 = dx.op.binary.i32(int32 %35int32, int32 %93int32, int32 %10int32) | |
| %95int32 = add %94int32, %36int32 | |
| %96int32 = sub %10int32, %95int32 | |
| %97int32 = dx.op.binary.i32(int32 %35int32, int32 %95int32, int32 %96int32) | |
| %98int32 = lshr %81int32, %94int32 | |
| %99int32 = shl %80int32, %97int32 | |
| %100int32 = or %98int32, %99int32 | |
| %101int32 = lshr %80int32, %97int32 | |
| %102int1 = uiGE %94int32, %33int32 | |
| %103int32 = sel %102int1, %101int32, %100int32 | |
| %104int1 = iEQ %94int32, %10int32 | |
| %105int32 = sel %104int1, %81int32, %103int32 | |
| %106int32 = shl %11int32, %94int32 | |
| %107int32 = lshr %11int32, %97int32 | |
| %108int32 = shl %11int32, %97int32 | |
| %109int32 = sel %102int1, %108int32, %107int32 | |
| %110int32 = sel %102int1, %10int32, %106int32 | |
| %111int32 = sel %104int1, %10int32, %109int32 | |
| %112int32 = sel %104int1, %11int32, %110int32 | |
| %113int32 = add %112int32, %32int32 | |
| %114int1 = uiLT %112int32, %11int32 | |
| %115int32 = zext.int32 %114int1 | |
| %116int32 = sub %10int32, %115int32 | |
| %117int32 = sub %111int32, %115int32 | |
| %118int32 = lshr %112int32, %11int32 | |
| %119int32 = ashr %111int32, %11int32 | |
| %120int32 = shl %111int32, %31int32 | |
| %121int32 = or %118int32, %120int32 | |
| %122int32 = and %80int32, %117int32 | |
| %123int32 = and %81int32, %113int32 | |
| %124int1 = iEQ %123int32, %121int32 | |
| %125int1 = iEQ %122int32, %119int32 | |
| %126int1 = and %125int1, %124int1 | |
| %127int1 = iNE %94int32, %10int32 | |
| %128int1 = and %126int1, %127int1 | |
| %129int32 = and %105int32, %11int32 | |
| %130int1 = iNE %129int32, %10int32 | |
| %131int1 = uiLT %121int32, %123int32 | |
| %132int1 = and %125int1, %131int1 | |
| %133int1 = iLT %119int32, %122int32 | |
| %134int1 = or %133int1, %132int1 | |
| %135int1 = and %128int1, %130int1 | |
| %136int1 = or %134int1, %135int1 | |
| %137int32 = zext.int32 %136int1 | |
| %138int32 = add %105int32, %137int32 | |
| %139float32 = uitof.float32 %94int32 | |
| %140float32 = dx.op.unary.f32(int32 %37int32, float32 %139float32) | |
| %141float32 = uitof.float32 %138int32 | |
| %142float32 = mul %141float32, %140float32 | |
| %143float32 = bitcast.float32 %73int32 | |
| %144float32 = mul %142float32, %143float32 | |
| %145float32 = bitcast.float32 %10int32 | |
| %146int1 = ord-fLT %145float32, %144float32 | |
| %147float32 = sel %146int1, %38float32, %39float32 | |
| %148float32 = bitcast.float32 %10int32 | |
| %149int1 = ord-fLT %144float32, %148float32 | |
| %150float32 = sel %149int1, %38float32, %39float32 | |
| %151float32 = bitcast.float32 %40int32 | |
| %152int1 = ord-fGE %151float32, %144float32 | |
| %153float32 = bitcast.float32 %41int32 | |
| %154int1 = ord-fGE %144float32, %153float32 | |
| %155float32 = dx.op.unary.f32(int32 %42int32, float32 %144float32) | |
| %156float32 = bitcast.float32 %43int32 | |
| %157float32 = sdiv %155float32, %156float32 | |
| %158int32 = ftoui.int32 %157float32 | |
| %159int32 = sub %10int32, %158int32 | |
| %160float32 = dx.op.unary.f32(int32 %44int32, float32 %157float32) | |
| %161float32 = bitcast.float32 %43int32 | |
| %162float32 = mul %161float32, %160float32 | |
| %163float32 = bitcast.float32 %29int32 | |
| %164float32 = mul %162float32, %163float32 | |
| %165float32 = sub %155float32, %162float32 | |
| %166int32 = ftoui.int32 %165float32 | |
| %167int32 = sub %10int32, %166int32 | |
| %168int1 = ord-fLT %147float32, %150float32 | |
| %169int1 = uiLT %10int32, %166int32 | |
| %170int32 = zext.int32 %169int1 | |
| %171int32 = sub %10int32, %170int32 | |
| %172int32 = sub %159int32, %170int32 | |
| %173int32 = sel %168int1, %172int32, %158int32 | |
| %174int32 = sel %168int1, %167int32, %166int32 | |
| %175int32 = sel %154int1, %45int32, %173int32 | |
| %176int32 = sel %154int1, %32int32, %174int32 | |
| %177int32 = sel %152int1, %46int32, %175int32 | |
| %178int32 = sel %152int1, %10int32, %176int32 | |
| %179int32 = add %55int32, %65int32 | |
| %180int32 = and %179int32, %24int32 | |
| %181struct dx.types.Handle = dx.op.createHandle(int32 %13int32, int8 %26int8, int32 %10int32, int32 %56int32, int1 %15int1) | |
| dx.op.bufferStore.i32(int32 %48int32, struct dx.types.Handle %181struct dx.types.Handle, int32 %180int32, int32 %25int32, int32 %178int32, int32 %177int3 | |
| 2, int32 %25int32, int32 %25int32, int8 %47int8) | |
| ret | |
| MD-Nodes: | |
| V:int32 %10int32 | |
| V:struct kernel_inputs* %9struct kernel_inputs* | |
| S:kernel_inputs | |
| V:int32 %11int32 | |
| V:int32 %12int32 | |
| \ | |
| V:int32 %10int32 | |
| V:struct kernel_inputs* %9struct kernel_inputs* | |
| S:kernel_inputs | |
| V:int32 %10int32 | |
| V:int32 %10int32 | |
| V:int32 %11int32 | |
| V:int32 %12int32 | |
| (nullptr) | |
| V:struct kernel_work_properies* %16struct kernel_work_properies* | |
| S:kernel_work_properies | |
| V:int32 %17int32 | |
| \ | |
| V:int32 %11int32 | |
| V:struct kernel_work_properies* %16struct kernel_work_properies* | |
| S:kernel_work_properies | |
| V:int32 %10int32 | |
| V:int32 %11int32 | |
| V:int32 %11int32 | |
| V:int32 %17int32 | |
| (nullptr) | |
| V:struct (null)[2]* %18struct (null)[2]* | |
| S:globals | |
| V:int32 %19int32 | |
| V:int32 %20int32 | |
| V:int1 %15int1 | |
| \ | |
| V:int32 %10int32 | |
| V:struct (null)[2]* %18struct (null)[2]* | |
| S:globals | |
| V:int32 %10int32 | |
| V:int32 %10int32 | |
| V:int32 %19int32 | |
| V:int32 %20int32 | |
| V:int1 %15int1 | |
| V:int1 %15int1 | |
| V:int1 %15int1 | |
| (nullptr) | |
| S:Mesa version 20.1.0-devel (git-6684fb67ad) | |
| \ | |
| S:Mesa version 20.1.0-devel (git-6684fb67ad) | |
| \ | |
| V:int32 %11int32 | |
| V:int32 %11int32 | |
| V:int32 %49int32 | |
| \ | |
| V:int32 %11int32 | |
| V:int32 %49int32 | |
| S:cs | |
| V:int32 %42int32 | |
| \ | |
| S:cs | |
| V:int32 %42int32 | |
| V:int32 %11int32 | |
| \ | |
| \ | |
| V:int32 %10int32 | |
| V:struct (null)[2]* %18struct (null)[2]* | |
| S:globals | |
| V:int32 %10int32 | |
| V:int32 %10int32 | |
| V:int32 %19int32 | |
| V:int32 %20int32 | |
| V:int1 %15int1 | |
| V:int1 %15int1 | |
| V:int1 %15int1 | |
| (nullptr) | |
| \ | |
| \ | |
| V:int32 %10int32 | |
| V:struct kernel_inputs* %9struct kernel_inputs* | |
| S:kernel_inputs | |
| V:int32 %10int32 | |
| V:int32 %10int32 | |
| V:int32 %11int32 | |
| V:int32 %12int32 | |
| (nullptr) | |
| \ | |
| V:int32 %11int32 | |
| V:struct kernel_work_properies* %16struct kernel_work_properies* | |
| S:kernel_work_properies | |
| V:int32 %10int32 | |
| V:int32 %11int32 | |
| V:int32 %11int32 | |
| V:int32 %17int32 | |
| (nullptr) | |
| \ | |
| (nullptr) | |
| \ | |
| \ | |
| V:int32 %10int32 | |
| V:struct (null)[2]* %18struct (null)[2]* | |
| S:globals | |
| V:int32 %10int32 | |
| V:int32 %10int32 | |
| V:int32 %19int32 | |
| V:int32 %20int32 | |
| V:int1 %15int1 | |
| V:int1 %15int1 | |
| V:int1 %15int1 | |
| (nullptr) | |
| \ | |
| \ | |
| V:int32 %10int32 | |
| V:struct kernel_inputs* %9struct kernel_inputs* | |
| S:kernel_inputs | |
| V:int32 %10int32 | |
| V:int32 %10int32 | |
| V:int32 %11int32 | |
| V:int32 %12int32 | |
| (nullptr) | |
| \ | |
| V:int32 %11int32 | |
| V:struct kernel_work_properies* %16struct kernel_work_properies* | |
| S:kernel_work_properies | |
| V:int32 %10int32 | |
| V:int32 %11int32 | |
| V:int32 %11int32 | |
| V:int32 %17int32 | |
| (nullptr) | |
| (nullptr) | |
| V:(void)()* %8void | |
| \ | |
| \ | |
| V:int32 %10int32 | |
| \ | |
| \ | |
| \ | |
| \ | |
| V:int32 %10int32 | |
| \ | |
| \ | |
| \ | |
| V:int32 %11int32 | |
| V:(void)()* %8void | |
| \ | |
| \ | |
| V:int32 %10int32 | |
| \ | |
| \ | |
| V:int32 %50int32 | |
| \ | |
| V:int32 %50int32 | |
| V:int32 %11int32 | |
| V:int32 %11int32 | |
| V:int64 %51int64 | |
| \ | |
| V:int32 %49int32 | |
| \ | |
| V:int32 %50int32 | |
| V:int32 %11int32 | |
| V:int32 %11int32 | |
| V:int32 %10int32 | |
| V:int64 %51int64 | |
| S:main | |
| \ | |
| V:(void)()* %8void | |
| S:main | |
| (nullptr) | |
| \ | |
| (nullptr) | |
| \ | |
| \ | |
| V:int32 %10int32 | |
| V:struct (null)[2]* %18struct (null)[2]* | |
| S:globals | |
| V:int32 %10int32 | |
| V:int32 %10int32 | |
| V:int32 %19int32 | |
| V:int32 %20int32 | |
| V:int1 %15int1 | |
| V:int1 %15int1 | |
| V:int1 %15int1 | |
| (nullptr) | |
| \ | |
| \ | |
| V:int32 %10int32 | |
| V:struct kernel_inputs* %9struct kernel_inputs* | |
| S:kernel_inputs | |
| V:int32 %10int32 | |
| V:int32 %10int32 | |
| V:int32 %11int32 | |
| V:int32 %12int32 | |
| (nullptr) | |
| \ | |
| V:int32 %11int32 | |
| V:struct kernel_work_properies* %16struct kernel_work_properies* | |
| S:kernel_work_properies | |
| V:int32 %10int32 | |
| V:int32 %11int32 | |
| V:int32 %11int32 | |
| V:int32 %17int32 | |
| (nullptr) | |
| (nullptr) | |
| \ | |
| V:int32 %49int32 | |
| \ | |
| V:int32 %50int32 | |
| V:int32 %11int32 | |
| V:int32 %11int32 | |
| V:int32 %10int32 | |
| V:int64 %51int64 | |
| Named Nodes: | |
| llvm.ident: | |
| \ | |
| S:Mesa version 20.1.0-devel (git-6684fb67ad) | |
| dx.version: | |
| \ | |
| V:int32 %11int32 | |
| V:int32 %11int32 | |
| dx.valver: | |
| \ | |
| V:int32 %11int32 | |
| V:int32 %49int32 | |
| dx.shaderModel: | |
| \ | |
| S:cs | |
| V:int32 %42int32 | |
| V:int32 %11int32 | |
| dx.resources: | |
| \ | |
| (nullptr) | |
| \ | |
| \ | |
| V:int32 %10int32 | |
| V:struct (null)[2]* %18struct (null)[2]* | |
| S:globals | |
| V:int32 %10int32 | |
| V:int32 %10int32 | |
| V:int32 %19int32 | |
| V:int32 %20int32 | |
| V:int1 %15int1 | |
| V:int1 %15int1 | |
| V:int1 %15int1 | |
| (nullptr) | |
| \ | |
| \ | |
| V:int32 %10int32 | |
| V:struct kernel_inputs* %9struct kernel_inputs* | |
| S:kernel_inputs | |
| V:int32 %10int32 | |
| V:int32 %10int32 | |
| V:int32 %11int32 | |
| V:int32 %12int32 | |
| (nullptr) | |
| \ | |
| V:int32 %11int32 | |
| V:struct kernel_work_properies* %16struct kernel_work_properies* | |
| S:kernel_work_properies | |
| V:int32 %10int32 | |
| V:int32 %11int32 | |
| V:int32 %11int32 | |
| V:int32 %17int32 | |
| (nullptr) | |
| (nullptr) | |
| dx.typeAnnotations: | |
| \ | |
| V:int32 %11int32 | |
| V:(void)()* %8void | |
| \ | |
| \ | |
| V:int32 %10int32 | |
| \ | |
| \ | |
| dx.entryPoints: | |
| \ | |
| V:(void)()* %8void | |
| S:main | |
| (nullptr) | |
| \ | |
| (nullptr) | |
| \ | |
| \ | |
| V:int32 %10int32 | |
| V:struct (null)[2]* %18struct (null)[2]* | |
| S:globals | |
| V:int32 %10int32 | |
| V:int32 %10int32 | |
| V:int32 %19int32 | |
| V:int32 %20int32 | |
| V:int1 %15int1 | |
| V:int1 %15int1 | |
| V:int1 %15int1 | |
| (nullptr) | |
| \ | |
| \ | |
| V:int32 %10int32 | |
| V:struct kernel_inputs* %9struct kernel_inputs* | |
| S:kernel_inputs | |
| V:int32 %10int32 | |
| V:int32 %10int32 | |
| V:int32 %11int32 | |
| V:int32 %12int32 | |
| (nullptr) | |
| \ | |
| V:int32 %11int32 | |
| V:struct kernel_work_properies* %16struct kernel_work_properies* | |
| S:kernel_work_properies | |
| V:int32 %10int32 | |
| V:int32 %11int32 | |
| V:int32 %11int32 | |
| V:int32 %17int32 | |
| (nullptr) | |
| (nullptr) | |
| \ | |
| V:int32 %49int32 | |
| \ | |
| V:int32 %50int32 | |
| V:int32 %11int32 | |
| V:int32 %11int32 | |
| V:int32 %10int32 | |
| V:int64 %51int64 | |
| Input signature: | |
| SEMANTIC-NAME Index Mask Reg SysValue Format | |
| ---------------------------------------------- | |
| Output signature: | |
| SEMANTIC-NAME Index Mask Reg SysValue Format | |
| ---------------------------------------------- | |
| Pipeline State Validation | |
| Inputs: | |
| SEMANTIC-NAME Rows Cols Kind Comp-Type Interp dynmask+stream Indices | |
| ---------------------------------------------- | |
| Outputs: | |
| SEMANTIC-NAME Rows Cols Kind Comp-Type Interp dynmask+stream Indices | |
| ---------------------------------------------- | |
| END DXIL MODULE | |
| D3D12: wrote 'unsigned.cso'... | |
| D3D12: wrote 'signed.cso'... | |
| [ OK ] ComputeTest.i64tof32 (663 ms) | |
| [----------] 1 test from ComputeTest (663 ms total) | |
| [----------] Global test environment tear-down | |
| [==========] 1 test from 1 test suite ran. (666 ms total) | |
| [ PASSED ] 1 test. |
Sign up for free
to join this conversation on GitHub.
Already have an account?
Sign in to comment