Created
January 13, 2026 23:26
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Check Point 1490 devicetree parsed
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| /dts-v1/; | |
| / { | |
| device-tree { | |
| version = "2.3"; | |
| #size-cells = <0x02>; | |
| model = "Annapurna Labs Alpine Dev Board"; | |
| #address-cells = <0x02>; | |
| compatible = "annapurna-labs,alpine"; | |
| name = [00]; | |
| clock-ranges; | |
| memory { | |
| device_type = "memory"; | |
| reg = <0x00 0x00 0x00 0x20000000 0x00 0x20000000 0x00 0x20000000 0x00 0x40000000 0x00 0x20000000 0x00 0x60000000 0x00 0x20000000>; | |
| }; | |
| chosen { | |
| bootargs = "boardFlavor=alpine_db_s2 quiet console=ttyS0,115200 noExtPorts= cp_net_config=3,(00:1C:7F:7D:4E:1B)(00:1C:7F:7D:4E:1C)(00:1C:7F:7D:4E:1D) uboot_ver=90 pci=pcie_bus_perf mem=2046M ramoops.mem_address=0x7fe00000 ramoops.mem_size=0x100000 ramoops.record_size=0x10000"; | |
| }; | |
| cpus { | |
| #size-cells = <0x00>; | |
| #address-cells = <0x01>; | |
| cpu@2 { | |
| device_type = "cpu"; | |
| clocks = <0x01>; | |
| reg = <0x02>; | |
| clock-names = "cpu"; | |
| clock-frequency = <0x6553f100>; | |
| compatible = "arm,cortex-a15"; | |
| }; | |
| cpu@3 { | |
| device_type = "cpu"; | |
| clocks = <0x01>; | |
| reg = <0x03>; | |
| clock-names = "cpu"; | |
| clock-frequency = <0x6553f100>; | |
| compatible = "arm,cortex-a15"; | |
| }; | |
| cpu@1 { | |
| device_type = "cpu"; | |
| clocks = <0x01>; | |
| reg = <0x01>; | |
| clock-names = "cpu"; | |
| clock-frequency = <0x6553f100>; | |
| compatible = "arm,cortex-a15"; | |
| }; | |
| cpu@0 { | |
| device_type = "cpu"; | |
| clocks = <0x01>; | |
| reg = <0x00>; | |
| clock-names = "cpu"; | |
| clock-frequency = <0x6553f100>; | |
| compatible = "arm,cortex-a15"; | |
| }; | |
| }; | |
| hypervisor { | |
| }; | |
| soc { | |
| ranges; | |
| #size-cells = <0x02>; | |
| interrupt-parent = <0x02>; | |
| #address-cells = <0x02>; | |
| compatible = "simple-bus"; | |
| uart2 { | |
| interrupts = <0x00 0x13 0x04>; | |
| reg-io-width = <0x04>; | |
| reg-shift = <0x02>; | |
| reg = <0x00 0xfd885000 0x00 0x1000>; | |
| clock-frequency = <0x165a0bc0>; | |
| compatible = "ns16550a"; | |
| }; | |
| pbs { | |
| reg = <0x00 0xfd8a8000 0x00 0x1000>; | |
| compatible = "annapurna-labs,al-pbs"; | |
| }; | |
| pcie-internal { | |
| device_type = "pci"; | |
| ranges = <0x00 0x00 0xfbc00000 0x00 0xfbc00000 0x00 0x100000 0x2000000 0x00 0xfe000000 0x00 0xfe000000 0x00 0x1000000>; | |
| interrupt-map = <0x4000 0x00 0x00 0x01 0x02 0x00 0x2b 0x04 0x4800 0x00 0x00 0x01 0x02 0x00 0x2c 0x04>; | |
| #size-cells = <0x02>; | |
| interrupt-map-mask = <0xf800 0x00 0x00 0x07>; | |
| interrupt-parent = <0x02>; | |
| bus-range = <0x00 0x00>; | |
| #address-cells = <0x03>; | |
| #interrupt-cells = <0x01>; | |
| compatible = "annapurna-labs,al-internal-pcie"; | |
| }; | |
| board-cfg { | |
| u-boot-offset = <0x20000>; | |
| id = "alpine_db (S2-L72)"; | |
| ethernet { | |
| port3 { | |
| status = "enabled"; | |
| mode = "rgmii"; | |
| 1g-serial { | |
| duplex = "full"; | |
| speed = "1000M"; | |
| auto-neg = "disabled"; | |
| }; | |
| }; | |
| port2 { | |
| status = "enabled"; | |
| mode = "sgmii-2.5g"; | |
| 1g-serial { | |
| duplex = "full"; | |
| speed = "1000M"; | |
| force-1000base-x = "enabled"; | |
| auto-neg = "disabled"; | |
| }; | |
| }; | |
| port0 { | |
| status = "enabled"; | |
| mode = "sgmii-2.5g"; | |
| 1g-serial { | |
| duplex = "full"; | |
| speed = "1000M"; | |
| force-1000base-x = "enabled"; | |
| auto-neg = "disabled"; | |
| }; | |
| }; | |
| port1 { | |
| status = "enabled"; | |
| mode = "rgmii"; | |
| ext_phy { | |
| phy_mgmt_if = "mdc-mdio"; | |
| mdc-mdio-freq = "1.0Mhz"; | |
| auto-neg-mode = "out-of-band"; | |
| phy-addr = <0x01>; | |
| }; | |
| }; | |
| }; | |
| pcie { | |
| ep-ports; | |
| port2 { | |
| width = <0x02>; | |
| gen = <0x02>; | |
| status = "enabled"; | |
| }; | |
| port0 { | |
| width = <0x01>; | |
| gen = <0x01>; | |
| status = "enabled"; | |
| }; | |
| port1 { | |
| width = <0x01>; | |
| gen = <0x01>; | |
| status = "enabled"; | |
| }; | |
| }; | |
| pinctrl_init { | |
| pinctrl-0 = <0x04 0x05 0x06 0x07>; | |
| }; | |
| serdes { | |
| group2 { | |
| ssc = "disabled"; | |
| inv-rx-lanes; | |
| active-lanes = <0x00 0x01>; | |
| inv-tx-lanes; | |
| interface = "pcie_g2x4"; | |
| ref-clock = "right"; | |
| lane_2_params { | |
| rx { | |
| override = "disabled"; | |
| }; | |
| tx { | |
| override = "disabled"; | |
| }; | |
| }; | |
| lane_3_params { | |
| rx { | |
| override = "disabled"; | |
| }; | |
| tx { | |
| override = "disabled"; | |
| }; | |
| }; | |
| lane_1_params { | |
| rx { | |
| override = "disabled"; | |
| }; | |
| tx { | |
| override = "disabled"; | |
| }; | |
| }; | |
| lane_0_params { | |
| rx { | |
| override = "disabled"; | |
| }; | |
| tx { | |
| override = "disabled"; | |
| }; | |
| }; | |
| }; | |
| group0 { | |
| ssc = "disabled"; | |
| inv-rx-lanes; | |
| active-lanes = <0x00 0x02>; | |
| inv-tx-lanes; | |
| interface = "pcie_g2x2_pcie_g2x2"; | |
| ref-clock = "left"; | |
| lane_2_params { | |
| rx { | |
| high_freq_agc_boost = <0x00>; | |
| low_freq_agc_gain = <0x07>; | |
| dcgain = <0x00>; | |
| dfe_gain = <0x00>; | |
| dfe_4th_tap_ctrl = <0x08>; | |
| dfe_2nd_tap_ctrl = <0x08>; | |
| dfe_1st_tap_ctrl = <0x00>; | |
| dfe_3rd_tap_ctrl = <0x00>; | |
| dfe_3db_freq = <0x07>; | |
| precal_code_sel = <0x00>; | |
| override = "enabled"; | |
| }; | |
| tx { | |
| slew_rate = <0x00>; | |
| total_driver_units = <0x13>; | |
| amp = <0x01>; | |
| pre_emph = <0x00>; | |
| post_emph = <0x02>; | |
| override = "enabled"; | |
| }; | |
| }; | |
| lane_3_params { | |
| rx { | |
| override = "disabled"; | |
| }; | |
| tx { | |
| override = "disabled"; | |
| }; | |
| }; | |
| lane_1_params { | |
| rx { | |
| override = "disabled"; | |
| }; | |
| tx { | |
| override = "disabled"; | |
| }; | |
| }; | |
| lane_0_params { | |
| rx { | |
| high_freq_agc_boost = <0x00>; | |
| low_freq_agc_gain = <0x07>; | |
| dcgain = <0x00>; | |
| dfe_gain = <0x00>; | |
| dfe_4th_tap_ctrl = <0x08>; | |
| dfe_2nd_tap_ctrl = <0x08>; | |
| dfe_1st_tap_ctrl = <0x00>; | |
| dfe_3rd_tap_ctrl = <0x00>; | |
| dfe_3db_freq = <0x07>; | |
| precal_code_sel = <0x00>; | |
| override = "enabled"; | |
| }; | |
| tx { | |
| slew_rate = <0x00>; | |
| total_driver_units = <0x13>; | |
| amp = <0x01>; | |
| pre_emph = <0x00>; | |
| post_emph = <0x02>; | |
| override = "enabled"; | |
| }; | |
| }; | |
| }; | |
| group3 { | |
| ssc = "disabled"; | |
| inv-rx-lanes; | |
| active-lanes = <0x01 0x03>; | |
| inv-tx-lanes; | |
| interface = "sgmii-2.5g"; | |
| ref-clock = "156.25Mhz"; | |
| lane_2_params { | |
| rx { | |
| override = "disabled"; | |
| }; | |
| tx { | |
| override = "disabled"; | |
| }; | |
| }; | |
| lane_3_params { | |
| rx { | |
| override = "disabled"; | |
| }; | |
| tx { | |
| override = "disabled"; | |
| }; | |
| }; | |
| lane_1_params { | |
| rx { | |
| override = "disabled"; | |
| }; | |
| tx { | |
| override = "disabled"; | |
| }; | |
| }; | |
| lane_0_params { | |
| rx { | |
| override = "disabled"; | |
| }; | |
| tx { | |
| override = "disabled"; | |
| }; | |
| }; | |
| }; | |
| group1 { | |
| ssc = "disabled"; | |
| inv-rx-lanes; | |
| active-lanes = <0x00 0x01 0x02 0x03>; | |
| inv-tx-lanes; | |
| interface = "off_bp"; | |
| ref-clock = "100Mhz"; | |
| lane_2_params { | |
| rx { | |
| high_freq_agc_boost = <0x00>; | |
| low_freq_agc_gain = <0x07>; | |
| dcgain = <0x00>; | |
| dfe_gain = <0x00>; | |
| dfe_4th_tap_ctrl = <0x08>; | |
| dfe_2nd_tap_ctrl = <0x08>; | |
| dfe_1st_tap_ctrl = <0x00>; | |
| dfe_3rd_tap_ctrl = <0x00>; | |
| dfe_3db_freq = <0x07>; | |
| precal_code_sel = <0x00>; | |
| override = "enabled"; | |
| }; | |
| tx { | |
| slew_rate = <0x00>; | |
| total_driver_units = <0x13>; | |
| amp = <0x01>; | |
| pre_emph = <0x00>; | |
| post_emph = <0x02>; | |
| override = "enabled"; | |
| }; | |
| }; | |
| lane_3_params { | |
| rx { | |
| high_freq_agc_boost = <0x00>; | |
| low_freq_agc_gain = <0x07>; | |
| dcgain = <0x00>; | |
| dfe_gain = <0x00>; | |
| dfe_4th_tap_ctrl = <0x08>; | |
| dfe_2nd_tap_ctrl = <0x08>; | |
| dfe_1st_tap_ctrl = <0x00>; | |
| dfe_3rd_tap_ctrl = <0x00>; | |
| dfe_3db_freq = <0x07>; | |
| precal_code_sel = <0x00>; | |
| override = "enabled"; | |
| }; | |
| tx { | |
| slew_rate = <0x00>; | |
| total_driver_units = <0x13>; | |
| amp = <0x01>; | |
| pre_emph = <0x00>; | |
| post_emph = <0x02>; | |
| override = "enabled"; | |
| }; | |
| }; | |
| lane_1_params { | |
| rx { | |
| high_freq_agc_boost = <0x00>; | |
| low_freq_agc_gain = <0x07>; | |
| dcgain = <0x00>; | |
| dfe_gain = <0x00>; | |
| dfe_4th_tap_ctrl = <0x08>; | |
| dfe_2nd_tap_ctrl = <0x08>; | |
| dfe_1st_tap_ctrl = <0x00>; | |
| dfe_3rd_tap_ctrl = <0x00>; | |
| dfe_3db_freq = <0x07>; | |
| precal_code_sel = <0x00>; | |
| override = "enabled"; | |
| }; | |
| tx { | |
| slew_rate = <0x00>; | |
| total_driver_units = <0x13>; | |
| amp = <0x01>; | |
| pre_emph = <0x00>; | |
| post_emph = <0x02>; | |
| override = "enabled"; | |
| }; | |
| }; | |
| lane_0_params { | |
| rx { | |
| high_freq_agc_boost = <0x00>; | |
| low_freq_agc_gain = <0x07>; | |
| dcgain = <0x00>; | |
| dfe_gain = <0x00>; | |
| dfe_4th_tap_ctrl = <0x08>; | |
| dfe_2nd_tap_ctrl = <0x08>; | |
| dfe_1st_tap_ctrl = <0x00>; | |
| dfe_3rd_tap_ctrl = <0x00>; | |
| dfe_3db_freq = <0x07>; | |
| precal_code_sel = <0x00>; | |
| override = "enabled"; | |
| }; | |
| tx { | |
| slew_rate = <0x00>; | |
| total_driver_units = <0x13>; | |
| amp = <0x01>; | |
| pre_emph = <0x00>; | |
| post_emph = <0x02>; | |
| override = "enabled"; | |
| }; | |
| }; | |
| }; | |
| }; | |
| gpio_init { | |
| gpio-list = <0x00 0x00 0x00 0x01 0x00 0x00 0x02 0x00 0x00 0x03 0x00 0x00 0x18 0x00 0x00 0x26 0x00 0x00 0x27 0x00 0x00 0x2d 0x00 0x00 0x04 0x01 0x01 0x05 0x01 0x01 0x17 0x01 0x01 0x19 0x01 0x01 0x28 0x01 0x00 0x29 0x01 0x00 0x2a 0x01 0x00 0x2b 0x01 0x00 0x2c 0x01 0x00>; | |
| }; | |
| }; | |
| uart1 { | |
| interrupts = <0x00 0x12 0x04>; | |
| reg-io-width = <0x04>; | |
| reg-shift = <0x02>; | |
| reg = <0x00 0xfd884000 0x00 0x1000>; | |
| clock-frequency = <0x165a0bc0>; | |
| compatible = "ns16550a"; | |
| }; | |
| i2c-gen { | |
| interrupts = <0x00 0x08 0x04>; | |
| clocks = <0x03>; | |
| reg = <0x00 0xfd894000 0x00 0x1000>; | |
| #size-cells = <0x00>; | |
| #address-cells = <0x01>; | |
| status = "disabled"; | |
| clock-frequency = <0x61a80>; | |
| compatible = "snps,designware-i2c"; | |
| }; | |
| wdt2 { | |
| interrupts = <0x00 0x0f 0x04>; | |
| clocks = <0x03>; | |
| reg = <0x00 0xfd88e000 0x00 0x1000>; | |
| status = "disabled"; | |
| clock-names = "apb_pclk"; | |
| compatible = "arm,sp805", "arm,primecell"; | |
| }; | |
| gpio2 { | |
| interrupts = <0x00 0x04 0x04>; | |
| clocks = <0x03>; | |
| #gpio-cells = <0x02>; | |
| reg = <0x00 0xfd889000 0x00 0x1000>; | |
| baseidx = <0x10>; | |
| gpio-controller; | |
| clock-names = "apb_pclk"; | |
| compatible = "arm,pl061", "arm,primecell"; | |
| }; | |
| pmu { | |
| interrupts = <0x00 0x44 0x04 0x00 0x45 0x04 0x00 0x46 0x04 0x00 0x47 0x04>; | |
| compatible = "arm,cortex-a15-pmu"; | |
| }; | |
| uart0 { | |
| interrupts = <0x00 0x11 0x04>; | |
| reg-io-width = <0x04>; | |
| reg-shift = <0x02>; | |
| reg = <0x00 0xfd883000 0x00 0x1000>; | |
| clock-frequency = <0x165a0bc0>; | |
| compatible = "ns16550a"; | |
| }; | |
| cpu_resume { | |
| reg = <0x00 0xfbff5ec0 0x00 0x30>; | |
| compatible = "annapurna-labs,al-cpu-resume"; | |
| }; | |
| timer0 { | |
| interrupts = <0x00 0x09 0x04>; | |
| clocks = <0x03>; | |
| reg = <0x00 0xfd890000 0x00 0x1000>; | |
| status = "disabled"; | |
| clock-names = "sbclk"; | |
| compatible = "arm,sp804", "arm,primecell"; | |
| }; | |
| timer3 { | |
| interrupts = <0x00 0x0c 0x04>; | |
| clocks = <0x03>; | |
| reg = <0x00 0xfd893000 0x00 0x1000>; | |
| status = "disabled"; | |
| clock-names = "sbclk"; | |
| compatible = "arm,sp804", "arm,primecell"; | |
| }; | |
| clocks { | |
| #size-cells = <0x00>; | |
| #address-cells = <0x01>; | |
| sbclk { | |
| phandle = <0x03>; | |
| linux,phandle = <0x03>; | |
| clock-frequency = <0x165a0bc0>; | |
| compatible = "fixed-clock"; | |
| #clock-cells = <0x00>; | |
| }; | |
| cpuclk { | |
| phandle = <0x01>; | |
| linux,phandle = <0x01>; | |
| clock-frequency = <0xf4240>; | |
| compatible = "fixed-clock"; | |
| #clock-cells = <0x00>; | |
| }; | |
| nbclk { | |
| clock-frequency = <0x2faf0800>; | |
| compatible = "fixed-clock"; | |
| #clock-cells = <0x00>; | |
| }; | |
| refclk { | |
| clock-frequency = <0x5f5e100>; | |
| compatible = "fixed-clock"; | |
| #clock-cells = <0x00>; | |
| }; | |
| }; | |
| spi { | |
| interrupts = <0x00 0x17 0x04>; | |
| bus-num = <0x00>; | |
| clocks = <0x03>; | |
| num-chipselect = <0x04>; | |
| reg = <0x00 0xfd882000 0x00 0x1000>; | |
| #size-cells = <0x00>; | |
| #address-cells = <0x01>; | |
| clock-names = "sbclk"; | |
| compatible = "snps,dw-spi-mmio"; | |
| spiflash@0 { | |
| reg = <0x00>; | |
| #size-cells = <0x01>; | |
| #address-cells = <0x01>; | |
| spi-max-frequency = <0x17d7840>; | |
| compatible = "spi_flash_jedec_detection"; | |
| partition@1 { | |
| reg = <0x200000 0x200000>; | |
| label = "spi_part1"; | |
| }; | |
| partition@0 { | |
| reg = <0x00 0x200000>; | |
| label = "spi_part0"; | |
| }; | |
| partition@2 { | |
| reg = <0x400000 0xc00000>; | |
| label = "spi_part2"; | |
| }; | |
| }; | |
| }; | |
| wdt3 { | |
| interrupts = <0x00 0x10 0x04>; | |
| clocks = <0x03>; | |
| reg = <0x00 0xfd88f000 0x00 0x1000>; | |
| status = "disabled"; | |
| clock-names = "apb_pclk"; | |
| compatible = "arm,sp805", "arm,primecell"; | |
| }; | |
| gpio5 { | |
| interrupts = <0x00 0x07 0x04>; | |
| clocks = <0x03>; | |
| #gpio-cells = <0x02>; | |
| reg = <0x00 0xfd897000 0x00 0x1000>; | |
| baseidx = <0x28>; | |
| gpio-controller; | |
| clock-names = "apb_pclk"; | |
| compatible = "arm,pl061", "arm,primecell"; | |
| }; | |
| pcie-external2 { | |
| device_type = "pci"; | |
| ranges = <0x00 0x00 0xfba00000 0x00 0xfba00000 0x00 0x200000 0x1000000 0x00 0x30000 0x00 0xf0000000 0x00 0x10000 0x2000000 0x00 0xf0010000 0x00 0xf0010000 0x00 0x7ff0000>; | |
| interrupt-map = <0x00 0x00 0x00 0x01 0x02 0x00 0x2a 0x04>; | |
| reg = <0x00 0xfd840000 0x00 0x20000>; | |
| #size-cells = <0x02>; | |
| interrupt-map-mask = <0x00 0x00 0x00 0x07>; | |
| interrupt-parent = <0x02>; | |
| bus-range = <0x00 0xff>; | |
| #address-cells = <0x03>; | |
| #interrupt-cells = <0x01>; | |
| compatible = "annapurna-labs,al-pci"; | |
| }; | |
| timer2 { | |
| interrupts = <0x00 0x0b 0x04>; | |
| clocks = <0x03>; | |
| reg = <0x00 0xfd892000 0x00 0x1000>; | |
| status = "disabled"; | |
| clock-names = "sbclk"; | |
| compatible = "arm,sp804", "arm,primecell"; | |
| }; | |
| mc { | |
| reg = <0x00 0xfb080000 0x00 0x10000>; | |
| compatible = "annapurna-labs,al-mc"; | |
| }; | |
| wdt1 { | |
| interrupts = <0x00 0x0e 0x04>; | |
| clocks = <0x03>; | |
| reg = <0x00 0xfd88d000 0x00 0x1000>; | |
| status = "disabled"; | |
| clock-names = "apb_pclk"; | |
| compatible = "arm,sp805", "arm,primecell"; | |
| }; | |
| i2c-pld { | |
| interrupts = <0x00 0x15 0x04>; | |
| clocks = <0x03>; | |
| reg = <0x00 0xfd880000 0x00 0x1000>; | |
| #size-cells = <0x00>; | |
| #address-cells = <0x01>; | |
| clock-frequency = <0x61a80>; | |
| compatible = "snps,designware-i2c"; | |
| rtc@68 { | |
| reg = <0x68>; | |
| compatible = "ds1337"; | |
| }; | |
| u59@22 { | |
| reg = <0x22>; | |
| compatible = "tca9555"; | |
| }; | |
| u18@2B { | |
| reg = <0x2b>; | |
| compatible = "nct7802y"; | |
| }; | |
| u68@24 { | |
| reg = <0x24>; | |
| compatible = "tca9555"; | |
| }; | |
| u71@21 { | |
| reg = <0x21>; | |
| compatible = "pcf8575"; | |
| }; | |
| u26@2C { | |
| reg = <0x2c>; | |
| compatible = "nct7802y"; | |
| }; | |
| u70@20 { | |
| reg = <0x20>; | |
| compatible = "pcf8575"; | |
| }; | |
| }; | |
| gic_main { | |
| interrupts = <0x01 0x09 0xf04>; | |
| interrupt-controller; | |
| reg = <0x00 0xfb001000 0x00 0x1000 0x00 0xfb002000 0x00 0x2000 0x00 0xfb004000 0x00 0x1000 0x00 0xfb006000 0x00 0x2000>; | |
| #size-cells = <0x00>; | |
| #address-cells = <0x00>; | |
| phandle = <0x02>; | |
| linux,phandle = <0x02>; | |
| #interrupt-cells = <0x03>; | |
| compatible = "arm,cortex-a15-gic"; | |
| }; | |
| pinctrl { | |
| reg = <0x00 0xfd8a8000 0x00 0x1000>; | |
| compatible = "annapurna-labs,al-pinctrl"; | |
| if_gpio9 { | |
| arg = <0x09>; | |
| id = "if_gpio"; | |
| }; | |
| if_gpio28 { | |
| arg = <0x1c>; | |
| id = "if_gpio"; | |
| }; | |
| if_nand_8 { | |
| arg = <0x00>; | |
| phandle = <0x04>; | |
| linux,phandle = <0x04>; | |
| id = "if_nand_8"; | |
| }; | |
| if_nand_cs_0 { | |
| arg = <0x00>; | |
| phandle = <0x05>; | |
| linux,phandle = <0x05>; | |
| id = "if_nand_cs_0"; | |
| }; | |
| if_spim_a_ss_1 { | |
| arg = <0x00>; | |
| id = "if_spim_a_ss_1"; | |
| }; | |
| if_sram_cs_0 { | |
| arg = <0x00>; | |
| id = "if_sram_cs_0"; | |
| }; | |
| if_ulpi_0_rst_n { | |
| arg = <0x00>; | |
| id = "if_ulpi_0_rst_n"; | |
| }; | |
| if_gpio27 { | |
| arg = <0x1b>; | |
| id = "if_gpio"; | |
| }; | |
| if_nand_cs_1 { | |
| arg = <0x00>; | |
| id = "if_nand_cs_1"; | |
| }; | |
| if_pci_ep_int_a { | |
| arg = <0x00>; | |
| id = "if_pci_ep_int_a"; | |
| }; | |
| if_eth_gpio { | |
| arg = <0x00>; | |
| id = "if_eth_gpio"; | |
| }; | |
| if_gpio2 { | |
| arg = <0x02>; | |
| id = "if_gpio"; | |
| }; | |
| if_nor_wp { | |
| arg = <0x00>; | |
| id = "if_nor_wp"; | |
| }; | |
| if_gpio22 { | |
| arg = <0x16>; | |
| id = "if_gpio"; | |
| }; | |
| if_gpio42 { | |
| arg = <0x2a>; | |
| id = "if_gpio"; | |
| }; | |
| if_gpio16 { | |
| arg = <0x10>; | |
| id = "if_gpio"; | |
| }; | |
| if_gpio15 { | |
| arg = <0x0f>; | |
| id = "if_gpio"; | |
| }; | |
| if_gpio14 { | |
| arg = <0x0e>; | |
| id = "if_gpio"; | |
| }; | |
| if_gpio7 { | |
| arg = <0x07>; | |
| id = "if_gpio"; | |
| }; | |
| if_gpio11 { | |
| arg = <0x0b>; | |
| id = "if_gpio"; | |
| }; | |
| if_eth_leds { | |
| arg = <0x00>; | |
| id = "if_eth_leds"; | |
| }; | |
| if_gpio18 { | |
| arg = <0x12>; | |
| id = "if_gpio"; | |
| }; | |
| if_gpio4 { | |
| arg = <0x04>; | |
| id = "if_gpio"; | |
| }; | |
| if_gpio12 { | |
| arg = <0x0c>; | |
| id = "if_gpio"; | |
| }; | |
| if_gpio24 { | |
| arg = <0x18>; | |
| id = "if_gpio"; | |
| }; | |
| if_ulpi_1_b { | |
| arg = <0x00>; | |
| id = "if_ulpi_1_b"; | |
| }; | |
| if_ulpi_1_rst_n { | |
| arg = <0x00>; | |
| id = "if_ulpi_1_rst_n"; | |
| }; | |
| if_gpio34 { | |
| arg = <0x22>; | |
| id = "if_gpio"; | |
| }; | |
| if_gpio20 { | |
| arg = <0x14>; | |
| id = "if_gpio"; | |
| }; | |
| if_nor_8 { | |
| arg = <0x00>; | |
| id = "if_nor_8"; | |
| }; | |
| if_sram_8 { | |
| arg = <0x00>; | |
| id = "if_sram_8"; | |
| }; | |
| if_nand_cs_2 { | |
| arg = <0x00>; | |
| id = "if_nand_cs_2"; | |
| }; | |
| if_sram_cs_2 { | |
| arg = <0x00>; | |
| id = "if_sram_cs_2"; | |
| }; | |
| if_nor_16 { | |
| arg = <0x00>; | |
| id = "if_nor_16"; | |
| }; | |
| if_gpio43 { | |
| arg = <0x2b>; | |
| id = "if_gpio"; | |
| }; | |
| if_gpio38 { | |
| arg = <0x26>; | |
| id = "if_gpio"; | |
| }; | |
| if_gpio1 { | |
| arg = <0x01>; | |
| id = "if_gpio"; | |
| }; | |
| if_gpio25 { | |
| arg = <0x19>; | |
| id = "if_gpio"; | |
| }; | |
| if_nor_cs_1 { | |
| arg = <0x00>; | |
| id = "if_nor_cs_1"; | |
| }; | |
| if_gpio3 { | |
| arg = <0x03>; | |
| id = "if_gpio"; | |
| }; | |
| if_gpio5 { | |
| arg = <0x05>; | |
| id = "if_gpio"; | |
| }; | |
| if_gpio21 { | |
| arg = <0x15>; | |
| id = "if_gpio"; | |
| }; | |
| if_gpio31 { | |
| arg = <0x1f>; | |
| id = "if_gpio"; | |
| }; | |
| if_gpio26 { | |
| arg = <0x1a>; | |
| id = "if_gpio"; | |
| }; | |
| if_gpio19 { | |
| arg = <0x13>; | |
| id = "if_gpio"; | |
| }; | |
| if_sram_cs_3 { | |
| arg = <0x00>; | |
| id = "if_sram_cs_3"; | |
| }; | |
| if_gpio41 { | |
| arg = <0x29>; | |
| id = "if_gpio"; | |
| }; | |
| if_gpio10 { | |
| arg = <0x0a>; | |
| id = "if_gpio"; | |
| }; | |
| if_sata_1_leds { | |
| arg = <0x00>; | |
| id = "if_sata_1_leds"; | |
| }; | |
| if_nand_wp { | |
| arg = <0x00>; | |
| id = "if_nand_wp"; | |
| }; | |
| if_gpio17 { | |
| arg = <0x11>; | |
| id = "if_gpio"; | |
| }; | |
| if_nor_cs_2 { | |
| arg = <0x00>; | |
| id = "if_nor_cs_2"; | |
| }; | |
| if_sram_cs_1 { | |
| arg = <0x00>; | |
| id = "if_sram_cs_1"; | |
| }; | |
| if_gpio32 { | |
| arg = <0x20>; | |
| id = "if_gpio"; | |
| }; | |
| if_gpio23 { | |
| arg = <0x17>; | |
| id = "if_gpio"; | |
| }; | |
| if_gpio35 { | |
| arg = <0x23>; | |
| id = "if_gpio"; | |
| }; | |
| if_gpio29 { | |
| arg = <0x1d>; | |
| id = "if_gpio"; | |
| }; | |
| if_pci_ep_reset_out { | |
| arg = <0x00>; | |
| id = "if_pci_ep_reset_out"; | |
| }; | |
| if_gpio40 { | |
| arg = <0x28>; | |
| id = "if_gpio"; | |
| }; | |
| if_nand_cs_3 { | |
| arg = <0x00>; | |
| id = "if_nand_cs_3"; | |
| }; | |
| if_gpio0 { | |
| arg = <0x00>; | |
| id = "if_gpio"; | |
| }; | |
| if_gpio36 { | |
| arg = <0x24>; | |
| id = "if_gpio"; | |
| }; | |
| if_spim_a_ss_3 { | |
| arg = <0x00>; | |
| id = "if_spim_a_ss_3"; | |
| }; | |
| if_gpio30 { | |
| arg = <0x1e>; | |
| id = "if_gpio"; | |
| }; | |
| if_uart_2 { | |
| arg = <0x00>; | |
| phandle = <0x07>; | |
| linux,phandle = <0x07>; | |
| id = "if_uart_2"; | |
| }; | |
| if_nor_cs_0 { | |
| arg = <0x00>; | |
| id = "if_nor_cs_0"; | |
| }; | |
| if_uart_3 { | |
| arg = <0x00>; | |
| id = "if_uart_3"; | |
| }; | |
| if_nor_cs_3 { | |
| arg = <0x00>; | |
| id = "if_nor_cs_3"; | |
| }; | |
| if_gpio37 { | |
| arg = <0x25>; | |
| id = "if_gpio"; | |
| }; | |
| if_sram_16 { | |
| arg = <0x00>; | |
| id = "if_sram_16"; | |
| }; | |
| if_gpio39 { | |
| arg = <0x27>; | |
| id = "if_gpio"; | |
| }; | |
| if_spim_a_ss_2 { | |
| arg = <0x00>; | |
| id = "if_spim_a_ss_2"; | |
| }; | |
| if_gpio8 { | |
| arg = <0x08>; | |
| id = "if_gpio"; | |
| }; | |
| if_uart_1 { | |
| arg = <0x00>; | |
| phandle = <0x06>; | |
| linux,phandle = <0x06>; | |
| id = "if_uart_1"; | |
| }; | |
| if_sata_0_leds { | |
| arg = <0x00>; | |
| id = "if_sata_0_leds"; | |
| }; | |
| if_uart_1_modem { | |
| arg = <0x00>; | |
| id = "if_uart_1_modem"; | |
| }; | |
| if_gpio13 { | |
| arg = <0x0d>; | |
| id = "if_gpio"; | |
| }; | |
| if_gpio33 { | |
| arg = <0x21>; | |
| id = "if_gpio"; | |
| }; | |
| if_nand_16 { | |
| arg = <0x00>; | |
| id = "if_nand_16"; | |
| }; | |
| if_i2c_gen { | |
| arg = <0x00>; | |
| id = "if_i2c_gen"; | |
| }; | |
| if_gpio6 { | |
| arg = <0x06>; | |
| id = "if_gpio"; | |
| }; | |
| }; | |
| gpio0 { | |
| interrupts = <0x00 0x02 0x04>; | |
| clocks = <0x03>; | |
| #gpio-cells = <0x02>; | |
| reg = <0x00 0xfd887000 0x00 0x1000>; | |
| baseidx = <0x00>; | |
| gpio-controller; | |
| clock-names = "apb_pclk"; | |
| compatible = "arm,pl061", "arm,primecell"; | |
| }; | |
| serdes { | |
| reg = <0x00 0xfd8c0000 0x00 0x1000>; | |
| compatible = "annapurna-labs,al-serdes"; | |
| }; | |
| pcie-external1 { | |
| device_type = "pci"; | |
| ranges = <0x00 0x00 0xfb800000 0x00 0xfb800000 0x00 0x200000 0x1000000 0x00 0x20000 0x00 0xe8000000 0x00 0x10000 0x2000000 0x00 0xe8010000 0x00 0xe8010000 0x00 0x7ff0000>; | |
| interrupt-map = <0x00 0x00 0x00 0x01 0x02 0x00 0x29 0x04>; | |
| reg = <0x00 0xfd820000 0x00 0x20000>; | |
| #size-cells = <0x02>; | |
| interrupt-map-mask = <0x00 0x00 0x00 0x07>; | |
| interrupt-parent = <0x02>; | |
| bus-range = <0x00 0xff>; | |
| #address-cells = <0x03>; | |
| status = "disabled"; | |
| #interrupt-cells = <0x01>; | |
| compatible = "annapurna-labs,al-pci"; | |
| }; | |
| pcie-external0 { | |
| device_type = "pci"; | |
| ranges = <0x00 0x00 0xfb600000 0x00 0xfb600000 0x00 0x200000 0x1000000 0x00 0x10000 0x00 0xe0000000 0x00 0x10000 0x2000000 0x00 0xe0010000 0x00 0xe0010000 0x00 0x7ff0000>; | |
| interrupt-map = <0x00 0x00 0x00 0x01 0x02 0x00 0x28 0x04>; | |
| reg = <0x00 0xfd800000 0x00 0x20000>; | |
| #size-cells = <0x02>; | |
| interrupt-map-mask = <0x00 0x00 0x00 0x07>; | |
| interrupt-parent = <0x02>; | |
| bus-range = <0x00 0xff>; | |
| #address-cells = <0x03>; | |
| status = "disabled"; | |
| #interrupt-cells = <0x01>; | |
| compatible = "annapurna-labs,al-pci"; | |
| }; | |
| arch-timer { | |
| interrupts = <0x01 0x0d 0xf08 0x01 0x0e 0xf08 0x01 0x0b 0xf08 0x01 0x0a 0xf08>; | |
| clock-frequency = <0x2faf080>; | |
| compatible = "arm,cortex-a15-timer", "arm,armv7-timer"; | |
| }; | |
| ccu { | |
| io_coherency = <0x01>; | |
| reg = <0x00 0xfb090000 0x00 0x10000>; | |
| compatible = "annapurna-labs,al-ccu"; | |
| }; | |
| uart3 { | |
| interrupts = <0x00 0x14 0x04>; | |
| reg-io-width = <0x04>; | |
| reg-shift = <0x02>; | |
| reg = <0x00 0xfd886000 0x00 0x1000>; | |
| status = "disabled"; | |
| clock-frequency = <0x165a0bc0>; | |
| compatible = "ns16550a"; | |
| }; | |
| gpio4 { | |
| interrupts = <0x00 0x06 0x04>; | |
| clocks = <0x03>; | |
| #gpio-cells = <0x02>; | |
| reg = <0x00 0xfd88b000 0x00 0x1000>; | |
| baseidx = <0x20>; | |
| gpio-controller; | |
| clock-names = "apb_pclk"; | |
| compatible = "arm,pl061", "arm,primecell"; | |
| }; | |
| msix { | |
| interrupts = <0x00 0x60 0x01 0x00 0x9f 0x01>; | |
| reg = <0x00 0xfbe00000 0x00 0x100000>; | |
| compatible = "annapurna-labs,al-msix"; | |
| }; | |
| timer1 { | |
| interrupts = <0x00 0x0a 0x04>; | |
| clocks = <0x03>; | |
| reg = <0x00 0xfd891000 0x00 0x1000>; | |
| status = "disabled"; | |
| clock-names = "sbclk"; | |
| compatible = "arm,sp804", "arm,primecell"; | |
| }; | |
| gpio1 { | |
| interrupts = <0x00 0x03 0x04>; | |
| clocks = <0x03>; | |
| #gpio-cells = <0x02>; | |
| reg = <0x00 0xfd888000 0x00 0x1000>; | |
| baseidx = <0x08>; | |
| gpio-controller; | |
| clock-names = "apb_pclk"; | |
| compatible = "arm,pl061", "arm,primecell"; | |
| }; | |
| gpio3 { | |
| interrupts = <0x00 0x05 0x04>; | |
| clocks = <0x03>; | |
| #gpio-cells = <0x02>; | |
| reg = <0x00 0xfd88a000 0x00 0x1000>; | |
| baseidx = <0x18>; | |
| gpio-controller; | |
| clock-names = "apb_pclk"; | |
| compatible = "arm,pl061", "arm,primecell"; | |
| }; | |
| thermal { | |
| reg = <0x00 0xfd860a00 0x00 0x100>; | |
| compatible = "annapurna-labs,al-thermal"; | |
| }; | |
| nb_service { | |
| interrupts = <0x00 0x40 0x04 0x00 0x41 0x04 0x00 0x42 0x04 0x00 0x43 0x04>; | |
| dev_ord_relax = <0x00>; | |
| reg = <0x00 0xfb070000 0x00 0x10000>; | |
| compatible = "annapurna-labs,al-nb-service"; | |
| }; | |
| nor_flash { | |
| reg = <0x00 0xf4000000 0x00 0x4000000>; | |
| device-width = <0x01>; | |
| bank-width = <0x01>; | |
| status = "disabled"; | |
| compatible = "cfi-flash"; | |
| }; | |
| nand-flash { | |
| interrupts = <0x00 0x01 0x04>; | |
| reg = <0x00 0xfa100000 0x00 0x202000>; | |
| #size-cells = <0x01>; | |
| #address-cells = <0x01>; | |
| compatible = "annapurna-labs,al-nand"; | |
| partition@4 { | |
| reg = <0xef80000 0x1000000>; | |
| label = "linux_kernel2"; | |
| }; | |
| partition@1 { | |
| reg = <0x200000 0x100000>; | |
| label = "device_tree"; | |
| }; | |
| partition@3 { | |
| reg = <0x1380000 0xdc00000>; | |
| label = "ubifs"; | |
| }; | |
| partition@8 { | |
| reg = <0x69f80000 0x100000>; | |
| label = "preset"; | |
| }; | |
| partition@0 { | |
| reg = <0x00 0x300000>; | |
| label = "al_boot"; | |
| }; | |
| partition@9 { | |
| reg = <0x6a080000 0x100000>; | |
| label = "adsl"; | |
| }; | |
| partition@7 { | |
| reg = <0x29f80000 0x40000000>; | |
| label = "logs"; | |
| }; | |
| partition@6 { | |
| reg = <0x1db80000 0xc400000>; | |
| label = "default-sw"; | |
| }; | |
| partition@10 { | |
| reg = <0x6a180000 0x15e80000>; | |
| label = "storage"; | |
| }; | |
| partition@2 { | |
| reg = <0x380000 0x1000000>; | |
| label = "linux_kernel"; | |
| }; | |
| partition@5 { | |
| reg = <0xff80000 0xdc00000>; | |
| label = "ubifs-2"; | |
| }; | |
| }; | |
| wdt0 { | |
| interrupts = <0x00 0x0d 0x04>; | |
| clocks = <0x03>; | |
| reg = <0x00 0xfd88c000 0x00 0x1000>; | |
| clock-names = "apb_pclk"; | |
| compatible = "arm,sp805", "arm,primecell"; | |
| }; | |
| }; | |
| aliases { | |
| }; | |
| }; | |
| }; |
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