Blackhawk95/papers.txt

## papers.txt


However, NVM has certain disadvantages for write references,
due to its high dynamic energy consumption for writes and low bandwidth compared to DRAM writes.


Literature review:

(~ ~)NVM & Hybrid memory technology in Cache
	*EqualWrites: Reducing Intra-Set Write Variations for Enhancing Lifetime of Non-Volatile Caches
		~ A technique for mitigating intra-set Write Variation by counting number of writes on each memory cell
		~ It performs swap on memory elements with largest and smallest counter value
	*Dynamic Adaptive Replacement Policy in Shared Last-Level Cache of DRAM/PCM Hybrid Memory for Big Data Storage
		~ PCM and DRAM as contiguous memory space
		~ Dynamic adaptive replacement policy, which adapts for each type of memory (LRU for PCM and MRU for DRAM)

(O O)NVM memory technology as main memory utilizing OS based support
	*A Wear-Leveling-Aware Dynamic Stack for PCM Memory in Embedded Systems
		~ A wear leveling aware dynamic stack to extend PCM’s lifetime when adopted in embedded systems as main memory
		~ The memory space is circularly allocated to stack frames leading to even usage of PCM memory
	*Wear-leveling for PCM main memory on embedded system via page management and process scheduling (2014)
		~ Making OS aware about of NVM memory and provide software based memory management in embedded systems
		~ No extra hardware support

(- -)DRAM/NVM hybrid memory technology as main memory
	*Improving PCM Endurance with Randomized Address Remapping in Hybrid Memory System
		~ A new hybrid memory architecture, where DRAM serves as cache for PCM main memory.
		~ Uses Randomized Address Remapping to prevent malicious attacks
	*Access pattern aware data placement for hybrid DRAM/NVM (2017)
		~ Access-aware placement of objects in the application code for hybrid memories

(X X)Error correction mechanisms to improve write endurance in NVM


Cicuit Level
	*NVSim: A Circuit-Level Performance, Energy, and Area Model for Emerging Nonvolatile Memory (2012)
		~READ AND UPDATE

(@ @)Models for both types of memory
[16] Doller E. Forging a future in memory—new technologies, new markets, new applications. In: IEEE 2010 Hot Chips Symposium; 22–24 August 2010; Stanford, CA, USA. New York, NY, USA: IEEE. pp. 1-28.

[18] Hassan A, Vandierendonck H, Nikolopoulos DS. Software-managed energy-eﬃcient hybrid DRAM/NVM main memory. In: ACM 2015 Computing Frontiers Conference; 18–21 May 2015; Ischia, Italy. New York, NY, USA: ACM. pp. 23:1-23:8.
[19] Suzuki K, Swanson S. The non-volatile memory technology database (nvmdb). Technical Report CS2015-1011, Department of Computer Science & Engineering, San Diego, CA, USA: University of California, May 2015. http://nvmdb.ucsd.edu.


	However, NVM has certain disadvantages for write references,
	due to its high dynamic energy consumption for writes and low bandwidth compared to DRAM writes.




	Literature review:

	(~ ~)NVM & Hybrid memory technology in Cache
	*EqualWrites: Reducing Intra-Set Write Variations for Enhancing Lifetime of Non-Volatile Caches
	~ A technique for mitigating intra-set Write Variation by counting number of writes on each memory cell
	~ It performs swap on memory elements with largest and smallest counter value
	*Dynamic Adaptive Replacement Policy in Shared Last-Level Cache of DRAM/PCM Hybrid Memory for Big Data Storage
	~ PCM and DRAM as contiguous memory space
	~ Dynamic adaptive replacement policy, which adapts for each type of memory (LRU for PCM and MRU for DRAM)

	(O O)NVM memory technology as main memory utilizing OS based support
	*A Wear-Leveling-Aware Dynamic Stack for PCM Memory in Embedded Systems
	~ A wear leveling aware dynamic stack to extend PCM’s lifetime when adopted in embedded systems as main memory
	~ The memory space is circularly allocated to stack frames leading to even usage of PCM memory
	*Wear-leveling for PCM main memory on embedded system via page management and process scheduling (2014)
	~ Making OS aware about of NVM memory and provide software based memory management in embedded systems
	~ No extra hardware support

	(- -)DRAM/NVM hybrid memory technology as main memory
	*Improving PCM Endurance with Randomized Address Remapping in Hybrid Memory System
	~ A new hybrid memory architecture, where DRAM serves as cache for PCM main memory.
	~ Uses Randomized Address Remapping to prevent malicious attacks
	*Access pattern aware data placement for hybrid DRAM/NVM (2017)
	~ Access-aware placement of objects in the application code for hybrid memories

	(X X)Error correction mechanisms to improve write endurance in NVM


	Cicuit Level
	*NVSim: A Circuit-Level Performance, Energy, and Area Model for Emerging Nonvolatile Memory (2012)
	~READ AND UPDATE

	(@ @)Models for both types of memory
	[16] Doller E. Forging a future in memory—new technologies, new markets, new applications. In: IEEE 2010 Hot Chips Symposium; 22–24 August 2010; Stanford, CA, USA. New York, NY, USA: IEEE. pp. 1-28.

	[18] Hassan A, Vandierendonck H, Nikolopoulos DS. Software-managed energy-eﬃcient hybrid DRAM/NVM main memory. In: ACM 2015 Computing Frontiers Conference; 18–21 May 2015; Ischia, Italy. New York, NY, USA: ACM. pp. 23:1-23:8.
	[19] Suzuki K, Swanson S. The non-volatile memory technology database (nvmdb). Technical Report CS2015-1011, Department of Computer Science & Engineering, San Diego, CA, USA: University of California, May 2015. http://nvmdb.ucsd.edu.
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